AM62Px MCU+ SDK  09.01.00
csl_dssVideoPort.h
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33 
48 #ifndef CSL_DSSVIDEOPORT_H_
49 #define CSL_DSSVIDEOPORT_H_
50 
51 /* ========================================================================== */
52 /* Include Files */
53 /* ========================================================================== */
54 
55 /* None */
56 
57 #ifdef __cplusplus
58 extern "C" {
59 #endif
60 
61 /* ========================================================================== */
62 /* Macros & Typedefs */
63 /* ========================================================================== */
64 
71 
80 #define CSL_DSS_VP_CSC_POS_AFTER_GAMMA \
81  ((uint32_t) CSL_DSS_VP1_CONFIG_COLORCONVPOS_VAL_AFTERGAMMA)
82 
83 #define CSL_DSS_VP_CSC_POS_BEFORE_GAMMA \
84  ((uint32_t) CSL_DSS_VP1_CONFIG_COLORCONVPOS_VAL_BEFOREGAMMA)
85 
95 #define CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_LOW \
96  ((uint32_t) CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_LOWLEVEL)
97 
98 #define CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_HIGH \
99  ((uint32_t) CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_HIGHLEVEL)
100 
101 #define CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_UNCHANGED \
102  ((uint32_t) CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_UNCHANGED)
103 
112 #define CSL_DSS_VP_TDM_CYCLE_1PERPIXEL \
113  ((uint32_t) CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_1CYCPERPIX)
114 
115 #define CSL_DSS_VP_TDM_CYCLE_2PERPIXEL \
116  ((uint32_t) CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_2CYCPERPIX)
117 
118 #define CSL_DSS_VP_TDM_CYCLE_3PERPIXEL \
119  ((uint32_t) CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_3CYCPERPIX)
120 
121 #define CSL_DSS_VP_TDM_CYCLE_3PER2PIXEL \
122  ((uint32_t) CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_3CYCPER2PIX)
123 
132 #define CSL_DSS_VP_TDM_PARALLEL_OUTPUT_8BIT \
133  ((uint32_t) CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_8BPARAINT)
134 
135 #define CSL_DSS_VP_TDM_PARALLEL_OUTPUT_9BIT \
136  ((uint32_t) CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_9BPARAINT)
137 
138 #define CSL_DSS_VP_TDM_PARALLEL_OUTPUT_12BIT \
139  ((uint32_t) CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_12BPARAINT)
140 
141 #define CSL_DSS_VP_TDM_PARALLEL_OUTPUT_16BIT \
142  ((uint32_t) CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_16BPARAINT)
143 
152 #define CSL_DSS_VP_HVSYNC_NOT_ALIGNED \
153  ((uint32_t) CSL_DSS_VP1_POL_FREQ_ALIGN_VAL_NOTALIGNED)
154 
155 #define CSL_DSS_VP_HVSYNC_ALIGNED \
156  ((uint32_t) CSL_DSS_VP1_POL_FREQ_ALIGN_VAL_ALIGNED)
157 
167 #define CSL_DSS_VP_HVCLK_CONTROL_OFF \
168  ((uint32_t) CSL_DSS_VP1_POL_FREQ_ONOFF_VAL_DOPEDPCK)
169 
170 #define CSL_DSS_VP_HVCLK_CONTROL_ON \
171  ((uint32_t) CSL_DSS_VP1_POL_FREQ_ONOFF_VAL_DBIT16)
172 
182 #define CSL_DSS_VP_LPP_DELTA_ZERO \
183  ((uint32_t) CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_SAME)
184 
185 #define CSL_DSS_VP_LPP_DELTA_PLUSONE \
186  ((uint32_t) CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_PLUSONE)
187 
188 #define CSL_DSS_VP_LPP_DELTA_MINUSONE \
189  ((uint32_t) CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_MINUSONE)
190 
200 #define CSL_DSS_VP_FID_FIRST_EVEN \
201  ((uint32_t) CSL_DSS_VP1_CONFIG_FIDFIRST_VAL_EVEN)
202 
203 #define CSL_DSS_VP_FID_FIRST_ODD \
204  ((uint32_t) CSL_DSS_VP1_CONFIG_FIDFIRST_VAL_ODD)
205 
214 #define CSL_DSS_VP_SAFETY_REGION_0 ((uint32_t) 0x0U)
215 
216 #define CSL_DSS_VP_SAFETY_REGION_1 ((uint32_t) 0x1U)
217 
218 #define CSL_DSS_VP_SAFETY_REGION_2 ((uint32_t) 0x2U)
219 
220 #define CSL_DSS_VP_SAFETY_REGION_3 ((uint32_t) 0x3U)
221 
222 #define CSL_DSS_VP_SAFETY_REGION_MAX ((uint32_t) 0x4U)
223 
224 #define CSL_DSS_VP_SAFETY_REGION_INVALID ((uint32_t) 0xFFU)
225 
235 #define CSL_DSS_VP_OLDI_MAP_TYPE_A \
236  ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_A)
237 
238 #define CSL_DSS_VP_OLDI_MAP_TYPE_B \
239  ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_B)
240 
241 #define CSL_DSS_VP_OLDI_MAP_TYPE_C \
242  ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_C)
243 
244 #define CSL_DSS_VP_OLDI_MAP_TYPE_D \
245  ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_D)
246 
247 #define CSL_DSS_VP_OLDI_MAP_TYPE_E \
248  ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_E)
249 
250 #define CSL_DSS_VP_OLDI_MAP_TYPE_F \
251  ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_F)
252 
265 #define CSL_DSS_VP_OLDI_BIT_DEPTH_18_BITS \
266  ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MSB_VAL_18B)
267 
268 #define CSL_DSS_VP_OLDI_BIT_DEPTH_24_BITS \
269  ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_MSB_VAL_24B)
270 
280 #define CSL_DSS_VP_OLDI_DUALMODESYNC_ENABLE \
281  ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_DUALMODESYNC_VAL_ENABLE)
282 
283 #define CSL_DSS_VP_OLDI_DUALMODESYNC_DISABLE \
284  ((uint32_t) CSL_DSS_VP1_DSS_OLDI_CFG_DUALMODESYNC_VAL_DISABLE)
285 
287 /* ========================================================================== */
288 /* Structure Declarations */
289 /* ========================================================================== */
290 
294 typedef struct
295 {
296  uint32_t gammaEnable;
300  uint32_t gammaData[CSL_DSS_NUM_LUT_ENTRIES];
303 
307 typedef struct
308 {
309  uint32_t tdmEnable;
316  uint32_t tdmCycleFormat;
319  uint32_t tdmParallelMode;
359 
364 typedef struct
365 {
366  uint32_t actVidPolarity;
372  uint32_t hsPolarity;
375  uint32_t vsPolarity;
379 
383 typedef struct
384 {
385  uint32_t hVAlign;
388  uint32_t hVClkControl;
391  uint32_t hVClkRiseFall;
394  uint32_t acBI;
398  uint32_t acB;
404  uint32_t vSyncGated;
408  uint32_t hSyncGated;
412  uint32_t pixelClockGated;
416  uint32_t pixelDataGated;
420  uint32_t pixelGated;
426 
430 typedef struct
431 {
499  uint32_t dvoFormat;
501  uint32_t cscRange;
503  uint32_t videoIfWidth;
515  uint32_t fidFirst;
520 
524 typedef struct
525 {
526  uint32_t hFrontPorch;
532  uint32_t hBackPorch;
538  uint32_t hSyncLen;
543  uint32_t vFrontPorch;
549  uint32_t vBackPorch;
556  uint32_t vSyncLen;
564 
568 typedef struct
569 {
570  uint32_t oldiMapType;
575  uint32_t dssBitDepth;
578  uint32_t dualModeSync;
583 
584 /* ========================================================================== */
585 /* Function Declarations */
586 /* ========================================================================== */
587 
597 void CSL_dssVpEnable(CSL_dss_vpRegs *vpRegs, uint32_t enable);
598 
608 
619  const CSL_DssVpLcdTdmCfg *lcdTdmCfg);
620 
630  uint32_t lineNum);
631 
643  const CSL_DssVpLcdOpTimingCfg *lcdCfg);
644 
663  const CSL_DssVpLcdBlankTimingCfg *blankCfg,
664  uint32_t dvoFormat,
665  uint32_t scanFormat,
666  uint32_t isCustomTiming);
667 
678  CSL_dss_vpRegs *vpRegs,
679  const CSL_DssVpLcdAdvSignalCfg *advSignalCfg);
680 
691  CSL_dss_vpRegs *vpRegs,
692  const CSL_DssVpLcdSignalPolarityCfg *polarityCfg);
693 
704  const CSL_DssVpGammaCfg *gammaCfg);
705 
721  const CSL_DssCscCoeff *cscCoeff,
722  uint32_t cscPos,
723  uint32_t cscEnable);
724 
734  uint32_t signSeedVal);
735 
747  uint32_t referenceSign,
748  uint32_t regionId);
749 
762  const CSL_DssSafetyChkCfg *safetyCfg,
763  uint32_t regionId);
764 
775 uint32_t CSL_dssVpGetSafetySign(const CSL_dss_vpRegs *vpRegs,
776  uint32_t regionId);
777 
785 void CSL_dssVpOldiReset(const CSL_dss_vpRegs *vpRegs);
786 
797  const CSL_DssVpOldiCfg *oldiCfg);
798 
808 void CSL_dssVpOldiEnable(CSL_dss_vpRegs *vpRegs, uint32_t enable);
809 
810 /* ========================================================================== */
811 /* Static Function Declarations */
812 /* ========================================================================== */
813 
820 static inline void CSL_dssVpGammaCfgInit(
821  CSL_DssVpGammaCfg *gammaCfg);
822 
829 static inline void CSL_dssVpLcdTdmCfgInit(
830  CSL_DssVpLcdTdmCfg *tdmCfg);
831 
838 static inline void CSL_dssVpLcdSignalPolarityCfgInit(
839  CSL_DssVpLcdSignalPolarityCfg *polarityCfg);
840 
847 static inline void CSL_dssVpLcdAdvSignalCfgInit(
848  CSL_DssVpLcdAdvSignalCfg *advSignalCfg);
849 
856 static inline void CSL_dssVpLcdOpTimingCfgInit(
857  CSL_DssVpLcdOpTimingCfg *lcdCfg);
858 
865 static inline void CSL_dssVpLcdBlankTimingCfgInit(
866  CSL_DssVpLcdBlankTimingCfg *blankCfg);
867 
874 static inline void CSL_dssVpOldiCfgInit(CSL_DssVpOldiCfg *oldiCfg);
875 
876 /* ========================================================================== */
877 /* Static Function Definitions */
878 /* ========================================================================== */
879 
880 static inline void CSL_dssVpGammaCfgInit(
881  CSL_DssVpGammaCfg *gammaCfg)
882 {
883  uint32_t i;
884  if(NULL != gammaCfg)
885  {
886  gammaCfg->gammaEnable = FALSE;
887  for(i=0U; i<CSL_DSS_NUM_LUT_ENTRIES; i++)
888  {
889  gammaCfg->gammaData[i] = 0U;
890  }
891  }
892 }
893 
894 static inline void CSL_dssVpLcdTdmCfgInit(
895  CSL_DssVpLcdTdmCfg *tdmCfg)
896 {
897  if(NULL != tdmCfg)
898  {
899  tdmCfg->tdmEnable = FALSE;
903  tdmCfg->numBitsPixel1Cycle0 = 0x0U;
904  tdmCfg->numBitsPixel1Cycle1 = 0x0U;
905  tdmCfg->numBitsPixel1Cycle2 = 0x0U;
906  tdmCfg->bitAlignPixel1Cycle0 = 0x0U;
907  tdmCfg->bitAlignPixel1Cycle1 = 0x0U;
908  tdmCfg->bitAlignPixel1Cycle2 = 0x0U;
909  tdmCfg->numBitsPixel2Cycle0 = 0x0U;
910  tdmCfg->numBitsPixel2Cycle1 = 0x0U;
911  tdmCfg->numBitsPixel2Cycle2 = 0x0U;
912  tdmCfg->bitAlignPixel2Cycle0 = 0x0U;
913  tdmCfg->bitAlignPixel2Cycle1 = 0x0U;
914  tdmCfg->bitAlignPixel2Cycle2 = 0x0U;
915  }
916 }
917 
919  CSL_DssVpLcdSignalPolarityCfg *polarityCfg)
920 {
921  if(NULL != polarityCfg)
922  {
923  polarityCfg->actVidPolarity = FVID2_POL_HIGH;
925  polarityCfg->hsPolarity = FVID2_POL_HIGH;
926  polarityCfg->vsPolarity = FVID2_POL_HIGH;
927  }
928 }
929 
930 static inline void CSL_dssVpLcdAdvSignalCfgInit(
931  CSL_DssVpLcdAdvSignalCfg *advSignalCfg)
932 {
933  if(NULL != advSignalCfg)
934  {
935  advSignalCfg->hVAlign = CSL_DSS_VP_HVSYNC_NOT_ALIGNED;
937  advSignalCfg->hVClkRiseFall = FVID2_EDGE_POL_FALLING;
938  advSignalCfg->acBI = 0x0U;
939  advSignalCfg->acB = 0x0U;
940  advSignalCfg->vSyncGated = FALSE;
941  advSignalCfg->hSyncGated = FALSE;
942  advSignalCfg->pixelClockGated = FALSE;
943  advSignalCfg->pixelDataGated = FALSE;
944  advSignalCfg->pixelGated = FALSE;
945  }
946 }
947 
948 static inline void CSL_dssVpLcdOpTimingCfgInit(
949  CSL_DssVpLcdOpTimingCfg *lcdCfg)
950 {
951  if(NULL != lcdCfg)
952  {
953  Fvid2ModeInfo_init(&(lcdCfg->mInfo));
956  lcdCfg->videoIfWidth = FVID2_VIFW_12BIT;
959  }
960 }
961 
963  CSL_DssVpLcdBlankTimingCfg *blankCfg)
964 {
965  if(NULL != blankCfg)
966  {
967  blankCfg->hFrontPorch = 0x0U;
968  blankCfg->hBackPorch = 0x0U;
969  blankCfg->hSyncLen = 0x0U;
970  blankCfg->vFrontPorch = 0x0U;
971  blankCfg->vBackPorch = 0x0U;
972  blankCfg->vSyncLen = 0x0U;
973  }
974 }
975 
976 static inline void CSL_dssVpOldiCfgInit(CSL_DssVpOldiCfg *oldiCfg)
977 {
978  if(NULL != oldiCfg)
979  {
984  }
985 }
986 
987 #ifdef __cplusplus
988 }
989 #endif
990 
991 #endif /* #ifndef CSL_DSSVIDEOPORT_H_ */
992 
CSL_DssVpLcdOpTimingCfg::deltaLinesPerPanel
uint32_t deltaLinesPerPanel
Definition: csl_dssVideoPort.h:512
CSL_dssVpSetLcdOpTimingConfig
int32_t CSL_dssVpSetLcdOpTimingConfig(CSL_dss_vpRegs *vpRegs, const CSL_DssVpLcdOpTimingCfg *lcdCfg)
Configure the LCD Timing parameters.
CSL_DssVpLcdAdvSignalCfg::hSyncGated
uint32_t hSyncGated
Definition: csl_dssVideoPort.h:408
CSL_dssVpLcdSignalPolarityCfgInit
static void CSL_dssVpLcdSignalPolarityCfgInit(CSL_DssVpLcdSignalPolarityCfg *polarityCfg)
CSL_DssVpLcdSignalPolarityCfg structure init function.
Definition: csl_dssVideoPort.h:918
CSL_DssVpLcdTdmCfg::bitAlignPixel2Cycle1
uint32_t bitAlignPixel2Cycle1
Definition: csl_dssVideoPort.h:352
CSL_DssVpLcdOpTimingCfg::videoIfWidth
uint32_t videoIfWidth
Definition: csl_dssVideoPort.h:503
CSL_DssSafetyChkCfg
Configuration for doing safety checks.
Definition: csl_dssTop.h:260
CSL_DssVpLcdTdmCfg::tdmEnable
uint32_t tdmEnable
Definition: csl_dssVideoPort.h:309
CSL_DSS_VP_FID_FIRST_EVEN
#define CSL_DSS_VP_FID_FIRST_EVEN
First field is even.
Definition: csl_dssVideoPort.h:200
CSL_dssVpOldiEnable
void CSL_dssVpOldiEnable(CSL_dss_vpRegs *vpRegs, uint32_t enable)
Enable/disable the OLDI Module.
CSL_DssVpLcdSignalPolarityCfg::vsPolarity
uint32_t vsPolarity
Definition: csl_dssVideoPort.h:375
CSL_dssVpSetGoBit
void CSL_dssVpSetGoBit(CSL_dss_vpRegs *vpRegs)
GO Command for the VP output. It is used to synchronize the pipelines associated with the VP output.
CSL_DssVpLcdOpTimingCfg::fidFirst
uint32_t fidFirst
Definition: csl_dssVideoPort.h:515
CSL_DssVpLcdOpTimingCfg
Timing configuration for the LCD output.
Definition: csl_dssVideoPort.h:431
CSL_DssVpGammaCfg
Gamma Correction configuration for DSS Video Port Output.
Definition: csl_dssVideoPort.h:295
CSL_dssVpSetCSCCoeff
void CSL_dssVpSetCSCCoeff(CSL_dss_vpRegs *vpRegs, const CSL_DssCscCoeff *cscCoeff, uint32_t cscPos, uint32_t cscEnable)
Configure the coefficients for Color Space Conversion.
CSL_DssVpLcdTdmCfg::numBitsPixel2Cycle1
uint32_t numBitsPixel2Cycle1
Definition: csl_dssVideoPort.h:343
CSL_dssVpGetSafetySign
uint32_t CSL_dssVpGetSafetySign(const CSL_dss_vpRegs *vpRegs, uint32_t regionId)
Get the Safety Signature of the sub region.
CSL_DssVpLcdBlankTimingCfg::hFrontPorch
uint32_t hFrontPorch
Definition: csl_dssVideoPort.h:526
CSL_dssVpEnableTvGamma
void CSL_dssVpEnableTvGamma(CSL_dss_vpRegs *vpRegs, const CSL_DssVpGammaCfg *gammaCfg)
Enable/Bypass TV Gamma Table.
FVID2_DV_GENERIC_DISCSYNC
#define FVID2_DV_GENERIC_DISCSYNC
Video format is for any discrete sync.
Definition: fvid2_dataTypes.h:230
CSL_DssVpLcdTdmCfg::numBitsPixel1Cycle1
uint32_t numBitsPixel1Cycle1
Definition: csl_dssVideoPort.h:325
CSL_DssVpLcdAdvSignalCfg::pixelGated
uint32_t pixelGated
Definition: csl_dssVideoPort.h:420
CSL_DssCscCoeff
Structure containing coefficients for Color Space Conversion.
Definition: csl_dssTop.h:220
CSL_DSS_CSC_RANGE_FULL
#define CSL_DSS_CSC_RANGE_FULL
Full range selected.
Definition: csl_dssTop.h:168
CSL_dssVpOldiReset
void CSL_dssVpOldiReset(const CSL_dss_vpRegs *vpRegs)
Reset the OLDI Module.
CSL_DssVpLcdBlankTimingCfg
Blanking Timing parameters for the LCD.
Definition: csl_dssVideoPort.h:525
FVID2_EDGE_POL_FALLING
#define FVID2_EDGE_POL_FALLING
Falling Edge.
Definition: fvid2_dataTypes.h:819
CSL_DssVpOldiCfg
OLDI Configuration.
Definition: csl_dssVideoPort.h:569
NULL
#define NULL
Define NULL if not defined.
Definition: csl_types.h:100
CSL_DSS_VP_TDM_CYCLE_1PERPIXEL
#define CSL_DSS_VP_TDM_CYCLE_1PERPIXEL
1 cycle per pixel
Definition: csl_dssVideoPort.h:112
CSL_dssVpLcdBlankTimingCfgInit
static void CSL_dssVpLcdBlankTimingCfgInit(CSL_DssVpLcdBlankTimingCfg *blankCfg)
CSL_DssVpLcdBlankTimingCfg structure init function.
Definition: csl_dssVideoPort.h:962
CSL_dssVpSetSafetyReferenceSign
void CSL_dssVpSetSafetyReferenceSign(CSL_dss_vpRegs *vpRegs, uint32_t referenceSign, uint32_t regionId)
Set the reference safety signature for data correctness check.
CSL_dssVpOldiCfgInit
static void CSL_dssVpOldiCfgInit(CSL_DssVpOldiCfg *oldiCfg)
CSL_DssVpOldiCfg structure init function.
Definition: csl_dssVideoPort.h:976
CSL_DssVpLcdAdvSignalCfg::hVAlign
uint32_t hVAlign
Definition: csl_dssVideoPort.h:385
CSL_dss_vp1Regs
Definition: cslr_dss.h:4274
Fvid2ModeInfo_init
static void Fvid2ModeInfo_init(Fvid2_ModeInfo *modeInfo)
Fvid2_ModeInfo structure init function. This defaults to 1080p60.
Definition: fvid2_dataTypes.h:2273
CSL_DssVpLcdAdvSignalCfg::pixelClockGated
uint32_t pixelClockGated
Definition: csl_dssVideoPort.h:412
CSL_dssVpSetLcdBlankTiming
int32_t CSL_dssVpSetLcdBlankTiming(CSL_dss_vpRegs *vpRegs, const CSL_DssVpLcdBlankTimingCfg *blankCfg, uint32_t dvoFormat, uint32_t scanFormat, uint32_t isCustomTiming)
Configure the LCD Blank Timing parameters.
CSL_dssVpSetLcdTdmConfig
void CSL_dssVpSetLcdTdmConfig(CSL_dss_vpRegs *vpRegs, const CSL_DssVpLcdTdmCfg *lcdTdmCfg)
Configure the LCD TDM(Time division multiplexing) parameters.
CSL_DssVpOldiCfg::oldiMapType
uint32_t oldiMapType
Definition: csl_dssVideoPort.h:570
CSL_dssVpSetSafetySignSeedVal
void CSL_dssVpSetSafetySignSeedVal(CSL_dss_vpRegs *vpRegs, uint32_t signSeedVal)
Set the seed value for the signature calculation.
CSL_DSS_VP_HVSYNC_NOT_ALIGNED
#define CSL_DSS_VP_HVSYNC_NOT_ALIGNED
HSYNC and VSYNC are not aligned.
Definition: csl_dssVideoPort.h:152
CSL_DSS_VP_HVCLK_CONTROL_OFF
#define CSL_DSS_VP_HVCLK_CONTROL_OFF
HSYNC and VSYNC are driven on opposite edges of the pixel clock than pixel data.
Definition: csl_dssVideoPort.h:167
CSL_DssVpLcdBlankTimingCfg::vBackPorch
uint32_t vBackPorch
Definition: csl_dssVideoPort.h:549
CSL_DssVpLcdSignalPolarityCfg
Polarity of Active Video, Pixel Clock, HSync and VSync signals for the LCD.
Definition: csl_dssVideoPort.h:365
FVID2_VIFW_12BIT
#define FVID2_VIFW_12BIT
12-bit interface.
Definition: fvid2_dataTypes.h:941
CSL_dssVpSetLcdSignalPolarityConfig
void CSL_dssVpSetLcdSignalPolarityConfig(CSL_dss_vpRegs *vpRegs, const CSL_DssVpLcdSignalPolarityCfg *polarityCfg)
Configure the Polarity of LCD signals(HSYNC, VSYNC, PCLK, Data)
CSL_DssVpLcdSignalPolarityCfg::hsPolarity
uint32_t hsPolarity
Definition: csl_dssVideoPort.h:372
CSL_DssVpLcdTdmCfg::bitAlignPixel1Cycle0
uint32_t bitAlignPixel1Cycle0
Definition: csl_dssVideoPort.h:331
CSL_DssVpLcdTdmCfg::tdmCycleFormat
uint32_t tdmCycleFormat
Definition: csl_dssVideoPort.h:316
CSL_dssVpLcdTdmCfgInit
static void CSL_dssVpLcdTdmCfgInit(CSL_DssVpLcdTdmCfg *tdmCfg)
CSL_DssVpLcdTdmCfg structure init function.
Definition: csl_dssVideoPort.h:894
CSL_DSS_NUM_LUT_ENTRIES
#define CSL_DSS_NUM_LUT_ENTRIES
Number of entries for CLUT/Gamma Correction.
Definition: csl_dssTop.h:207
CSL_DssVpLcdAdvSignalCfg::acB
uint32_t acB
Definition: csl_dssVideoPort.h:398
CSL_DssVpLcdAdvSignalCfg::acBI
uint32_t acBI
Definition: csl_dssVideoPort.h:394
CSL_DssVpLcdAdvSignalCfg::hVClkControl
uint32_t hVClkControl
Definition: csl_dssVideoPort.h:388
CSL_DssVpOldiCfg::dualModeSync
uint32_t dualModeSync
Definition: csl_dssVideoPort.h:578
CSL_dssVpSetOldiConfig
void CSL_dssVpSetOldiConfig(CSL_dss_vpRegs *vpRegs, const CSL_DssVpOldiCfg *oldiCfg)
Set the OLDI configuration.
Fvid2_ModeInfo
FVID2 Mode information structure.
Definition: fvid2_dataTypes.h:1307
CSL_DssVpLcdOpTimingCfg::cscRange
uint32_t cscRange
Definition: csl_dssVideoPort.h:501
CSL_DSS_VP_OLDI_MAP_TYPE_C
#define CSL_DSS_VP_OLDI_MAP_TYPE_C
Map Type C is Single Link 24 bit VESA.
Definition: csl_dssVideoPort.h:241
CSL_DssVpLcdTdmCfg::numBitsPixel2Cycle0
uint32_t numBitsPixel2Cycle0
Definition: csl_dssVideoPort.h:340
CSL_DSS_VP_OLDI_BIT_DEPTH_24_BITS
#define CSL_DSS_VP_OLDI_BIT_DEPTH_24_BITS
Input RGB data's bit depth is 24.
Definition: csl_dssVideoPort.h:268
CSL_DssVpLcdOpTimingCfg::dvoFormat
uint32_t dvoFormat
Definition: csl_dssVideoPort.h:499
CSL_dssVpSetLcdAdvSignalConfig
void CSL_dssVpSetLcdAdvSignalConfig(CSL_dss_vpRegs *vpRegs, const CSL_DssVpLcdAdvSignalCfg *advSignalCfg)
Configure the advance LCD Signal parameters.
CSL_dssVpSetLcdLineNum
void CSL_dssVpSetLcdLineNum(CSL_dss_vpRegs *vpRegs, uint32_t lineNum)
Set the Line Number at which the interrupt should be generated.
CSL_DssVpLcdTdmCfg::bitAlignPixel2Cycle0
uint32_t bitAlignPixel2Cycle0
Definition: csl_dssVideoPort.h:349
CSL_DssVpLcdTdmCfg::numBitsPixel1Cycle0
uint32_t numBitsPixel1Cycle0
Definition: csl_dssVideoPort.h:322
CSL_DssVpLcdTdmCfg::bitAlignPixel2Cycle2
uint32_t bitAlignPixel2Cycle2
Definition: csl_dssVideoPort.h:355
CSL_DssVpLcdBlankTimingCfg::vFrontPorch
uint32_t vFrontPorch
Definition: csl_dssVideoPort.h:543
CSL_DssVpGammaCfg::gammaEnable
uint32_t gammaEnable
Definition: csl_dssVideoPort.h:296
CSL_DssVpLcdBlankTimingCfg::hSyncLen
uint32_t hSyncLen
Definition: csl_dssVideoPort.h:538
CSL_DSS_VP_LPP_DELTA_ZERO
#define CSL_DSS_VP_LPP_DELTA_ZERO
Odd field has same size as even.
Definition: csl_dssVideoPort.h:182
CSL_DssVpOldiCfg::dataEnablePolarity
uint32_t dataEnablePolarity
Definition: csl_dssVideoPort.h:572
CSL_DssVpLcdTdmCfg::numBitsPixel1Cycle2
uint32_t numBitsPixel1Cycle2
Definition: csl_dssVideoPort.h:328
CSL_DSS_VP_TDM_PARALLEL_OUTPUT_8BIT
#define CSL_DSS_VP_TDM_PARALLEL_OUTPUT_8BIT
8-bit parallel output interface selected
Definition: csl_dssVideoPort.h:132
CSL_DSS_VP_OLDI_DUALMODESYNC_DISABLE
#define CSL_DSS_VP_OLDI_DUALMODESYNC_DISABLE
Disable dual mode operation.
Definition: csl_dssVideoPort.h:283
CSL_dssVpSetSafetyChkConfig
void CSL_dssVpSetSafetyChkConfig(CSL_dss_vpRegs *vpRegs, const CSL_DssSafetyChkCfg *safetyCfg, uint32_t regionId)
Configure the Safety Check parameters.
FVID2_POL_HIGH
#define FVID2_POL_HIGH
High Polarity.
Definition: fvid2_dataTypes.h:804
CSL_dssVpLcdAdvSignalCfgInit
static void CSL_dssVpLcdAdvSignalCfgInit(CSL_DssVpLcdAdvSignalCfg *advSignalCfg)
CSL_DssVpLcdAdvSignalCfg structure init function.
Definition: csl_dssVideoPort.h:930
FVID2_EDGE_POL_RISING
#define FVID2_EDGE_POL_RISING
Rising Edge.
Definition: fvid2_dataTypes.h:817
CSL_DssVpLcdTdmCfg::tdmParallelMode
uint32_t tdmParallelMode
Definition: csl_dssVideoPort.h:319
CSL_DssVpGammaCfg::gammaData
uint32_t gammaData[CSL_DSS_NUM_LUT_ENTRIES]
Definition: csl_dssVideoPort.h:300
CSL_DssVpLcdBlankTimingCfg::vSyncLen
uint32_t vSyncLen
Definition: csl_dssVideoPort.h:556
CSL_dssVpGammaCfgInit
static void CSL_dssVpGammaCfgInit(CSL_DssVpGammaCfg *gammaCfg)
CSL_DssVpGammaCfg structure init function.
Definition: csl_dssVideoPort.h:880
CSL_dssVpEnable
void CSL_dssVpEnable(CSL_dss_vpRegs *vpRegs, uint32_t enable)
Enable the DSS Video Port.
CSL_DssVpLcdOpTimingCfg::mInfo
Fvid2_ModeInfo mInfo
Definition: csl_dssVideoPort.h:432
CSL_DssVpOldiCfg::dssBitDepth
uint32_t dssBitDepth
Definition: csl_dssVideoPort.h:575
CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_LOW
#define CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_LOW
Low level.
Definition: csl_dssVideoPort.h:95
CSL_dssVpLcdOpTimingCfgInit
static void CSL_dssVpLcdOpTimingCfgInit(CSL_DssVpLcdOpTimingCfg *lcdCfg)
CSL_DssVpLcdOpTimingCfg structure init function.
Definition: csl_dssVideoPort.h:948
CSL_DssVpLcdSignalPolarityCfg::pixelClkPolarity
uint32_t pixelClkPolarity
Definition: csl_dssVideoPort.h:369
CSL_DssVpLcdAdvSignalCfg::vSyncGated
uint32_t vSyncGated
Definition: csl_dssVideoPort.h:404
CSL_DssVpLcdTdmCfg::bitAlignPixel1Cycle2
uint32_t bitAlignPixel1Cycle2
Definition: csl_dssVideoPort.h:337
CSL_DssVpLcdBlankTimingCfg::hBackPorch
uint32_t hBackPorch
Definition: csl_dssVideoPort.h:532
CSL_DssVpLcdAdvSignalCfg
Advance Signal Configuration for the LCD.
Definition: csl_dssVideoPort.h:384
CSL_DssVpLcdTdmCfg::tdmUnusedBitsLevel
uint32_t tdmUnusedBitsLevel
Definition: csl_dssVideoPort.h:313
CSL_DssVpLcdSignalPolarityCfg::actVidPolarity
uint32_t actVidPolarity
Definition: csl_dssVideoPort.h:366
CSL_DssVpLcdTdmCfg::bitAlignPixel1Cycle1
uint32_t bitAlignPixel1Cycle1
Definition: csl_dssVideoPort.h:334
CSL_DssVpLcdTdmCfg
LCD Configuration for Time Division Multiplexing.
Definition: csl_dssVideoPort.h:308
CSL_DssVpLcdTdmCfg::numBitsPixel2Cycle2
uint32_t numBitsPixel2Cycle2
Definition: csl_dssVideoPort.h:346
FALSE
#define FALSE
Definition: csl_types.h:62
CSL_DssVpLcdAdvSignalCfg::pixelDataGated
uint32_t pixelDataGated
Definition: csl_dssVideoPort.h:416
CSL_dss_vpRegs
CSL_dss_vp1Regs CSL_dss_vpRegs
DSS Video Port Registers.
Definition: csl_dssVideoPort.h:70
CSL_DssVpLcdAdvSignalCfg::hVClkRiseFall
uint32_t hVClkRiseFall
Definition: csl_dssVideoPort.h:391