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AM62Px MCU+ SDK
09.01.00
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AM62Px MCU+ SDK
09.01.00
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Timing configuration for the LCD output.
Data Fields | |
| Fvid2_ModeInfo | mInfo |
| uint32_t | dvoFormat |
| uint32_t | cscRange |
| uint32_t | videoIfWidth |
| uint32_t | deltaLinesPerPanel |
| uint32_t | fidFirst |
| Fvid2_ModeInfo CSL_DssVpLcdOpTimingCfg::mInfo |
FVID2 mode information Fvid2_ModeInfo
standard:
Standard for which to get the info. For valid values see Fvid2_Standard. In case of BT output this should always be FVID2_STD_CUSTOM
width:
Active video frame width in pixels
height:
Active video frame height in lines
scanFormat:
Scan format of standard. For valid values see Fvid2_ScanFormat
hFrontPorch:
Horizontal Front Porch. Specifies the number of pixel clock periods to add to the end of a line transmission before line clock is asserted. In BT mode and interlaced, this field corresponds to the vertical field blanking No 1 for Even Field. In case of BT progressive mode this field is unused
hBackPorch:
Horizontal Back Porch. Specifies the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display. In BT mode and interlaced, this field corresponds to the vertical field blanking No 2 for Even Field. In case of BT progressive mode this field is unused
hSyncLen:
Horizontal synchronization pulse width. Encoded Value(from 1 to 256)to specify the number of pixel clock periods to pulse the line clock at the end of each line. In BT mode, this field corresponds to 12-bit horizontal blanking
vFrontPorch:
Vertical front porch. Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the end of each frame. When in BT mode and interlaced, this field corresponds to the vertical field blanking No 1 for Odd Field. In case of BT progressive mode this field corresponds to the Vertical frame blanking No 2
vBackPorch:
Vertical back porch. Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the beginning of a frame. In BT mode and interlaced, this field corresponds to the vertical field blanking No 2 for Odd Field. In case of BT progressive mode this field corresponds to the Vertical frame blanking No 2 before the first set of pixels is output to the display
vSyncLen:
Vertical synchronization pulse width. In active mode, RW 0x00 encoded value (from 1 to 256) to specify the number of line clock periods (program to value minus 1) to pulse the frame clock (VSYNC) pin at the end of each frame after the end of frame wait (VFP) period elapses. In BT mode, this field is not used
pixelClock, fps: Not used, set to 0 or default
| uint32_t CSL_DssVpLcdOpTimingCfg::dvoFormat |
Digital output format. For valid values see Fvid2_DVFormat
| uint32_t CSL_DssVpLcdOpTimingCfg::cscRange |
CSC Range. For valid values see CSL_DssCscRange
| uint32_t CSL_DssVpLcdOpTimingCfg::videoIfWidth |
Video interface Width, Valid options are
FVID2_VIFW_12BIT,
FVID2_VIFW_16BIT,
FVID2_VIFW_18BIT,
FVID2_VIFW_24BIT,
FVID2_VIFW_30BIT,
FVID2_VIFW_36BIT
For more details see Fvid2_VideoIfWidth
| uint32_t CSL_DssVpLcdOpTimingCfg::deltaLinesPerPanel |
Delta size of the odd field compared to the even field. For valid values see CSL_DssVpDeltaLpp
| uint32_t CSL_DssVpLcdOpTimingCfg::fidFirst |
Selects the first field to output in case of interlace mode. In case of progressive mode, the value is not used. For valid values see CSL_DssVpFidFirstVal
1.8.20