Detailed Description

Common (across contexts) interrupts.

This represents both status and configuration (enable/disable) structures. The description of the fields is in terms of status. For configuration they should be interpreted as "true if you want to enable the detection of this condition, false otherwise".

For interrupt status, the interrupts can be cleared by issuing CSIRX_commonClearAllIntr API

Data Fields
bool	isOcpError
	reserved, keep this as 0 More...

bool	isGenericShortPacketReceive
	true if short packet was received other than the MIPI sync events: Frame Start Code (0x0) Frame End Code (0x1) Line Start Code (0x2) Line End Code (0x3) Sync codes 0x4 to 0x7 are reserved by MIPI. Therefore, data type between 0x8 and x0F only will be applicable to this. More...

bool	isOneBitShortPacketErrorCorrect
	if true, ECC has been used to do the correction of 1-bit error (short packet only). Influenced by CSIRX_CommonConfig::isHeaderErrorCheckEnabled. More...

bool	isMoreThanOneBitShortPacketErrorCannotCorrect
	if true, more than 1-bit error that cannot be ECC corrected and was detected in the short packet or long packet header. Influenced by CSIRX_CommonConfig::isHeaderErrorCheckEnabled. More...

bool	isComplexioError
	if true, one or more of complex IO errors defined in CSIRX_ComplexioLanesIntr happened. They can be queried using CSIRX_complexioGetPendingIntr API. More...

bool	isFifoOverflow
	if true, it indicates data input rate is higher than the data output rate resulting in the receive FIFO overflowing. In case of an overflow, the module properly finishes the burst that has been started and doesn't issue any new OCP transactions on the master port. A reset of the module is required to restart correctly More...

bool	isContextIntr [CSIRX_CONTEXTS_MAX]
	if any of the context entries is true, one or more of context interrupts defined in CSIRX_ContextIntr happened for the respective context. The IRQs for a specific context can be queried using CSIRX_contextGetPendingIntr API and they can be cleared using CSIRX_contextClearAllIntr API More...

Field Documentation

◆ isOcpError

bool CSIRX_CommonIntr::isOcpError

reserved, keep this as 0

◆ isGenericShortPacketReceive

bool CSIRX_CommonIntr::isGenericShortPacketReceive

true if short packet was received other than the MIPI sync events:
Frame Start Code (0x0)
Frame End Code (0x1)
Line Start Code (0x2)
Line End Code (0x3)
Sync codes 0x4 to 0x7 are reserved by MIPI. Therefore, data type between 0x8 and x0F only will be applicable to this.

◆ isOneBitShortPacketErrorCorrect

bool CSIRX_CommonIntr::isOneBitShortPacketErrorCorrect

if true, ECC has been used to do the correction of 1-bit error (short packet only). Influenced by CSIRX_CommonConfig::isHeaderErrorCheckEnabled.

◆ isMoreThanOneBitShortPacketErrorCannotCorrect

bool CSIRX_CommonIntr::isMoreThanOneBitShortPacketErrorCannotCorrect

if true, more than 1-bit error that cannot be ECC corrected and was detected in the short packet or long packet header. Influenced by CSIRX_CommonConfig::isHeaderErrorCheckEnabled.

◆ isComplexioError

bool CSIRX_CommonIntr::isComplexioError

if true, one or more of complex IO errors defined in CSIRX_ComplexioLanesIntr happened. They can be queried using CSIRX_complexioGetPendingIntr API.

◆ isFifoOverflow

bool CSIRX_CommonIntr::isFifoOverflow

if true, it indicates data input rate is higher than the data output rate resulting in the receive FIFO overflowing. In case of an overflow, the module properly finishes the burst that has been started and doesn't issue any new OCP transactions on the master port. A reset of the module is required to restart correctly

◆ isContextIntr

bool CSIRX_CommonIntr::isContextIntr[CSIRX_CONTEXTS_MAX]

if any of the context entries is true, one or more of context interrupts defined in CSIRX_ContextIntr happened for the respective context. The IRQs for a specific context can be queried using CSIRX_contextGetPendingIntr API and they can be cleared using CSIRX_contextClearAllIntr API