| Feature | Module |
| Memory Configurator (SysConfig based Linker generation) (Memory Configurator) | Common |
| Coremark and Dhrystone benchmark (Coremark Benchmark, Dhrystone Benchmark) | Common |
| GPMC PSRAM support (without DMA) (GPMC) | GPMC |
| McSPI LLD driver support (MCSPI Low Level Driver) | McSPI |
| UART LLD driver support (UART Low Level Driver) | UART |
| HW Spinlock example (Spinlock Example) | Spinlock |
| SafeIPC support (IPC SafeIPC Echo) | IPC |
| ECAP-ADC & ECAP-EDMA example (ADC SOC ECAP) (ECAP EDMA Example) | ECAP |
| EPWM Synchronization example (EPWM Synchronization) | EPWM |
| Uniflash tool support (TI Uniflash Tool) | Uniflash |
| LwIP stack is upgraded to 2.2.0 version | Ethernet and Networking |
| YANG data model based configuration support for IET/Frame Preemption(IEEE 802.1Qbu), Credit Based Shaper(IEEE 802.1Qav), Enhancements for Scheduled Traffic(IEEE 802.1Qbv) and other TSN features | Ethernet and Networking |
| Ethernet Switch management through standard Link Layer Discovery Protocol(IEEE 802.1AB) for CPSW peripheral | Ethernet and Networking |
| Multi-time domain gPTP(IEEE 802.1AS) support enabled in TSN stack | Ethernet and Networking |
| Example to showcase the simultaneous execution of Time-Sensitive Networking and LwIP stack | Ethernet and Networking |
| Syscfg and documentation update for static IP configuration, custom MAC address and other ethernet related configurations | Ethernet and Networking |
| Module | Supported CPUs | SysConfig Support | OS support | Key features tested | Key features not tested / NOT supported |
| Cache | R5F | YES | FreeRTOS, NORTOS | Cache write back, invalidate, enable/disable | - |
| Clock | R5F | YES | FreeRTOS, NORTOS | Tick timer at user specified resolution, timeouts and delays | - |
| CpuId | R5F | NA | FreeRTOS, NORTOS | Verify Core ID and Cluster ID that application is currently running on | - |
| CycleCounter | R5F | NA | FreeRTOS, NORTOS | Measure CPU cycles using CPU specific internal counters | - |
| Debug | R5F | YES | FreeRTOS, NORTOS | Logging and assert to any combo of: UART, CCS, shared memory | - |
| Heap | R5F | NA | FreeRTOS, NORTOS | Create arbitrary heaps in user defined memory segments | - |
| Hwi | R5F | YES | FreeRTOS, NORTOS | Interrupt register, enable/disable/restore, Interrupt prioritization | - |
| MPU | R5F | YES | FreeRTOS, NORTOS | Setup MPU and control access to address space | - |
| Semaphore | R5F | NA | FreeRTOS, NORTOS | Binary, Counting Semaphore, recursive mutexs with timeout | - |
| Task | R5F | NA | FreeRTOS | Create, delete tasks | - |
| Timer | R5F | YES | FreeRTOS, NORTOS | Configure arbitrary timers | - |
| Peripheral | Supported CPUs | SysConfig Support | DMA Supported | Key features tested | Key features not tested / NOT supported |
| ADC | R5F | YES | Yes. Example: adc_soc_continuous_dma | Single software triggered conversion, Multiple ADC trigger using PWM, Result read using DMA, EPWM trip through PPB limit, PPB limits, PPB offsets, burst mode oversampling, differential mode, Offset, EPWM triggered conversion | - |
| Bootloader | R5F | YES | Yes. DMA enabled for SBL QSPI | Boot modes: QSPI, UART. All R5F's | - |
| CMPSS | R5F | YES | NA | Asynchronous PWM trip | - |
| CPSW | R5F | YES | No | MAC loopback, PHY loopback, LWIP: Getting IP, Ping, Iperf, Layer 2 MAC, Layer 2 PTP Timestamping and Ethernet CPSW Switch support, TSN stack | RMII, MII mode |
| DAC | R5F | YES | Yes. Example: dac_sine_dma | Constant voltage, Square wave generation, Sine wave generation with and without DMA, Ramp wave generation, Random Voltage generation | - |
| ECAP | R5F | YES | No | ECAP APWM mode, PWM capture | - |
| EDMA | R5F | YES | NA | DMA transfer using interrupt and polling mode, QDMA Transfer, Channel Chaining, PaRAM Linking | - |
| EPWM | R5F | YES | Yes. Example: epwm_dma | PWM outputs A and B in up-down count mode, Trip zone, Update PWM using EDMA, Valley switching, High resolution time period adjustment, type5 feature | - |
| EQEP | R5F | YES | NA | Speed and Position measurement. Frequency Measurement | - |
| FSI | R5F | YES | Yes. Example: fsi_loopback_dma | RX, TX, polling, interrupt mode, Dma, single lane loopback. | - FSI Spi Mode |
| GPIO | R5F | YES | NA | Output, Input and Interrupt functionality | - |
| I2C | R5F | YES | No | Controller mode, basic read/write | - |
| IPC Notify | R5F | YES | NA | Mailbox functionality, IPC between RTOS/NORTOS CPUs | M4F core |
| IPC Rpmsg | R5F | YES | NA | RPMessage protocol based IPC | M4F core |
| MCAN | R5F | YES | No | RX, TX, interrupt and polling mode, Corrupt Message Transmission Prevention, Error Passive state, Bus Off State, Bus Monitoring Mode | - |
| MCSPI | R5F | YES | Yes. Example: mcspi_loopback_dma | Controller/Peripheral mode, basic read/write, polling, interrupt and DMA mode | - |
| MDIO | R5F | YES | NA | Register read/write, link status and link interrupt enable API | - |
| MPU Firewall | R5F | YES | NA | Only compiled (Works only on HS-SE device) | - |
| MMCSD | R5F | YES | NA | MMCSD 4bit, Raw read/write | - file IO, eMMC |
PINMUX | R5F | YES | NA | Tested with multiple peripheral pinmuxes PMU | R5F | NO | NA | Tested various PMU events | Counter overflow detection is not enabled | - PRUICSS | R5F | YES | NA | Tested with Ethercat FW HAL | - QSPI | R5F | YES | Yes. Example: qspi_flash_dma_transfer | Read direct, Write indirect, Read/Write commands, DMA for read | - RTI | R5F | YES | No | Counter read, timebase selction, comparator setup for Interrupt, DMA requests | Capture feature, fast enabling/disabling of events not tested SDFM | R5F | YES | No | Filter data read from CPU, Filter data read with PWM sync | - SOC | R5F | YES | NA | Lock/unlock MMRs, clock enable, set Hz, Xbar configuration, SW Warm Reset, Address Translation | - SPINLOCK | R5F | NA | NA | Lock, unlock HW spinlocks | - UART | R5F | YES | Yes. Example: uart_echo_dma | Basic read/write at baud rate 115200, polling, interrupt mode | HW flow control not tested, DMA mode not supported WATCHDOG | R5F | YES | NA | Reset mode, Interrupt mode | -
| Module | Supported CPUs | SysConfig Support | OS Support | Key features tested | Key features not tested |
| Time-Sensitive Networking(gPTP-IEEE 802.1AS) | R5F | NO | FreeRTOS | gPTP IEEE 802.1 AS-2020 compliant gPTP stack, End Nodes and Bridge mode support, YANG data model configuration | Multi-Clock Domain |
| LwIP | R5F | YES | FreeRTOS | TCP/UDP IP networking stack with and without checksum offload enabled, TCP/UDP IP networking stack with server and client functionality, basic Socket APIs, netconn APIs and raw APIs, DHCP, ping, TCP iperf, scatter-gather, DSCP priority mapping | Other LwIP features |
| Ethernet driver (ENET) | R5F | YES | FreeRTOS | Ethernet as port using CPSW, MAC loopback and PHY loopback, Layer 2 MAC, Packet Timestamping, CPSW Switch, CPSW EST, interrupt pacing, Policer and Classifier, MDIO Manual Mode, Credit Based Shaper (IEEE 802.1Qav), Strapped PHY (Early Ethernet) | RMII, MII mode |
| ICSS-EMAC | R5F | YES | FreeRTOS | Only compiled | Not tested |
| Mbed-TLS | R5F | NO | FreeRTOS | Tested software cryptography after porting, used mbedTLS with LwIP to implement HTTPS server | Hardware offloaded cryptography |
| Module | Supported CPUs | SysConfig Support | OS support | Key features tested | Key features not tested / NOT supported |
| MCRC | R5F | NA | NORTOS | Full CPU, Auto CPU Mode and Semi CPU Auto Mode | - |
| DCC | R5F | NA | NORTOS | Single Shot and Continuous modes | - |
| PBIST | R5F | NA | NORTOS | Memories supported by MSS PBIST controller. | - |
| ESM | R5F | NA | NORTOS | Tested in combination with RTI, DCC | - |
| RTI | R5F | NA | NORTOS | WINDOWSIZE_100_PERCENT, WINDOWSIZE_50_PERCENT ,Latency/Propagation timing error(early)(50% window),Latency/Propagation timing error(late)(50% window) | - |
| ECC | R5F | NA | NORTOS | ECC of MSS_L2, R5F TCM, MCAN, VIM, ICSSM, TPTC | R5F Cache |
| ECC Bus Safety | R5F | NA | NORTOS | AHB, AXI, TPTC | - |
| CCM | R5F | NA | NORTOS | CCM Self Test Mode,Error Forcing Mode and Self Test Error Forcing Mode. | - |
| R5F STC(LBIST), Static Register Read | R5F | NA | NORTOS | STC of R5F, R5F CPU Static Register Read | - |
| ID | Head Line | Module | Applicable Releases | Resolution/Comments |
| MCUSDK-9309 | IPC: Issue when Combination of Notify and RPMsg is enabled in SysCfg. | IPC | 8.01.00 onwards | Use Only Notify or Only Notify+RPMsg on all cores. |
| MCUSDK-12153 | Syscfg Code Duplication in EPWM XCMP configs | EPWM | 09.00.00 | - |
| MCUSDK-11836 | LIN_sendWakeupSignal is not functional as expected | LIN | 09.00.00 | - |
| MCUSDK-11828 | lin_external example does not work if default configuration is disabled | LIN | 09.00.00 | Fix enableParity variable in syscfg template, disable Loopbacks/interrupt if loopback/interrupt is not enabled |
| MCUSDK-11725 | Data Abort on ECAP_getModuloCounterStatus() API | ECAP | 08.06.00 onwards | Unaligned access. Usage of 32 bit read macro to read a 16 bit address location |
| MCUSDK-11385 | RP message send hang issue in case of timeout | IPC | 08.06.00 onwards | RPMsg send invoked IPC Notify send without timeout management |
| ID | Head Line | Module | Reported in release | Workaround |
| MCUSDK-7319 | CONTROLSS-SDFM: Two Back-to-Back Writes to SDCPARMx Register Bit Fields CEVT1SEL, CEVT2SEL, and HZEN Within Three SD-Modulator Clock Cycles can Corrupt SDFM State Machine, Resulting in Spurious Comparator Events | SDFM | 08.04.00 onwards | Avoid back-to-back writes within three SD-modulator clock cycles or have the SDCPARMx register bit fields configured in one register write. |
| MCUSDK-8073 | UART1 not working as expected while configuring two uarts i.e UART0 and UART1 for two different cores | UART | 08.04.00 onwards | UART1 configuration from other core should be done after UART0 is configured and initialized |
| MCUSDK-9082 | MbedTLS - RSA exploit by kernel-privileged cache side-channel attackers | Mbed-TLS | 08.06.00 onwards | - |
| MCUSDK-9459 | UART LLD EDMA Mode not generating interrupt with TX and RX trigger levels greater than 1 | UART | 09.01.00 onwards | - |
| MCUSDK-10005 | UART LLD Write incompatible with data length 5 and 6 | UART | 09.01.00 onwards | Use other data length |
| MCUSDK-11247 | Delay missing after setting FIFO CLEAR bit | UART | 08.06.00 onwards | - |
| MCUSDK-11462 | EPWM: Illegal Combo Logic example fails | EPWM | 09.00.00 onwards | - |
| MCUSDK-11526 | UART LLD does not output readable characters with 16x AUTO BAUD operation mode | UART | 09.01.00 onwards | - |
| MCUSDK-10626 | FSI DMA loopback example TX and RX mismatching on 2nd run | FSI | 08.06.00 onwards | Reset board between 2 runs |
| MCUSDK-11730 | A wrong counter is used for Event 2 in PMU configuration | PMU | 09.00.00 onwards | - |
| PROC_SDL-5616 | ECC Bus Safety SEC and DED Error Injection fails for CPSW. | SDL | 8.6.0 onwards | None. |
| PROC_SDL-5617 | ECC Bus Safety SEC and DED Error Injection fails for MSS_L2. | SDL | 8.6.0 onwards | None. |
| PROC_SDL-4749 | ECC Bus Safety DED Error Injection fails for AXI. | SDL | 8.5.0 onwards | None. |
| PROC_SDL-5979 | R5F Cache ECC diagnostics are not supported. | SDL | 8.5.0 onwards | None. |
| ID | Head Line | Module | SDK Status |
| i2311 | USART: Spurious DMA Interrupts | UART | Implemented |
| i2313 | GPMC: Sub-32-bit read issue with NAND and FPGA/FIFO | GPMC | Not supported in SDK |
| i2324 | No synchronizer present between GCM and GCD status signals | Common | Open |
| i2345 | CPSW: Ethernet Packet corruption occurs if CPDMA fetches a packet which spans across memory banks | CPSW | Implemented |
| i2350 | McSPI data transfer using EDMA in 'ABSYNC' mode stops after 32 bits transfer | McSPI | Implemented |
| i2354 | SDFM: Two Back-to-Back Writes to SDCPARMx Register Bit Fields CEVT1SEL, CEVT2SEL, and HZEN Within Three SD-Modulator Clock Cycles can Corrupt SDFM State Machine, Resulting in Spurious Comparator Events | SDFM | Open |
| i2355 | ADC: DMA Read of Stale Result | ADC | Implemented |
| i2356 | ADC: Interrupts may Stop if INTxCONT (Continue-to-Interrupt Mode) is not Set | ADC | Implemented |
| i2375 | SDFM module event flags (SDIFLG.FLTx_FLG_CEVTx) do not get set again if the comparator event is still active and digital filter path (using SDCOMPxCTL.CEVTxDIGFILTSEL) is being selected | SDFM | Open |
| i2392 | Race condition in capture registers resulting in events miss | Common | Open |
| i2394 | Race condition in interrupt and error aggregator capture registers resulting in events miss | Common | Open |
| i2401 | CPSW: Host Timestamps Cause CPSW Port to Lock up | CPSW | Open |
| i2402 | CPSW: Ethernet to Host Checksum Offload does not work | CPSW | Open |
| i2404 | Race condition in mailbox registers resulting in events miss | IPC | Implemented |
| i2405 | CONTROLSS: Race condition OUTPUT_XBAR and PWM_XBAR resulting in event miss | XBAR | Open |
1.8.20