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SDL API Guide for J721E
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SDL API Guide for J721E
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Go to the source code of this file.
DCC Operation Mode | |
| #define | SDL_DCC_MODE_SINGLE_SHOT_1 (DCC_DCCGCTRL_SINGLESHOT_MODE1) |
| #define | SDL_DCC_MODE_SINGLE_SHOT_2 (DCC_DCCGCTRL_SINGLESHOT_MODE2) |
| #define | SDL_DCC_MODE_CONTINUOUS (DCC_DCCGCTRL_SINGLESHOT_DISABLE) |
| typedef uint32_t | SDL_DCC_mode |
| Enum to select the DCC Operation Mode. More... | |
DCC Clock source of COUNT0 | |
| #define | SDL_DCC_CLK0_SRC_CLOCK0_0 (DCC_DCCCLKSRC0_CLKSRC0_0) |
| #define | SDL_DCC_CLK0_SRC_CLOCK0_1 (DCC_DCCCLKSRC0_CLKSRC0_1) |
| #define | SDL_DCC_CLK0_SRC_CLOCK0_2 (DCC_DCCCLKSRC0_CLKSRC0_2) |
| typedef uint32_t | SDL_DCC_clkSrc0 |
| Enum to select the COUNT0 clock source. More... | |
DCC Clock source of COUNT1 | |
| #define | SDL_DCC_CLK1_SRC_CLOCK1 (DCC_DCCCLKSRC1_CLKSRC_0) |
| #define | SDL_DCC_CLK1_SRC_CLOCKSRC0 (DCC_DCCCLKSRC1_CLKSRC_1) |
| #define | SDL_DCC_CLK1_SRC_CLOCKSRC1 (DCC_DCCCLKSRC1_CLKSRC_2) |
| #define | SDL_DCC_CLK1_SRC_CLOCKSRC2 (DCC_DCCCLKSRC1_CLKSRC_3) |
| #define | SDL_DCC_CLK1_SRC_CLOCKSRC3 (DCC_DCCCLKSRC1_CLKSRC_4) |
| #define | SDL_DCC_CLK1_SRC_CLOCKSRC4 (DCC_DCCCLKSRC1_CLKSRC_5) |
| #define | SDL_DCC_CLK1_SRC_CLOCKSRC5 (DCC_DCCCLKSRC1_CLKSRC_6) |
| #define | SDL_DCC_CLK1_SRC_CLOCKSRC6 (DCC_DCCCLKSRC1_CLKSRC_7) |
| #define | SDL_DCC_CLK1_SRC_CLOCKSRC7 (DCC_DCCCLKSRC1_CLKSRC_8) |
| #define | SDL_DCC_CLK1_SRC_FICLK (DCC_DCCCLKSRC1_CLKSRC_OTHER) |
| typedef uint32_t | SDL_DCC_clkSrc1 |
| Enum to select the COUNT1 clock source. More... | |
DCC Interrupt type | |
| #define | SDL_DCC_INTERRUPT_ERR (0x0U) |
| #define | SDL_DCC_INTERRUPT_DONE (0x1U) |
| typedef uint32_t | SDL_DCC_intrType |
| Enum for DCC interrupts. More... | |
Data Structures | |
| struct | SDL_DCC_config |
| Structure containing parameters for DCC module configuration. More... | |
| struct | SDL_DCC_status |
| struct | SDL_DCC_staticRegs |
Functions | |
| int32_t | SDL_DCC_configure (SDL_DCC_Inst instance, const SDL_DCC_config *pConfig) |
| This API is used to configure DCC module. More... | |
| int32_t | SDL_DCC_verifyConfig (SDL_DCC_Inst instance, const SDL_DCC_config *pConfig) |
| This API is used to verify the configuration for DCC module. More... | |
| int32_t | SDL_DCC_enable (SDL_DCC_Inst instance) |
| This API is used to enable the DCC module. More... | |
| int32_t | SDL_DCC_disable (SDL_DCC_Inst instance) |
| This API is used to disable the DCC module. More... | |
| int32_t | SDL_DCC_getStatus (SDL_DCC_Inst instance, SDL_DCC_status *pStatus) |
| This API is used to get the stauts of DCC module. More... | |
| int32_t | SDL_DCC_enableIntr (SDL_DCC_Inst instance, SDL_DCC_intrType intr) |
| This API is used to Enable the interrupts. More... | |
| int32_t | SDL_DCC_clearIntr (SDL_DCC_Inst instance, SDL_DCC_intrType intr) |
| This API is used to clear the interrupts. More... | |
| int32_t | SDL_DCC_getStaticRegs (SDL_DCC_Inst instance, SDL_DCC_staticRegs *pStaticRegs) |
| This API is used to get the value of static registers for DCC module. More... | |
| #define DCC_DCCGCTRL (0x0U) |
| #define DCC_DCCREV (0x4U) |
| #define DCC_DCCCNTSEED0 (0x8U) |
| #define DCC_DCCVALIDSEED0 (0xcU) |
| #define DCC_DCCCNTSEED1 (0x10U) |
| #define DCC_DCCSTAT (0x14U) |
| #define DCC_DCCCNT0 (0x18U) |
| #define DCC_DCCVALID0 (0x1cU) |
| #define DCC_DCCCNT1 (0x20U) |
| #define DCC_DCCCLKSRC1 (0x24U) |
| #define DCC_DCCCLKSRC0 (0x28U) |
| #define DCC_DCCGCTRL_DCCENA_SHIFT (0U) |
| #define DCC_DCCGCTRL_DCCENA_MASK (0x0000000fU) |
| #define DCC_DCCGCTRL_DCCENA_ENABLE (0xFU) |
| #define DCC_DCCGCTRL_DCCENA_DISABLE (0x5U) |
| #define DCC_DCCGCTRL_ERRENA_SHIFT (4U) |
| #define DCC_DCCGCTRL_ERRENA_MASK (0x000000f0U) |
| #define DCC_DCCGCTRL_ERRENA_ENABLE (0xFU) |
| #define DCC_DCCGCTRL_ERRENA_DISABLE (0x5U) |
| #define DCC_DCCGCTRL_SINGLESHOT_SHIFT (8U) |
| #define DCC_DCCGCTRL_SINGLESHOT_MASK (0x00000f00U) |
| #define DCC_DCCGCTRL_SINGLESHOT_MODE1 (0xAU) |
| #define DCC_DCCGCTRL_SINGLESHOT_MODE2 (0xBU) |
| #define DCC_DCCGCTRL_SINGLESHOT_DISABLE (0x0U) |
| #define DCC_DCCGCTRL_DONEENA_SHIFT (12U) |
| #define DCC_DCCGCTRL_DONEENA_MASK (0x0000f000U) |
| #define DCC_DCCGCTRL_DONEENA_ENABLE (0xFU) |
| #define DCC_DCCGCTRL_DONEENA_DISABLE (0x5U) |
| #define DCC_DCCGCTRL_RES_SHIFT (16U) |
| #define DCC_DCCGCTRL_RES_MASK (0xffff0000U) |
| #define DCC_DCCREV_MINOR_SHIFT (0U) |
| #define DCC_DCCREV_MINOR_MASK (0x0000003fU) |
| #define DCC_DCCREV_CUSTOM_SHIFT (6U) |
| #define DCC_DCCREV_CUSTOM_MASK (0x000000c0U) |
| #define DCC_DCCREV_MAJOR_SHIFT (8U) |
| #define DCC_DCCREV_MAJOR_MASK (0x00000700U) |
| #define DCC_DCCREV_RTL_SHIFT (11U) |
| #define DCC_DCCREV_RTL_MASK (0x0000f800U) |
| #define DCC_DCCREV_FUNC_SHIFT (16U) |
| #define DCC_DCCREV_FUNC_MASK (0x0fff0000U) |
| #define DCC_DCCREV_RES_SHIFT (28U) |
| #define DCC_DCCREV_RES_MASK (0x30000000U) |
| #define DCC_DCCREV_SCHEME_SHIFT (30U) |
| #define DCC_DCCREV_SCHEME_MASK (0xc0000000U) |
| #define DCC_DCCCNTSEED0_COUNTSEED0_SHIFT (0U) |
| #define DCC_DCCCNTSEED0_COUNTSEED0_MASK (0x000fffffU) |
| #define DCC_DCCCNTSEED0_RES_SHIFT (20U) |
| #define DCC_DCCCNTSEED0_RES_MASK (0xfff00000U) |
| #define DCC_DCCVALIDSEED0_VALIDSEED0_SHIFT (0U) |
| #define DCC_DCCVALIDSEED0_VALIDSEED0_MASK (0x0000ffffU) |
| #define DCC_DCCVALIDSEED0_RES_SHIFT (16U) |
| #define DCC_DCCVALIDSEED0_RES_MASK (0xffff0000U) |
| #define DCC_DCCCNTSEED1_COUNTSEED1_SHIFT (0U) |
| #define DCC_DCCCNTSEED1_COUNTSEED1_MASK (0x000fffffU) |
| #define DCC_DCCCNTSEED1_RES_SHIFT (20U) |
| #define DCC_DCCCNTSEED1_RES_MASK (0xfff00000U) |
| #define DCC_DCCSTAT_ERRFLG_SHIFT (0U) |
| #define DCC_DCCSTAT_ERRFLG_MASK (0x00000001U) |
| #define DCC_DCCSTAT_DONEFLG_SHIFT (1U) |
| #define DCC_DCCSTAT_DONEFLG_MASK (0x00000002U) |
| #define DCC_DCCSTAT_RES_SHIFT (2U) |
| #define DCC_DCCSTAT_RES_MASK (0xfffffffcU) |
| #define DCC_DCCCNT0_COUNT0_SHIFT (0U) |
| #define DCC_DCCCNT0_COUNT0_MASK (0x000fffffU) |
| #define DCC_DCCCNT0_RES_SHIFT (20U) |
| #define DCC_DCCCNT0_RES_MASK (0xfff00000U) |
| #define DCC_DCCVALID0_VALID0_SHIFT (0U) |
| #define DCC_DCCVALID0_VALID0_MASK (0x0000ffffU) |
| #define DCC_DCCVALID0_RES_SHIFT (16U) |
| #define DCC_DCCVALID0_RES_MASK (0xffff0000U) |
| #define DCC_DCCCNT1_COUNT1_SHIFT (0U) |
| #define DCC_DCCCNT1_COUNT1_MASK (0x000fffffU) |
| #define DCC_DCCCNT1_RES_SHIFT (20U) |
| #define DCC_DCCCNT1_RES_MASK (0xfff00000U) |
| #define DCC_DCCCLKSRC1_CLKSRC_SHIFT (0U) |
| #define DCC_DCCCLKSRC1_CLKSRC_MASK (0x0000000fU) |
| #define DCC_DCCCLKSRC1_CLKSRC_0 (0x0U) |
| #define DCC_DCCCLKSRC1_CLKSRC_1 (0x1U) |
| #define DCC_DCCCLKSRC1_CLKSRC_2 (0x2U) |
| #define DCC_DCCCLKSRC1_CLKSRC_3 (0x3U) |
| #define DCC_DCCCLKSRC1_CLKSRC_4 (0x4U) |
| #define DCC_DCCCLKSRC1_CLKSRC_5 (0x5U) |
| #define DCC_DCCCLKSRC1_CLKSRC_6 (0x6U) |
| #define DCC_DCCCLKSRC1_CLKSRC_7 (0x7U) |
| #define DCC_DCCCLKSRC1_CLKSRC_8 (0x8U) |
| #define DCC_DCCCLKSRC1_CLKSRC_OTHER (0xFU) |
| #define DCC_DCCCLKSRC1_RES1_SHIFT (4U) |
| #define DCC_DCCCLKSRC1_RES1_MASK (0x00000ff0U) |
| #define DCC_DCCCLKSRC1_KEY_SHIFT (12U) |
| #define DCC_DCCCLKSRC1_KEY_MASK (0x0000f000U) |
| #define DCC_DCCCLKSRC1_KEY_ENABLE (0xAU) |
| #define DCC_DCCCLKSRC1_KEY_DISABLE (0x0U) |
| #define DCC_DCCCLKSRC1_RES0_SHIFT (16U) |
| #define DCC_DCCCLKSRC1_RES0_MASK (0xffff0000U) |
| #define DCC_DCCCLKSRC0_CLKSRC0_SHIFT (0U) |
| #define DCC_DCCCLKSRC0_CLKSRC0_MASK (0x0000000fU) |
| #define DCC_DCCCLKSRC0_CLKSRC0_0 (0x0U) |
| #define DCC_DCCCLKSRC0_CLKSRC0_1 (0x1U) |
| #define DCC_DCCCLKSRC0_CLKSRC0_2 (0x2U) |
| #define DCC_DCCCLKSRC0_RES1_SHIFT (4U) |
| #define DCC_DCCCLKSRC0_RES1_MASK (0x00000ff0U) |
| #define DCC_DCCCLKSRC0_KEY_SHIFT (12U) |
| #define DCC_DCCCLKSRC0_KEY_MASK (0x0000f000U) |
| #define DCC_DCCCLKSRC0_KEY_ENABLE (0xAU) |
| #define DCC_DCCCLKSRC0_KEY_DISABLE (0x0U) |
| #define DCC_DCCCLKSRC0_RES0_SHIFT (16U) |
| #define DCC_DCCCLKSRC0_RES0_MASK (0xffff0000U) |
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