2.3. Release Notes - 08_06_00¶
2.3.1. Introduction¶
This release notes provides important information that will assist you in using the PDK software package for the Jacinto family of devices. This document provides the product information and known issues that are specific to the PDK software package.
New features added / supported is listed below and defects fixed are highlighted in Fixed Issues. Also please check Upgrade and Compatibility for backward compatibility
2.3.2. What’s New¶
ID |
Description |
Module |
Supported Platforms |
|---|---|---|---|
NA |
NONE |
NA |
NA |
2.3.3. Upgrade and Compatibility¶
2.3.3.1. PDK¶
Added new target, namely safertos_examples, to build all SafeRTOS examples supported by PDK.
For Example:
make -sj custom_target BUILD_TARGET_LIST_ALL=safertos_examples BOARD=<board> BUILD_PROFILE_LIST_ALL=<list_of_build_profiles>
2.3.3.2. SafeRTOS¶
SafeRTOS examples earlier named as test_task_switch_safertos and safertos_test_ut are now renamed as task_switch_safertos and unit_test_safertos respectively.
2.3.3.3. OSAL¶
For SafeRTOS, all tasks are created with FPU enabled.
clockfxn paramater for ClockP_create is updated from type ‘void*’ to function pointer of type ClockP_FxnCallback
void (*ClockP_FxnCallback)(void *args);
2.3.3.4. RTOS¶
C7X support files such as boot.c, Startup.c, Cache.c, etc, are moved to the CSL layer. They were earlier part of the respective RTOS portable layer.
2.3.3.5. OSPI¶
A New parameter “opMode” is added to CSL_ospiConfigPhyDLL() API. This lets user to configure Phy to operate in either master mode or bypass mode.
2.3.4. Device Support¶
J721E SR1.1, J721E-HS SR1.1 (BOARD=j721e_evm)
Associated TIFS versions:
TIFS name
J721E SR revision
tifs.bin
SR1.0 & SR1.1 GP
tifs-hs-enc.bin
SR1.0 HS
tifs-sr1.1-hs-enc.bin
SR1.1 HS
2.3.5. Validation Information¶
For details on the validated examples refer to the platform specific test report available here.
2.3.6. Tool Chain Information¶
Component |
Version |
|---|---|
FreeRTOS Kernel |
10.5.1 |
lwIP stack |
2.1.2 |
lwIP-contrib |
2.1.0 |
TI ARM CLANG |
1.3.0.LTS |
PRU code generation tools |
2.3.3 |
GCC ARM code generation tools |
ARCH64 9.2-2019.12 |
CGT XML Processing Scripts |
2.61.00 |
System Analyzer (UIA Target) |
2_30_01_02 |
Component |
Version |
|---|---|
TI C6x code generation tools |
8.3.7 |
TI C7x code generation tools |
3.1.0.LTS |
2.3.7. Change Request¶
Refer to monthly roadmap slides for changes in the planned features
2.3.8. Fixed Issues¶
ID |
Head Line |
Module |
Affected Versions |
Affected Platforms |
|---|---|---|---|---|
CSIRX: Incorrect DATA Shift value for RAW8 mode |
CSI2RX |
08.04.00 |
J721E, J721S2, J784S4 |
|
CSIRX: Incorrect Dual Pixel mode for YUV422 |
CSI2RX |
08.04.00 |
J721E, J721S2, J784S4 |
|
Heap OSAL hangs if previous allocation has buffer overflow |
OSAL |
08.02.00 |
J721E, J721S2 |
|
[DSS] HPD Pulse event is not handled in the eDP driver |
DSS |
08.02.00 |
J721E, J721S2, J784S4 |
|
SciServer: Multiple definition of Hwi Data |
SCICLIENT |
08.04.00 |
J721E, J7200, J721S2, J784S4 |
|
MCSPI DMA does not support 48bit address space |
MCSPI |
08.04.00 |
J721E, J7200, J721S2, J784S4 |
|
FreeRTOS taskLoad is not proper |
OSAL |
08.02.00 |
J721E, J7200, J721S2, J784S4 |
|
Non-supported Sciclient APIs are present in header files |
SCICLIENT |
08.04.00 |
J721E, J7200, J721S2, J784S4 |
|
SBL: SBL_authentication() function is not defined |
SBL |
08.05.00 |
J721E, J7200, J721S2, J784S4 |
|
[VISS]: RGB output from VISS does not work |
VHWA |
08.05.00 |
J721E, J721S2 |
|
IPC: ipc_echo_testb image for mcu1_0 fails to boot on QNX (SPL boot) |
IPC |
08.05.00 |
J721E |
|
OSPI PHY Tuning - DLL Half Clock Lock Mode w/ DTR enabled |
OSPI |
08.02.00 |
J721E, J7200, J721S2, J784S4 |
|
xUsingFPU as pdTRUE should be supported on SAFERTOS |
OSAL |
08.04.00 |
J721E |
2.3.9. Known Issues¶
ID |
Head Line |
Module |
Reported in Release |
Affected Platforms |
Impact |
Workaround in this release |
|---|---|---|---|---|---|---|
Pulsar (R5F) : High priority interrupt is missed by VIM |
CSL, OSAL |
07.00.00 |
J721E, J7200 |
Baremetal implementation is pending |
Use RTOS instead of baremetal |
|
UART : Potential interrupt storm |
UART |
07.02.00 |
J7200, J721E |
Error interrupt resulting in hang. |
None |
|
[SPI] DMA mode does not work for SPI5 |
McSPI |
07.01.00 |
J721E |
Cannot use DMA with SPI5 |
Disable DMA for SPI5 OR use another instance of SPI |
|
[SPI] Transfer stalls when transfer length is not multiple of FIFO length in DMA mode |
McSPI |
07.02.00 |
J721E |
Cannot transfer data if data size is not multiple of FIFO length in DMA mode |
Use transfer size in multiple of FIFO length |
|
UDMA MCU NAVSS Channel Num 5 is not functional, when booting the application using the SBL bootloader. |
UDMA |
07.01.00 |
J721E |
Low Impact. UDMA MCU NAVSS Channel 5 can’t be used when booting the application using the SBL bootloader. |
Use any other channel. In the defaultBoardCfg Channel no. 5 is not used. The issue will be seen only when the boardcfg is updated to use channel 5. |
|
MCU/Main NAVSS UDMA memcpy from L2SRAM fails |
UDMA |
07.00.00 |
J721E |
Transfer works fine when source buffer, destination buffer and TRPD buffers are in L2SRAM. The issue happens only when the ring memory is in L2SRAM location |
Use ring memory from non-L2SRAM location |
|
Output mismatch when each region requiring 3 TRs |
VHWA |
01.00.00 |
J721E |
In multi-region mode with more then 3 TR per region can’t be used |
In multi-region mode for each region less than 3 TR should be used |
|
Sciclient Firewall Testapp Fails on HS Device |
SCICLIENT |
07.03.00 |
J721E-HS |
None |
None |
|
IPC Performance Test hangs after loading the binary |
IPC |
08.01.00 |
J721E, J7200 |
The app won’t work for this release |
None |
|
MCU Only Mode: IPC attachment with remote cores fail |
LPM |
08.02.00 |
J721E |
None |
None |
|
MCU Only Mode - Linux boot fails on A72 core |
LPM |
08.02.00 |
J721E |
None |
None |
|
USART: Spurious DMA Interrupts |
UART |
08.04.00 |
J721E, J7200, J721S2 |
None |
None |
|
USART: Erroneous clear/trigger of timeout interrupt |
UART |
08.02.00 |
J721E, J7200, J721S2 |
None |
None |
|
Main Domain GPIO does not service interrupts |
GPIO |
08.04.00 |
J721E, J7200 |
None |
None |
|
IPC: stack corruption of taskWaiter used in RPMessage_getRemoteEndPt |
IPC |
08.00.00 |
J721E, J7200, J721S2, J784S4 |
None |
Make taskWaiter element as global |
|
DSS: rxBuffer range check missing in DP_mailbox |
DSS |
08.04.00 |
J721E, J721S2, J784S4 |
DP sink module should not send message > 1 KB size |
None |
|
[DSS/eDP]: Busy Waiting in eDP driver causes hang |
DSS |
08.04.00 |
J721E, J721S2 |
Can cause hang in the display driver in case mailbox is empty. |
None |
|
[OSAL]: Mutex implementation uses recursive mutex of FreeRTOS |
OSAL |
08.05.00 |
J721E, J721S2, J784S4 |
Misleading naming convention of FreeRTOS Mutex APIs |
None |
|
[UART]: Driver does not support stop/timeout condition |
UART |
08.05.00 |
J721E |
Cannot use stop/timeout condition during reception of data |
None |
|
[DOF]: Predictors are reset in the SET_PARAMS control command |
VHWA |
08.05.00 |
J721E,J721S2 |
If the predictors are changed in the same handle,dof does not work and returns error in the SubmitRequest API |
None |
|
CSI-TX takes longer time to queue and dequeue in driver than expected. |
CSI2TX |
08.04.00 |
J721E |
Takes more time to transmit the frame than expected |
None |
|
J721S2/J784S4: Main2MCU IRQ Router allocations fail for output lines 32 to 41 |
SCICLIENT |
08.05.00 |
J721S2, J784S4 |
Cannot use Main2MCU IRQ Router allocations for output lines 32 to 41 |
None |
|
GLBCE is not correctly enabled in multi-handle scenario |
VHWA |
08.05.00 |
J721E, J721S2, J784S4 |
When VISS driver is used in multi-handle scenario with one of the handle having GLBCE disabled,driver does not enable GLBCE properly for the handles where it is enabled. |
None |
|
Assertion from EnetMcm_coreAttach API |
ENET |
08.01.00 |
J721E, J7200, J784S4 |
Race condition in MCM cmd handling in ETHFW usecases |
None |
|
Cable connect/disconnect can cause CPSW unrecoverable condition |
ENET |
08.00.00 |
J721E, J7200, J784S4 |
Packets will be dropped on the affected MAC port |
None. Device reboot is required |
2.3.10. Limitations¶
2.3.10.1. PDK¶
PDK examples do not support SMP mode. Some of examples still support build in SMP mode but these binaries are not supported or validated.
TI Clang compiler does not enable O3 optimization level and Thumb2 mode which were enabled by default with TI ARM CGT compiler. This has an impact on driver throughput. E.g. Ethernet performance has reduced by ~20% on J721E
The PMU counter overflow is not handled in Baremetal for use of CycleprofilerP APIs or the TimerP_getTimeInUsecs API.
Applications can periodically use the CycleprofilerP_refreshCounter to check overflow and refresh the higher bits of the PMU counter.
2.3.10.2. ENET¶
Scatter-gather functionality is currently supported only for packet transmission.
2.3.10.3. SafeRTOS¶
OSAL APIs namely, HwiP_disable and HwiP_restore can only be called from a privileged mode. These APIs will give an assertion error for an unprivileged context.
None.