2.6. Release Notes - 08_02_00¶
2.6.1. Introduction¶
This release notes provides important information that will assist you in using the PDK software package for the Jacinto family of devices. This document provides the product information and known issues that are specific to the PDK software package.
New features added / supported is listed below and defects fixed are highlighted in Fixed Issues. Also please check Upgrade and Compatibility for backward compatibility
2.6.2. What’s New¶
ID |
Description |
Module |
Supported Platforms |
|---|---|---|---|
PDK-10498 |
MCU only mode: IPC re-attached after MAIN domain restart |
IPC |
J721E |
PDK-5377 |
SERDES sharing - support for configuring SERDES in R5-SBL |
SBL |
J721E |
PDK-10808 |
Memory benchmark applications should be part of the standard SDK |
COMMON |
J721E, J7200 |
2.6.3. Upgrade and Compatibility¶
2.6.3.1. FreeRTOS¶
By default all the tasks will be created with floating point context enabled; i.e, save/restore of FPU Registers will be performed during each task switch.
Until last release, this was not enabled and any task that required floating point hardware had to call portTASK_USES_FLOATING_POINT.
For more details, refer Task FPU context
2.6.4. Device Support¶
J721E EVM SR1.0 and SR1.1, J721E-HS EVM (BOARD=j721e_evm)
Associated TIFS versions:
TIFS name
J721E SR revision
tifs.bin
SR1.0 & SR1.1 GP
tifs-hs-enc.bin
SR1.0 HS
tifs-sr1.1-hs-enc.bin
SR1.1 HS
2.6.5. Validation Information¶
For details on the validated examples refer to the platform specific test report available here.
2.6.6. Tool Chain Information¶
Component |
Version |
|---|---|
FreeRTOS Kernel |
10.5.1 |
lwIP stack |
2.1.2 |
lwIP-contrib |
2.1.0 |
TI ARM CLANG |
1.3.0.LTS |
PRU code generation tools |
2.3.3 |
GCC ARM code generation tools |
ARCH64 9.2-2019.12 |
CGT XML Processing Scripts |
2.61.00 |
System Analyzer (UIA Target) |
2_30_01_02 |
Component |
Version |
|---|---|
TI C6x code generation tools |
8.3.7 |
TI C7x code generation tools |
2.1.1.LTS |
2.6.7. Change Request¶
ID |
Head Line |
Original Fix Version |
New Fix Version |
|---|---|---|---|
PDK-10708 |
PDK Support for XIP with ECC enabled |
08.02.00 |
09.00.00 |
PDK-9473 |
Safety Compliance for SCICLIENT |
08.02.00 |
08.06.00 |
PDK-9351 |
Example to configure Timer Manager module |
08.02.00 |
09.00.00 |
PDK-5381 |
R5-SBL - Support to dump EEPROM to shared memory |
08.02.00 |
08.06.00 |
PDK-9540 |
Defer DDR Register Write Verification to later stage |
08.02.00 |
08.04.00 |
PDK-5365 |
Board: ECC support in BOARD OSPI Flash Driver |
08.02.00 |
09.00.00 |
JACINTOREQ-2449 |
C7x/C66x SafeRTOS support descope |
08.02.00 |
08.04.00 |
JACINTOREQ-2439 |
Ethernet: Defer CPSW EST and IET features in Enet LLD and EthFw |
08.02.00 |
09.0x.00 |
2.6.8. Fixed Issues¶
ID |
Head Line |
Module |
Affected Versions |
Affected Platforms |
|---|---|---|---|---|
Conflicting library definitions for __mpu_init() when using Clang compiler |
CSL |
08.01.00 |
J721E, J7200, AM65xx |
|
Enet: High packet drop in iperf UDP test |
ENET |
08.01.00 |
J721E, J7200, AM65xx |
|
SBL should avoid hardcoding 0xBAD00000 in many places |
SBL |
08.01.00 |
J721E, J7200, AM65xx |
|
The number of McSPI instances are only 5 in SPI driver |
McSPI |
08.01.00 |
J721E, J7200, AM65xx |
|
IPC: Documentation is ambiguous w.r.t buffer size |
IPC |
08.01.00 |
J721E, J7200, AM65xx |
|
LPM module is incorrectly packaged in SDK8.1 |
LPM |
08.01.00 |
J721E, J7200 |
|
LPM module uses SBL_INVALID_CORE instead of SBL_INVALID_ID |
LPM |
08.01.00 |
J721E, J7200 |
|
XIP memory benchmarking app fails for J721e/J7200 |
CSL |
08.01.00 |
J721E, J7200 |
|
DDR dual core memory benchmarking app is not working for J721e/J7200 |
CSL |
08.01.00 |
J721E, J7200 |
|
XIP dual core memory benchmarking app is not working for J721e/J7200 |
CSL |
08.01.00 |
J721E, J7200 |
|
MCU2 core diagnostic tests not running through sbl |
BOARD |
07.00.00 |
J721E |
|
Display port (eDP) diagnostic test failure |
BOARD |
07.00.00 |
J721E |
|
MCU only mode: handler for TISCI_MSG_SYS_RESET should clear current owner from ACL for MAIN cores |
SCICLIENT |
08.00.00 |
J721E |
|
[CSITX]: Infinite loop when initializing csitx driver, in lane ready function |
CSI2TX |
07.03.00 |
J721E |
|
Incorrect bin file for encrypting binary image |
COMMON |
07.03.00 |
J721E |
|
[DSSM2M] DSS M2M driver does not return error for unsupported format |
DSS |
07.03.00 |
J721E |
|
Semaphore not deleted in capture driver |
CSI2RX |
08.01.00 |
J721E |
|
Windows Build in SDK8.1 fails due to dependency on xdctools_3_61_04_40_core |
COMMON |
08.01.00 |
J721E |
|
SBL: Combined boot image: Seeing seg-fault when including all 8 remote core images |
SBL |
08.01.00 |
J721E |
|
OSAL: TimerP module restricts usage of up to max 4 DMTimer for R5Fs |
OSAL |
08.01.00 |
J721E |
|
Memory Benchmarking App does not finish on MCU2_0 |
CSL |
08.01.00 |
J721E |
2.6.9. Known Issues¶
ID |
Head Line |
Module |
Reported in Release |
Affected Platforms |
Impact |
Workaround in this release |
|---|---|---|---|---|---|---|
Pulsar (R5F) : High priority interrupt is missed by VIM |
CSL, OSAL |
07.00.00 |
J721E, J7200, AM65xx |
Baremetal implementation is pending |
Use RTOS instead of baremetal |
|
ICSS V1 CSL not up to date with ICSSG |
CSL |
07.00.00 |
J721E, AM65xx |
None |
Patch available. Will be included in next release |
|
UART : Potential interrupt storm |
UART |
07.02.00 |
J7200, J721E |
Error interrupt resulting in hang. |
None |
|
[SPI] DMA mode does not work for SPI5 |
McSPI |
07.01.00 |
J721E |
Cannot use DMA with SPI5 |
Disable DMA for SPI5 OR use another instance of SPI |
|
[SPI] Transfer stalls when transfer length is not multiple of FIFO length in DMA mode |
McSPI |
07.02.00 |
J721E |
Cannot transfer data if data size is not multiple of FIFO length in DMA mode |
Use transfer size in multiple of FIFO length |
|
J721E: MCU Timer 0 is not usable from application (sysbios) with SBL |
OSAL, SBL |
07.01.00 |
J721E |
None |
Use any other timer |
|
UDMA MCU NAVSS Channel Num 5 is not functional, when booting the application using the SBL bootloader. |
UDMA |
07.01.00 |
J721E |
Low Impact. UDMA MCU NAVSS Channel 5 can’t be used when booting the application using the SBL bootloader. |
Use any other channel. In the defaultBoardCfg Channel no. 5 is not used. The issue will be seen only when the boardcfg is updated to use channel 5. |
|
MCU/Main NAVSS UDMA memcpy from L2SRAM fails |
UDMA |
07.00.00 |
J721E |
Transfer works fine when source buffer, destination buffer and TRPD buffers are in L2SRAM. The issue happens only when the ring memory is in L2SRAM location |
Use ring memory from non-L2SRAM location |
|
Output mismatch when each region requiring 3 TRs |
VHWA |
01.00.00 |
J721E |
In multi-region mode with more then 3 TR per region can’t be used |
In multi-region mode for each region less than 3 TR should be used |
|
SBL prebuild binary for J721E HS doesn’t work from package |
SBL |
07.03.00 |
J721E-HS |
None |
Cleanup the SBL library and re-build the SBL image for HS. Commands: - Clean sbl_lib_uart (make sbl_lib_uart_clean) - Build for HS (make -sj sbl_uart_img_hs) |
|
Sciclient Firewall Testapp Fails on HS Device |
SCICLIENT |
07.03.00 |
J721E-HS |
None |
None |
|
IPC Performance Test hangs after loading the binary |
IPC |
08.01.00 |
J721E, J7200, AM65xx |
The app won’t work for this release |
None |
|
[DSS]: Add support for lane speed for the DSI output |
DSS |
07.03.00 |
J721E |
DSI driver cannot be used for different lane speeds |
None |
|
SPI instance should be decided by SPI driver and not Board Module |
OSPI |
08.01.00 |
J721E, J7200, AM65xx |
None |
None |
|
SPI driver does not support all instances with SPI_open |
McSPI |
08.02.00 |
J721E, J7200, AM65xx |
Customer cannot use all SPI instances supported by SoC |
None |
|
[SBL] SBL should not copy build folder contents to board folder during packaging |
SBL |
08.01.00 |
J721E, J7200, AM65xx |
None |
None |
|
ACK/NACK is send for TISCI messages without AOP flag |
Sciclient |
08.01.00 |
J721E, J7200 |
None |
None |
|
keywriter: smek gets generated even when argument not specified |
Security |
08.01.00 |
J721E, J7200 |
None |
None |
|
UART instances 3-9 does not work on MAIN R5 in interrupt mode |
UART |
08.01.00 |
J721E, J7200 |
User needs to add interrupt configuration |
None |
|
DMA Utils examples are broken with SDK |
UDMA |
08.00.00 |
J721E |
None |
User can run example with FreeRTOS |
|
Sciclient_pmSetModuleClkFreq returns fail when called from SBL_SlaveCoreBoot for c66 |
SBL |
08.00.00 |
J721E |
None |
None |
|
M2M colour space conversion from RGB24 to YUV420SP fails |
DSS |
08.02.00 |
J721E |
None |
None |
|
CSL: Sierra SerDes Instance 1 Lane Control is Incorrect |
CSL |
08.01.00 |
J721E |
None |
None |
|
DSS M2M testapp fails when run for scaling |
DSS |
08.02.00 |
J721E |
None |
None |
|
Facing issue with resolution change in DSS_M2M node |
DSS |
08.01.00 |
J721E |
None |
None |
|
MCU Only Mode: IPC attachment with remote cores fail |
LPM |
08.02.00 |
J721E |
None |
None |
|
MCU Only Mode - Linux boot fails on A72 core |
LPM |
08.02.00 |
J721E |
None |
None |
2.6.10. Limitations¶
2.6.10.1. PDK¶
PDK examples do not support SMP mode. Some of examples still support build in SMP mode but these binaries are not supported or validated.
TI Clang compiler does not enable O3 optimization level and Thumb2 mode which were enabled by default with TI ARM CGT compiler. This has an impact on driver throughput. E.g. Ethernet performance has reduced by ~20% on J721E
2.6.10.2. ENET¶
lwIP stack integration doesn’t support checksum hardware-offload feature.