2.7. Release Notes - 08_01_00¶
2.7.1. Introduction¶
This release notes provides important information that will assist you in using the PDK software package for the Jacinto family of devices. This document provides the product information and known issues that are specific to the PDK software package.
New features added / supported is listed below and defects fixed are highlighted in Fixed Issues. Also please check Upgrade and Compatibility for backward compatibility
2.7.2. What’s New¶
ID |
Description |
Module |
Supported Platforms |
|---|---|---|---|
JACINTOREQ-1168 |
SDK shall support migration to LLVM/TI CLANG |
COMMON |
J721E, J7200, AM65XX |
JACINTOREQ-473 |
MCU only mode - Ability to restart Main domain |
LPM |
J721E |
JACINTOREQ-1162 |
PDK shall support FreeRTOS on the C7x for CPU |
FreeRTOS |
J721E |
PDK-10387 |
PDK OSAL Support for FreeRTOS on C66x/C7x |
OSAL |
J721E |
JACINTOREQ-1229 |
PDK shall support migration of C6x/C7x drivers to FreeRTOS |
COMMON |
J721E |
PDK-9714 |
FreeRTOS ROV Support |
FreeRTOS |
J721E |
PDK-9546 |
SafeRTOS Support on R5 for CPU |
SafeRTOS |
J721E |
PDK-9534 |
PDK shall support running SafeRTOS Integration Tests running on R5F |
SafeRTOS |
J721E |
JACINTOREQ-1098 |
PMIC LLD shall configure voltage, current, power good and thermal monitor |
PMIC |
J721E, J7200 |
JACINTOREQ-1090 |
PMIC LLD shall support Watchdog in Trigger and Q&A Mode |
PMIC |
J721E, J7200 |
JACINTOREQ-1086 |
PMIC LLD shall support TPS6594x Leo PMIC |
PMIC |
J721E, J7200 |
JACINTOREQ-1092 |
PMIC LLD shall decipher error events and call out to application with error code |
PMIC |
J721E, J7200 |
JACINTOREQ-1097 |
PMIC LLD shall support CRC |
PMIC |
J721E, J7200 |
JACINTOREQ-1088 |
PMIC LLD shall support I2C and SPI communication interface |
PMIC |
J721E, J7200 |
JACINTOREQ-1104 |
PMIC LLD shall support PFSM states |
PMIC |
J721E, J7200 |
JACINTOREQ-1094 |
PMIC LLD shall support Low Power modes |
PMIC |
J721E, J7200 |
JACINTOREQ-1089 |
PMIC LLD shall configure RTC for PMIC low power |
PMIC |
J721E, J7200 |
JACINTOREQ-1416 |
PMIC LLD shall support DDR Retention mode |
PMIC |
J721E, J7200 |
JACINTOREQ-1091 |
PMIC LLD shall configure GPIO Pin Functionality |
PMIC |
J721E, J7200 |
JACINTOREQ-1093 |
PMIC LLD shall configure BUCK and LDO regulator output voltages |
PMIC |
J721E, J7200 |
JACINTOREQ-1103 |
PMIC LLD shall support ESM for MCU and SOC Errors |
PMIC |
J721E, J7200 |
JACINTOREQ-494 |
Enet LLD: CPSW Inter clients (cores) packet communication |
ENET |
J721E, J7200 |
ETHFW-1711 |
Enet LLD: Support MAC only mode of operation for few CPSW switch ports |
ENET |
J721E, J7200 |
2.7.3. Upgrade and Compatibility¶
2.7.3.1. FreeRTOS¶
This release introduces FreeRTOS Support for J721E PDK Drivers/Examples on C66x/C7x cores.
PDK drivers/examples are migrated and validated with FreeRTOS running in C66x/C7x cores.
FreeRTOS is not supported on A72 core.
FreeRTOS support is availble on all other cores. ( R5F, C66x, C7x )
FreeRTOS Real-time Object View (ROV) in CCS IDE is available for R5F, C66x cores.
See FreeRTOS Chapter for more details.
2.7.3.2. TI-RTOS(SysBIOS)¶
TI-RTOS(SysBIOS) is not supported on any cores from this release.
RTOS support on A72 is also descoped.
2.7.3.3. NDK¶
TI’s NDK TCP/IP stack is no longer supported on any cores.
lwIP is now the only TCP/IP stack supported in this release.
2.7.3.4. OSAL¶
Following OSAL APIs which supported only TI-RTOS(SysBIOS) are descoped in this release.
- EventP
EventP_pend()
Migrate to similar API EventP_wait() which is supported for FreeRTOS
- QueueP
Descoped API
Alternative API
Osal_Queue_Handle
QueueP_Handle
Osal_Queue_Elem
QueueP_Elem
Osal_Queue_construct + Osal_Queue_handle
QueueP_create
Osal_Queue_put
QueueP_put
Osal_Queue_get
QueueP_get
Osal_Queue_empty
QueueP_isEmpty
2.7.3.5. TI-CLANG¶
This release introduces TI ARM Clang tool-chain/compiler for MCU R5 cores
PDK drivers/examples are migrated from TI ARM CGT and validated with TI ARM Clang tool-chain.
Note: TI ARM Clang tool chain generated code/binary size is more than that of TI ARM CGT.
See TI ARM CLANG Usage and Migration Guidelines Chapter for more details.
2.7.3.6. LPM¶
LPM library provides APIs to transistion the SoC and PMIC from ACTIVE to MCU only mode and vice-versa.
SoC’s such as J721E, integrates a Micro Controller Unit Subsystem (MCU SS) as a chip-in-chip.
It can operate fully isolated from rest of the chip using a separate voltage supply, clock sources and resets and include the components needed for device management.
This allows the MCU SS to function continuously regardless of the state of the rest of the device.
Depending on the application needs, MCU only mode can be used for:
Reset & recovery of main domain functionality in case of detected failure.
As a low power mode of operation where in functionality implemented in MCU mode continues to be operational while rest of chip is powered down. In this case Software running on MCU domain can detect and process wakeup events and in response can reload and restart applications running in Main domain
See LPM Chapter for more details.
2.7.4. Device Support¶
J721E EVM SR1.0 and SR1.1, J721E-HS EVM (BOARD=j721e_evm)
Associated TIFS versions:
TIFS name
J721E SR revision
tifs.bin
SR1.0 & SR1.1 GP
tifs-hs-enc.bin
SR1.0 HS
tifs-sr1.1-hs-enc.bin
SR1.1 HS
2.7.5. Validation Information¶
For details on the validated examples refer to the platform specific test report available here.
2.7.6. Tool Chain Information¶
Component |
Version |
|---|---|
FreeRTOS Kernel |
10.5.1 |
lwIP stack |
2.1.2 |
lwIP-contrib |
2.1.0 |
TI ARM CLANG |
1.3.0.LTS |
PRU code generation tools |
2.3.3 |
GCC ARM code generation tools |
ARCH64 9.2-2019.12 |
CGT XML Processing Scripts |
2.61.00 |
System Analyzer (UIA Target) |
2_30_01_02 |
Component |
Version |
|---|---|
TI C6x code generation tools |
8.3.7 |
TI C7x code generation tools |
2.0.1.STS |
2.7.7. Change Request¶
ID |
Head Line |
Original Fix Version |
New Fix Version |
|---|---|---|---|
JACINTOREQ-1595 |
PDK: XIP With OTFA Support Descope |
08.01.00 |
None |
JACINTOREQ-2037 |
PMIC Safety requirements needs to be moved to 8.2 release |
08.01.00 |
08.02.00 |
JACINTOREQ-1861 |
SBL - Support to dump EEPROM is deferred to 8.2 release |
08.01.00 |
08.02.00 |
JACINTOREQ-1860 |
SERDES sharing feature in SBL deferred to 8.2 release |
08.01.00 |
08.02.00 |
JACINTOREQ-1596 |
PDK: C6x/C7x SafeRTOS support descope |
08.01.00 |
08.02.00 |
2.7.8. Fixed Issues¶
ID |
Head Line |
Module |
Affected Versions |
Affected Platforms |
|---|---|---|---|---|
CSL ECC test application fails on J721E |
CSL |
07.01.00 |
J721E |
|
[CSIRX]: hangs is observed when re-running example with different number of channels |
CSIRX |
07.03.00 |
J721E |
|
Examples: MAC loopback app test causes abort in debug mode during restart |
ENET |
08.00.00 |
J721E |
|
[CPSW] Packet drop with QSGMII ports IPerf |
ENET |
06.02.00 |
J721E, J7200 |
|
PLL1, PLL3 not enabled after MCU only to Active mode switch |
SCICLIENT |
08.00.00 |
J721E |
|
[DSS_M2M]: Assertion is observed in the DSS M2M driver when using it in multi-handle mode |
DSS |
08.00.00 |
J721E |
|
CUST SBL with SBL_SKIP_MCU_RESET should release MCU R5 before jumping to application |
SBL |
08.00.00 |
J721E |
|
C66 Cache OSAL for nonos is not optimal for larger buffers |
OSAL |
08.00.00 |
J721E |
|
MCU only mode: IPC re-attached after MAIN domain restart |
IPC |
08.00.00 |
J721E |
|
eDP firmware responds wrongly to some messages |
DSS |
08.00.00 |
J721E |
|
Make for sbl_multicore_amp fails with proper last core of mpu1_1 |
SBL |
08.00.00 |
J721E, J7200, AM65xx |
|
IPC: RPMessage heap is sized wrong and is causing heap corruption of Rx messages |
IPC |
08.00.00 |
J721E, J7200, AM65xx |
|
[DSS] Incorrect offset calculation in DSS for H/V flip |
DSS |
08.00.00 |
J721E |
2.7.9. Known Issues¶
ID |
Head Line |
Module |
Reported in Release |
Affected Platforms |
Impact |
Workaround in this release |
|---|---|---|---|---|---|---|
Pulsar (R5F) : High priority interrupt is missed by VIM |
CSL, OSAL |
07.00.00 |
J721E, J7200, AM65xx |
Baremetal implementation is pending |
Use RTOS instead of baremetal |
|
ICSS V1 CSL not up to date with ICSSG |
CSL |
07.00.00 |
J721E, AM65xx |
None |
Patch available. Will be included in next release |
|
UART : Potential interrupt storm |
UART |
07.02.00 |
J7200, J721E |
Error interrupt resulting in hang. |
None |
|
[SPI] DMA mode does not work for SPI5 |
McSPI |
07.01.00 |
J721E |
Cannot use DMA with SPI5 |
Disable DMA for SPI5 OR use another instance of SPI |
|
[SPI] Transfer stalls when transfer length is not multiple of FIFO length in DMA mode |
McSPI |
07.02.00 |
J721E |
Cannot transfer data if data size is not multiple of FIFO length in DMA mode |
Use transfer size in multiple of FIFO length |
|
J721E: MCU Timer 0 is not usable from application (sysbios) with SBL |
OSAL, SBL |
07.01.00 |
J721E |
None |
Use any other timer |
|
UDMA MCU NAVSS Channel Num 5 is not functional, when booting the application using the SBL bootloader. |
UDMA |
07.01.00 |
J721E |
Low Impact. UDMA MCU NAVSS Channel 5 can’t be used when booting the application using the SBL bootloader. |
Use any other channel. In the defaultBoardCfg Channel no. 5 is not used. The issue will be seen only when the boardcfg is updated to use channel 5. |
|
MCU/Main NAVSS UDMA memcpy from L2SRAM fails |
UDMA |
07.00.00 |
J721E |
Transfer works fine when source buffer, destination buffer and TRPD buffers are in L2SRAM. The issue happens only when the ring memory is in L2SRAM location |
Use ring memory from non-L2SRAM location |
|
MCU2 core diagnostic tests not running through sbl |
BOARD |
07.00.00 |
J721E |
None |
Use CCS/JTAG to run the tests |
|
Display port (eDP) diagnostic test failure |
BOARD |
07.00.00 |
J721E |
None |
Use display sample application |
|
Output mismatch when each region requiring 3 TRs |
VHWA |
01.00.00 |
J721E |
In multi-region mode with more then 3 TR per region can’t be used |
In multi-region mode for each region less than 3 TR should be used |
|
SBL prebuild binary for J721E HS doesn’t work from package |
SBL |
07.03.00 |
J721E-HS |
None |
Cleanup the SBL library and re-build the SBL image for HS. Commands: - Clean sbl_lib_uart (make sbl_lib_uart_clean) - Build for HS (make -sj sbl_uart_img_hs) |
|
Sciclient Firewall Testapp Fails on HS Device |
SCICLIENT |
07.03.00 |
J721E-HS |
None |
None |
|
MCU only mode: handler for TISCI_MSG_SYS_RESET should clear current owner from ACL for MAIN cores |
SCICLIENT |
08.00.00 |
J721E |
None |
None |
|
[CSITX]: Infinite loop when initializing csitx driver, in lane ready function |
CSI2TX |
07.03.00 |
J721E |
Driver hangs in failure scenario instead of timeout |
None |
|
Incorrect bin file for encrypting binary image |
COMMON |
07.03.00 |
J721E |
None |
None |
|
IPC Performance Test hangs after loading the binary |
IPC |
08.01.00 |
J721E, J7200, AM65xx |
The app won’t work for this release |
None |
|
Conflicting library definitions for __mpu_init() when using Clang compiler |
CSL |
08.01.00 |
J721E, J7200, AM65xx |
User should link libraries in correct order |
Ensure ti.csl.init.aer5f is the first library included and use –priority flag |
|
[DSSM2M] DSS M2M driver does not return error for unsupported format |
DSS |
07.03.00 |
J721E |
User can pass wrong inputs to driver and driver will not throw error |
User should pass correct parameters |
|
[DSS]: Add support for lane speed for the DSI output |
DSS |
07.03.00 |
J721E |
DSI driver cannot be used for different lane speeds |
None |
|
Enet: High packet drop in iperf UDP test |
ENET |
08.01.00 |
J721E, J7200, AM65xx |
iperf UDP test will not run successfully |
None |
2.7.10. Limitations¶
2.7.10.1. PDK¶
PDK examples do not support SMP mode. Some of examples still support build in SMP mode but these binaries are not supported or validated.
TI Clang compiler does not enable O3 optimization level and Thumb2 mode which were enabled by default with TI ARM CGT compiler. This has an impact on driver throughput. E.g. Ethernet performance has reduced by ~20% on J721E
C++ build is not supported in this release for TI Clang compiler. It will be added back in next release.
2.7.10.2. ENET¶
lwIP stack integration doesn’t support checksum hardware-offload feature.