MCUSW
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This files defines ETH MCAL configuration structures
Data Structures | |
struct | Eth_CpswConfigType |
Eth Cpsw Configurations type Configuration related to Cpsw data. More... | |
struct | Eth_Udma_RingCfgType |
struct | Eth_Udma_EventCfgType |
struct | Eth_Udma_RingEventCfgType |
Eth ring event configuration type Configuration related to ring event. More... | |
struct | Eth_FifoRingMapCfgType |
Eth Fifo ring map configuration type Configuration related to fifo map to ring. More... | |
struct | Eth_ChannelCfgType |
Eth channel configuration type Configuration related to channel. More... | |
struct | Eth_FlowCfgType |
Eth flow configuration type Configuration related to flow. More... | |
struct | Eth_ChannelFlowCfgType |
Eth channel flow configuration type Configuration related to channel flow. More... | |
struct | Eth_FifoHandleType |
Eth Fifo configuration type Configuration related to Fifo. More... | |
struct | Eth_Udma_CfgType |
Eth Udma configuration type Configuration related to Udma. More... | |
struct | Eth_VirtualMacConfigType |
Eth driver virtual mac configuration data Configuration related to virtual MAC configuration. More... | |
struct | Eth_HwTimerConfigType |
Eth driver hardware timer configuration data Configuration related to hardware timer. More... | |
struct | Eth_ControlerConfigType |
Eth controller configuration type Configuration related to Eth controller configuration. More... | |
struct | Eth_ConfigType |
Eth configuration type Configuration data of all controller. More... | |
Functions | |
VAR (uint8, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Egress_BufferMem_0[196608U] | |
VAR (Eth_DescType, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Egress_Descriptor_0[128U] | |
VAR (uint8, ETH_VAR_NO_INIT) Eth_Ctrl_0_Egress_BufferState_0[128U] | |
VAR (Eth_QueueType, ETH_VAR_NO_INIT) Eth_Ctrl_0_Egress_Queue_0[1U] | |
VAR (Eth_Udma_RingDynType, ETH_VAR_NO_INIT) Eth_RingDyn_Ctrl_0[6U] | |
void | EthApp_wbInvCache (uint8 *buf, uint16 len) |
Function to write-back and invalidate cache. More... | |
void | EthApp_wbCache (uint8 *buf, uint16 len) |
Function to write-back cache. More... | |
void | EthApp_invCache (uint8 *buf, uint16 len) |
Function to invalidate cache. More... | |
Variables | |
const Eth_Udma_RingCfgType | Eth_Udma_RingCfg_0 [6U] |
const Eth_Udma_EventCfgType | Eth_EventCfg_Ctrl_0 [2U] |
const Eth_Udma_RingEventCfgType | Eth_RingEventCfg_Ctrl_0 [2U] |
Enumerations | |
enum | Eth_MdioOperModeType { ETH_MDIO_OPMODE_NORMAL = 0x00U, ETH_MDIO_OPMODE_MANUAL = 0x01U } |
MDIO operating mode. More... | |
Macros | |
#define | ETH_VERSION_INFO_API (STD_ON) |
Enable/disable SPI get version info API. More... | |
#define | ETH_GLOBALTIMESUPPORT_API (STD_ON) |
Enable/disable Eth time sync related API. More... | |
#define | ETH_DEV_ERROR_DETECT (STD_ON) |
Enable/Disable Development Error Detection. More... | |
#define | ETH_GET_COUNTER_VALUES_API (STD_ON) |
Enable/disable Eth get counter values API. More... | |
#define | ETH_GET_RX_STATS_API (STD_ON) |
Enable/disable Eth get RX stats count API. More... | |
#define | ETH_GET_TX_STATS_API (STD_ON) |
Enable/disable Eth get TX stats count API. More... | |
#define | ETH_GET_TX_ERROR_COUNTERSVALUES_API (STD_ON) |
Enable/disable Eth get TX error stats count API. More... | |
#define | ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_ICMP (STD_OFF) |
Enable/disable Hardware Offloading for ICMP checksums. More... | |
#define | ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_IPV4 (STD_OFF) |
Enable/disable Hardware offloading for IPv4 Header checksums. More... | |
#define | ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_TCP (STD_OFF) |
Enable/disable Hardware offloading for TCP checksums. More... | |
#define | ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_UDP (STD_OFF) |
Enable/disable Hardware offloading for UDP checksums. More... | |
#define | ETH_ENABLE_MII_API (STD_ON) |
Enable/disable Eth MII related API. More... | |
#define | ETH_UPDATE_PHYS_ADDR_FILTER_API (STD_ON) |
Enable/disable optional API Eth_UpdatePhysAddrFilter. More... | |
#define | ETH_VIRTUALMAC_NOTIFYMSGRECEIVED_API (STD_OFF) |
Enable/disable optional API Eth_NotifyVirtmacMsgReceived. More... | |
#define | ETH_VIRTUALMAC_SUBSCRIBEALLTRAFFIC_API (STD_OFF) |
Enable/disable optional API Eth_DispatchVirtmacSubscribeAllTraffic. More... | |
#define | ETH_VIRTUALMAC_UNSUBSCRIBEALLTRAFFIC_API (STD_OFF) |
Enable/disable optional API Eth_DispatchVirtmacUnsubscribeAllTraffic. More... | |
#define | ETH_VIRTUALMAC_SUBSCRIBEDSTMAC_API (STD_OFF) |
Enable/disable optional API Eth_DispatchVirtmacSubscribeDstMac. More... | |
#define | ETH_VIRTUALMAC_UNSUBSCRIBEDSTMAC_API (STD_OFF) |
Enable/disable optional API Eth_DispatchVirtmacUnsubscribeDstMac. More... | |
#define | ETH_VIRTUALMAC_ASSOCIATEIPV4MACADDR_API (STD_OFF) |
Enable/disable optional API Eth_DispatchVirtmacAssociateIPv4Macaddr. More... | |
#define | ETH_VIRTUALMAC_DISASSOCIATEIPV4MACADDR_API (STD_OFF) |
Enable/disable optional API Eth_DispatchVirtmacDisassociateIPv4Macaddr. More... | |
#define | ETH_VIRTUALMAC_ADD_UNICAST_MACADDR_API (STD_OFF) |
Enable/disable optional API Eth_DispatchVirtmacAddUnicastAddr. More... | |
#define | ETH_VIRTUALMAC_ADD_MCAST_MACADDR_API (STD_OFF) |
Enable/disable optional API Eth_DispatchVirtmacAddMcastAddr. More... | |
#define | ETH_VIRTUALMAC_DEL_MACADDR_API (STD_OFF) |
Enable/disable optional API Eth_DispatchVirtmacDelAddr. More... | |
#define | ETH_VIRTUALMAC_SEND_CUSTOM_NOTIFY_API (STD_OFF) |
Enable/disable optional API Eth_SendCustomNotify. More... | |
#define | ETH_VIRTUALMAC_ADD_VLAN_API (STD_OFF) |
Enable/disable optional API Eth_DispatchVirtmacAddVlan. More... | |
#define | ETH_VIRTUALMAC_DEL_VLAN_API (STD_OFF) |
Enable/disable optional API Eth_DispatchVirtmacDelVlan. More... | |
#define | ETH_ISR_TYPE (ETH_ISR_CAT2) |
ISR type. More... | |
#define | ETH_OS_COUNTER_ID ((CounterType)OsCounter_0) |
Counter ID for counter used to count wait ticks. More... | |
#define | ETH_OS_COUNTER_FREQ (1000000000U) |
Frequency in Hz of the counter specified in ETH_OS_COUNTER_ID. More... | |
#define | ETH_VIRTUALMAC_SUPPORT (STD_OFF) |
Enable/disable Virtual MAC support. More... | |
#define | ETH_VIRTUALMAC_FWINFO_TIMEOUT (0U) |
Timeout value for Firmware Attach msg received from server. More... | |
#define | EthConf_EthCtrlConfig_EthConfig_0 (0U) |
Eth controller ID Configured controller ID(s) More... | |
#define | ETH_CTRL_ID_MAX (1u) |
Eth max controller ID. More... | |
#define | UDMA_WAIT_TEARDOWN_COUNTER (10000u) |
Eth DMA max teardown timeout. More... | |
#define | ETH_START_SEC_CONST_UNSPECIFIED |
#define | ETH_STOP_SEC_CONST_UNSPECIFIED |
#define | ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED_128 |
#define | ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED_128 |
#define | ETH_START_SEC_VAR_NO_INIT_8 |
#define | ETH_STOP_SEC_VAR_NO_INIT_8 |
#define | ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED |
#define | ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED |
#define | ETH_START_SEC_CODE |
#define | ETH_STOP_SEC_CODE |
Eth Service Ids | |
The Service Id is used to identify the source of an error when reported through the Det_ReportError() function. | |
#define | ETH_SID_INIT ((uint8) 0x01U) |
Eth_Init() API Service ID. More... | |
#define | ETH_SID_SET_CONTROLLER_MODE ((uint8) 0x03U) |
Eth_SetControllerMode() API Service ID. More... | |
#define | ETH_SID_GET_CONTROLLER_MODE ((uint8) 0x04U) |
Eth_GetControllerMode() API Service ID. More... | |
#define | ETH_SID_WRITE_MII ((uint8) 0x05U) |
Eth_WriteMii() API Service ID. More... | |
#define | ETH_SID_READ_MII ((uint8) 0x06U) |
Eth_ReadMii() API Service ID. More... | |
#define | ETH_SID_GET_COUNTER_STATE ((uint8) 0x07U) |
Eth_GetCounterState() API Service ID. More... | |
#define | ETH_SID_GET_PHYS_ADDR ((uint8) 0x08U) |
Eth_GetPhysAddr() API Service ID. More... | |
#define | ETH_SID_PROVIDE_TX_BUFFER ((uint8) 0x09U) |
Eth_ProvideTxBuffer() API Service ID. More... | |
#define | ETH_SID_MAIN_FUNCTION ((uint8) 0x0AU) |
Eth_MainFunction() API Service ID. More... | |
#define | ETH_SID_TRANSMIT ((uint8) 0x0BU) |
Eth_Transmit() API Service ID. More... | |
#define | ETH_SID_RECEIVE ((uint8) 0x0CU) |
Eth_Receive() API Service ID. More... | |
#define | ETH_SID_TX_CONFIRMATION ((uint8) 0x0EU) |
Eth_TxConfirmation() API Service ID. More... | |
#define | ETH_SID_GET_VERSION_INFO ((uint8) 0x0FU) |
Eth_GetVersionInfo() API Service ID. More... | |
#define | ETH_SID_RX_IRQ_HDLR ((uint8) 0x10U) |
Eth_RxIrqHdlr_<CtrlIdx>() API Service ID. More... | |
#define | ETH_SID_TX_IRQ_HDLR ((uint8) 0x11U) |
Eth_TxIrqHdlr_<CtrlIdx>() API Service ID. More... | |
#define | ETH_SID_UPDATE_PHYS_ADDR_FILTER ((uint8) 0x12U) |
Eth_UpdatePhysAddrFilter() API Service ID. More... | |
#define | ETH_SID_SET_PHYS_ADDR ((uint8) 0x13U) |
Eth_SetPhysAddr() API Service ID. More... | |
#define | ETH_SID_GET_COUNTER_VALUES ((uint8) 0x14U) |
Eth_GetCounterValues() API Service ID. More... | |
#define | ETH_SID_GET_RX_STATS ((uint8) 0x15U) |
Eth_GetRxStats() API Service ID. More... | |
#define | ETH_SID_GET_TX_STATS ((uint8) 0x1CU) |
Eth_GetTxStats() API Service ID. More... | |
#define | ETH_SID_GET_TXERROR_COUNTERVALUES ((uint8) 0x1DU) |
Eth_GetTxErrorCounterValues() API Service ID. More... | |
#define | ETH_SID_GET_CURRENT_TIME ((uint8) 0x16U) |
Eth_GetCurrentTime() API Service ID. More... | |
#define | ETH_SID_ENABLE_EGRESS_TIMESTAMP ((uint8) 0x17U) |
Eth_EnableEgressTimeStamp() API Service ID. More... | |
#define | ETH_SID_GET_EGRESS_TIMESTAMP ((uint8) 0x18U) |
Eth_GetEgressTimeStamp() API Service ID. More... | |
#define | ETH_SID_GET_INGRESS_TIMESTAMP ((uint8) 0x19U) |
Eth_GetIngressTimeStamp() API Service ID. More... | |
#define | ETH_SID_SET_CORRECTION_TIME ((uint8) 0x1AU) |
Eth_SetCorrectionTime() API Service ID. More... | |
#define | ETH_SID_SET_GLOBAL_TIME ((uint8) 0x1BU) |
Eth_SetGlobalTime() API Service ID. More... | |
#define | ETH_SID_DISPATCH_VIRTMAC_INIT ((uint8) 0x1CU) |
Eth_DispatchVirtmacInit() API Service ID. More... | |
#define | ETH_SID_DISPATCH_VIRTMAC_DEINIT ((uint8) 0x1DU) |
Eth_DispatchVirtmacDeinit() API Service ID. More... | |
#define | ETH_SID_NOTIFY_VIRTMAC_MSGRECV ((uint8) 0x1EU) |
Eth_NotifyVirtmacMsgRecv() API Service ID. More... | |
#define | ETH_SID_DISPATCH_VIRTMAC_SUBSCRIBE_ALLTRAFFIC ((uint8) 0x1FU) |
Eth_DispatchVirtmacSubscribeAllTraffic() API Service ID. More... | |
#define | ETH_SID_DISPATCH_VIRTMAC_UNSUBSCRIBE_ALLTRAFFIC ((uint8) 0x20U) |
Eth_DispatchVirtmacUnsubscribeAllTraffic() API Service ID. More... | |
#define | ETH_SID_DISPATCH_VIRTMAC_SUBSCRIBE_DSTMAC ((uint8) 0x21U) |
Eth_DispatchVirtmacSubscribeDstMac() API Service ID. More... | |
#define | ETH_SID_DISPATCH_VIRTMAC_UNSUBSCRIBE_DSTMAC ((uint8) 0x22U) |
Eth_DispatchVirtmacUnsubscribeDstMac() API Service ID. More... | |
#define | ETH_SID_DISPATCH_VIRTMAC_IPV4_MACADDR_ASSOCIATE ((uint8) 0x23U) |
Eth_DispatchVirtmacIPv4MacAddrAssociate() API Service ID. More... | |
#define | ETH_SID_DISPATCH_VIRTMAC_IPV4_MACADDR_DISASSOCIATE ((uint8) 0x24U) |
Eth_DispatchVirtmacIPv4MacAddrDisassociate() API Service ID. More... | |
#define | ETH_SID_DISPATCH_VIRTMAC_ADD_UNICAST_MACADDR ((uint8) 0x25U) |
Eth_DispatchVirtmacAddUnicastMacAddr() API Service ID. More... | |
#define | ETH_SID_DISPATCH_VIRTMAC_ADD_MCAST_MACADDR ((uint8) 0x26U) |
Eth_DispatchVirtmacAddMcastMacAddr() API Service ID. More... | |
#define | ETH_SID_DISPATCH_VIRTMAC_DEL_MACADDR ((uint8) 0x27U) |
Eth_DispatchVirtmacDelMacAddr() API Service ID. More... | |
#define | ETH_SID_DISPATCH_VIRTMAC_ADD_VLAN ((uint8) 0x28U) |
Eth_DispatchVirtmacAddVlan() API Service ID. More... | |
#define | ETH_SID_DISPATCH_VIRTMAC_DEL_VLAN ((uint8) 0x29U) |
Eth_DispatchVirtmacDelVlan() API Service ID. More... | |
#define | ETH_SID_SEND_CUSTOM_NOTIFY ((uint8) 0x2AU) |
Eth_SendCustomNotify() API Service ID. More... | |
#define | ETH_SID_VIRTMAC_RPC_INIT ((uint8) 0x2BU) |
Eth_VirtMacRpcInit() API Service ID. More... | |
#define | ETH_SID_SET_BANDWIDTH_LIMIT ((uint8) 0x2CU) |
Eth_SetBandwidthLimit() API Service ID. More... | |
#define | ETH_SID_GET_BANDWIDTH_LIMIT ((uint8) 0x2DU) |
Eth_GetBandwidthLimit() API Service ID. More... | |
#define | ETH_PRE_COMPILE_VARIANT (STD_ON) |
Eth configuration variant. More... | |
#define | ETH_LINK_TIME_VARIANT (STD_OFF) |
#define | ETH_POST_BUILD_VARIANT (STD_OFF) |
#define | ETH_DMA_IR_SUPPORT (STD_ON) |
Eth DMA feature flag support. More... | |
#define | ETH_DMA_CQ_RING_SUPPORT (STD_ON) |
#define | ETH_DMA_TEARDOWN_SUPPORT (STD_ON) |
#define | UDMA_DEVICE_ID_RING (235U) |
Eth DMA devices ID. More... | |
#define | UDMA_DEVICE_ID_UDMA (236U) |
#define | UDMA_DEVICE_ID_PSIL (232U) |
#define | UDMA_DEVICE_ID_IA (233U) |
#define | UDMA_DEVICE_ID_IR (237U) |
#define | UDMA_DEVICE_ID_CORE (250U) |
#define | UDMA_TX_CHANNEL_PEER_OFFSET (0xf000U) |
Eth DMA peer and thread offset. More... | |
#define | UDMA_RX_CHANNEL_PEER_OFFSET (0x7000U) |
#define | UDMA_SOURCE_THREAD_OFFSET (0x6000U) |
#define | UDMA_DEST_THREAD_OFFSET (0xe000U) |
#define | ETH_DMA_TX_BASE_REG (0x2aa00000U) |
Eth DMA base register address. More... | |
#define | ETH_DMA_RX_BASE_REG (0x2a800000U) |
#define | ETH_DMA_RINGRT_BASE (0x2b800000U) |
#define | ETH_DMA_RINGCFG_BASE (0x28440000U) |
#define | ETH_DMA_INTAGGR_INTR_BASE (0x2a700000U) |
#define | ETH_DMA_TXCRT_CHAN_CTL(CHAN) (0x00000000U + ((CHAN) * 0x1000U)) |
Eth DMA macro to calculate register address for DMA register address. More... | |
#define | ETH_DMA_TXCRT_CHAN_PEER8(CHAN) (0x00000220U + ((CHAN) * 0x1000U)) |
#define | ETH_DMA_RXCRT_CHAN_CTL(CHAN) (0x00000000U + ((CHAN) * 0x1000U)) |
#define | ETH_DMA_RXCRT_CHAN_PEER8(CHAN) (0x00000220U + ((CHAN) * 0x1000U)) |
#define | ETH_DMA_RINGRT_RING_FDB(RING) (0x00000010U + ((RING) * 0x1000U)) |
#define | ETH_DMA_RINGRT_RING_FOCC(RING) (0x00000018U + ((RING) * 0x1000U)) |
#define | ETH_DMA_RINGRT_RING_RDB(RING) (0x00000010U + ((RING) * 0x1000U)) |
#define | ETH_DMA_RINGRT_RING_ROCC(RING) (0x00000018U + ((RING) * 0x1000U)) |
#define | ETH_DMA_RINGCFG_RING_SIZE(RING) (0x00000048U + ((RING) * 0x100U)) |
#define | ETH_DMA_INTAGGR_INTR_VINT_ENABLE_SET(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000000U + ((VINT) * 0x1000U)) |
#define | ETH_DMA_INTAGGR_INTR_VINT_ENABLE_CLEAR(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000008U + ((VINT) * 0x1000U)) |
#define | ETH_DMA_INTAGGR_INTR_VINT_STATUS_SET(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000010U + ((VINT) * 0x1000U)) |
#define | ETH_DMA_INTAGGR_INTR_VINT_STATUS_CLEAR(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000018U + ((VINT) * 0x1000U)) |
#define | ETH_DMA_INTAGGR_INTR_VINT_STATUSM(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000020U + ((VINT) * 0x1000U)) |
#define | Eth_GetRingFDBReg(RingNum) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_FDB((RingNum))) |
#define | Eth_GetRingFOCCReg(RingNum) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_FOCC((RingNum))) |
#define | Eth_GetRingRDBReg(RingNum) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_RDB((RingNum))) |
#define | Eth_GetRingROCCReg(RingNum) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_ROCC((RingNum))) |
#define | Eth_GetRingSizeReg(RingNum) (ETH_DMA_RINGCFG_BASE + ETH_DMA_RINGCFG_RING_SIZE((RingNum))) |
#define | Eth_GetTxChannelCtlRegAddress(ChanId) (ETH_DMA_TX_BASE_REG + ETH_DMA_TXCRT_CHAN_CTL((ChanId))) |
#define | Eth_GetTxChannelPeer8RegAddress(ChanId) (ETH_DMA_TX_BASE_REG + ETH_DMA_TXCRT_CHAN_PEER8((ChanId))) |
#define | Eth_GetRxChannelCtlRegAddress(ChanId) (ETH_DMA_RX_BASE_REG + ETH_DMA_RXCRT_CHAN_CTL((ChanId))) |
#define | Eth_GetRxChannelPeer8RegAddress(ChanId) (ETH_DMA_RX_BASE_REG + ETH_DMA_RXCRT_CHAN_PEER8((ChanId))) |
#define | Eth_GetDem_E_HARDWARE_ERROR(CtrlIndex) ( ETH_DEM_NO_EVENT ) |
ETH DEM Error codes to report. More... | |
#define | Eth_GetDem_E_LATECOLLISION(CtrlIndex) ( ETH_DEM_NO_EVENT ) |
#define | Eth_GetDem_E_MULTIPLECOLLISION(CtrlIndex) ( ETH_DEM_NO_EVENT ) |
#define | Eth_GetDem_E_SINGLECOLLISION(CtrlIndex) ( ETH_DEM_NO_EVENT ) |
#define | Eth_GetDem_E_ALIGNMENT(CtrlIndex) ( ETH_DEM_NO_EVENT ) |
#define | Eth_GetDem_E_OVERSIZEFRAME(CtrlIndex) ( ETH_DEM_NO_EVENT ) |
#define | Eth_GetDem_E_UNDERSIZEFRAME(CtrlIndex) ( ETH_DEM_NO_EVENT ) |
#define | Eth_GetDem_E_CRC(CtrlIndex) ( ETH_DEM_NO_EVENT ) |
#define | Eth_GetDem_E_RX_FRAMES_LOST(CtrlIndex) ( ETH_DEM_NO_EVENT ) |
#define | Eth_GetDem_E_ACCESS(CtrlIndex) ( ETH_DEM_NO_EVENT ) |
#define | Eth_GetDem_E_TX_INTERNAL(CtrlIndex) ( ETH_DEM_NO_EVENT ) |
#define | Eth_IsVirtualMacModeEnable(CtrlIndex) ( FALSE ) |
Eth function like macro to access controler configuration. More... | |
#define | Eth_GetTxChannelThreadOffset(CtrlIndex) ( 0xf000U ) |
#define | Eth_VirtMacGetEthFwRpcComChannelId(CtrlIndex) ( 0xFFFFU ) |
#define | Eth_VirtMacGetEthPollRecvMsgInEthMain(CtrlIndex) ( FALSE ) |
#define | Eth_VirtMacGetRpcCmdCompleteFuncPtr(CtrlIndex) ( (Eth_RpcCmdComplete)NULL_PTR ) |
#define | Eth_VirtMacGetFwRegisterFuncPtr(CtrlIndex) ( (Eth_RpcFwRegistered)NULL_PTR ) |
#define | Eth_GetTxEnableInterrupt(CtrlIndex) ( TRUE ) |
#define | Eth_GetRxEnableInterrupt(CtrlIndex) ( TRUE ) |
#define | Eth_GetEnetType(CtrlIndex) ( ETH_ENETTYPE_CPSW2G ) |
#define | Eth_GetMacPortNum(CtrlIndex) ( ETH_PORT_MAC_PORT_1 ) |
#define | Eth_GetMacAddressHigh(CtrlIndex) ( 0xaabbccddU ) |
#define | Eth_GetMacAddressLow(CtrlIndex) ( 0xeeffU ) |
#define | Eth_UseDefaultMacAddress(CtrlIndex) ( TRUE ) |
#define | Eth_GetMiiConnectionType(CtrlIndex) ( ETH_MAC_CONN_TYPE_RGMII_FORCE_1000_FULL ) |
#define | Eth_GetLoopBackMode(CtrlIndex) ( FALSE ) |
#define | Eth_GetHardwareLoopTimeout(CtrlIndex) ( 32000U ) |
#define | Eth_GetEnableCacheOps(CtrlIndex) ( TRUE ) |
#define | Eth_GetCacheWritebackInvalidateFuncPtr(CtrlIndex) ( &EthApp_wbInvCache ) |
#define | Eth_GetCacheWritebackFuncPtr(CtrlIndex) ( &EthApp_wbCache ) |
#define | Eth_GetCacheInvalidateFuncPtr(CtrlIndex) ( &EthApp_invCache ) |
#define | Eth_DescriptorGetCacheWritebackInvalidateFuncPtr(CtrlIndex) ( Eth_GetCacheWritebackInvalidateFuncPtr(CtrlIndex) ) |
#define | Eth_DescriptorGetCacheWritebackFuncPtr(CtrlIndex) ( Eth_GetCacheWritebackFuncPtr(CtrlIndex) ) |
#define | Eth_DescriptorGetCacheInvalidateFuncPtr(CtrlIndex) ( Eth_GetCacheInvalidateFuncPtr(CtrlIndex) ) |
#define | Eth_RingGetCacheWritebackInvalidateFuncPtr(CtrlIndex) ( Eth_GetCacheWritebackInvalidateFuncPtr(CtrlIndex) ) |
#define | Eth_RingGetCacheWritebackFuncPtr(CtrlIndex) ( Eth_GetCacheWritebackFuncPtr(CtrlIndex) ) |
#define | Eth_RingGetCacheInvalidateFuncPtr(CtrlIndex) ( Eth_GetCacheInvalidateFuncPtr(CtrlIndex) ) |
#define | Eth_Cpsw_GetPhyMacRegAddr() ( 0x40f00200U ) |
#define | Eth_Cpsw_GetAleRegAddr() ( 0x4603e000U ) |
#define | Eth_Cpsw_GetCptsRegAddr() ( 0x4603d000U ) |
#define | Eth_Cpsw_GetMdioRegAddr() ( 0x46000f00U ) |
#define | Eth_Cpsw_GetCtrlRegAddr() ( 0x46020000U ) |
#define | Eth_Cpsw_GetCptsRefClockFreq() ( 1U ) |
#define | Eth_Cpsw_GetCppiClockFreq() ( 333333333U ) |
#define | Eth_Cpsw_GetMdioBusClockFreq(CtrlIndex) ( 2200000U ) |
#define | Eth_Cpsw_GetMdioOpMode(CtrlIndex) ( ETH_MDIO_OPMODE_MANUAL ) |
#define | Eth_GetRxMtuLength(CtrlIndex) ( 1522U ) |
#define | Eth_GetTxChanStartNum(CtrlIndex) ( 30U ) |
#define | Eth_GetRxChanStartNum(CtrlIndex) ( 30U ) |
#define | Eth_GetEgressFifoTotalNum(CtrlIndex) ( 1U ) |
#define | Eth_GetIngressFifoTotalNum(CtrlIndex) ( 1U ) |
#define | Eth_GetRingTotalNum(CtrlIndex) ( 6U ) |
#define | Eth_GetTxChanTotalNum(CtrlIndex) ( 1U ) |
#define | Eth_GetRxChanTotalNum(CtrlIndex) ( 1U ) |
#define | Eth_GetFlowTotalNumber(CtrlIndex) ( 1U ) |
#define | Eth_GetEventTotalNum(CtrlIndex) ( 2U ) |
#define | Eth_GetRingEventTotalNum(CtrlIndex) ( 2U ) |
#define | Eth_GetEgressFifoPacketNum(CtrlIndex, FifoIdx) ( 128U ) |
#define | Eth_GetEgressFifoPacketSize(CtrlIndex, FifoIdx) ( 1522U ) |
#define | Eth_GetIngressFifoPacketNum(CtrlIndex, FifoIdx) ( 128U ) |
#define | Eth_GetIngressFifoPacketSize(CtrlIndex, FifoIdx) ( 1522U ) |
#define | Eth_GetEgressFifoDescAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Egress_Descriptor_0[(DescIdx)] ) |
#define | Eth_GetEgressFifoDescUserInfoAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Egress_Descriptor_0[(DescIdx)].bufferInfo ) |
#define | Eth_GetEgressFifoBufferDataAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Egress_BufferMem_0[(DescIdx) * 1536U] ) |
#define | Eth_GetEgressFifoQueueAddress(CtrlIndex, FifoIdx) ( Eth_Ctrl_0_Egress_Queue_0 ) |
#define | Eth_GetEgressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx) ( Eth_Ctrl_0_Egress_BufferState_0[BufferIdx] ) |
#define | Eth_SetEgressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx, Val) ( Eth_Ctrl_0_Egress_BufferState_0[BufferIdx] = Val ) |
#define | Eth_GetIngressFifoDescAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Ingress_Descriptor_0[(DescIdx)] ) |
#define | Eth_GetIngressFifoDescUserInfoAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Ingress_Descriptor_0[(DescIdx)].bufferInfo ) |
#define | Eth_GetIngressFifoBufferDataAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Ingress_BufferMem_0[(DescIdx) * 1536U] ) |
#define | Eth_GetIngressFifoQueueAddress(CtrlIndex, FifoIdx) ( Eth_Ctrl_0_Ingress_Queue_0 ) |
#define | Eth_GetIngressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx) ( Eth_Ctrl_0_Ingress_BufferState_0[(BufferIdx)] ) |
#define | Eth_SetIngressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx, Val) ( Eth_Ctrl_0_Ingress_BufferState_0[(BufferIdx)] = Val ) |
#define | Eth_GetEgressFifoCqIdx(CtrlIndex, FifoIdx) ( 0U ) |
#define | Eth_GetEgressFifoFqIdx(CtrlIndex, FifoIdx) ( 2U ) |
#define | Eth_GetIngressFifoCqIdx(CtrlIndex, FifoIdx) ( 1U ) |
#define | Eth_GetIngressFifoFqIdx(CtrlIndex, FifoIdx) ( 3U ) |
#define | Eth_GetTxChanId(CtrlIndex, ChIdx) ( 30U ) |
#define | Eth_GetTxChanTdCqRingIdx(CtrlIndex, ChIdx) ( 4U ) |
#define | Eth_GetTxChanDepth(CtrlIndex, ChIdx) ( 128U ) |
#define | Eth_GetRxChanId(CtrlIndex, ChIdx) ( 30U ) |
#define | Eth_GetRxChanTdCqRingIdx(CtrlIndex, ChIdx) ( 5U ) |
#define | Eth_GetRxChanFlowTotalNum(CtrlIndex, ChIdx) ( 1U ) |
#define | Eth_GetRxChanFlowStartNum(CtrlIndex, ChIdx) ( 60U ) |
#define | Eth_GetFlowId(CtrlIndex, FlowIdx) ( 60U ) |
#define | Eth_GetFlowCqRingIdx(CtrlIndex, FlowIdx) ( 1U ) |
#define | Eth_GetFlowFqRingIdx(CtrlIndex, FlowIdx) ( 3U ) |
#define | Eth_GetDynRingElemAddress(CtrlIndex, RingIdx) ( &Eth_RingDyn_Ctrl_0[(RingIdx)] ) |
#define | Eth_GetRingHwId(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].hwId ) |
#define | Eth_GetRingTotalElemNum(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].size ) |
#define | Eth_GetRingPriority(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].priority ) |
#define | Eth_GetRingMemBaseAddress(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].memPtr ) |
#define | Eth_GetRingEventRingIdx(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].ringIdx ) |
#define | Eth_GetRingEventGlobalEventNum(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].globalEvent ) |
#define | Eth_GetRingEventVirtBitNum(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].virtBitNum ) |
#define | Eth_GetRingEventEventIdx(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].eventIdx ) |
#define | Eth_GetRingEventSrcOffsetNum(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].srcOffset ) |
#define | Eth_GetEventCoreIntrNum(CtrlIndex, EvtIdx) ( Eth_EventCfg_Ctrl_0[(EvtIdx)].coreIntrNum ) |
#define | Eth_GetEventVirtIntrNum(CtrlIndex, EvtIdx) ( Eth_EventCfg_Ctrl_0[(EvtIdx)].virtIntrNum ) |
#define | Eth_GetEventIrIntrNum(CtrlIndex, EvtIdx) ( Eth_EventCfg_Ctrl_0[(EvtIdx)].IrIntrNum ) |
#define | Eth_GetTxEventCoreIntrNum(CtrlIndex) ( 80U ) |
#define | Eth_GetRxEventCoreIntrNum(CtrlIndex) ( 81U ) |
#define | Eth_GetHwTimerTotalNum(CtrlIndex) ( 0U ) |
#define | Eth_GetHwTimerId(CtrlIndex, Index) ( 0xFFU ) |
#define | Eth_GetHwTimerCounter(CtrlIndex, Index) ( 0xFFU ) |
#define | Eth_GetHwTimerIntervalMs(CtrlIndex, Index) ( 0xFFFFFFFFU ) |
#define | Eth_GetHwTimerBaseAddr(CtrlIndex, Index) ( 0xFFFFFFFFU ) |
#define | Eth_GetHwTimerDynRunningState(CtrlIndex, Index) ( FALSE ) |
#define | Eth_SetHwTimerDynRunningState(CtrlIndex, Index, Val) ( (void)(CtrlIndex) ) |
#define | Eth_GetRxIrqPacingEnable(CtrlIndex) ( FALSE ) |
#define | Eth_GetTxIrqPacingEnable(CtrlIndex) ( FALSE ) |
#define | Eth_GetRxHwTimerIdx(CtrlIndex) ( 255U ) |
#define | Eth_GetTxHwTimerIdx(CtrlIndex) ( 255U ) |
#define | Eth_GetIrqPacingEnable(CtrlIndex) ( Eth_GetTxIrqPacingEnable(CtrlIndex) || Eth_GetRxIrqPacingEnable(CtrlIndex) ) |
#define ETH_SID_INIT ((uint8) 0x01U) |
Eth_Init() API Service ID.
#define ETH_SID_SET_CONTROLLER_MODE ((uint8) 0x03U) |
Eth_SetControllerMode() API Service ID.
#define ETH_SID_GET_CONTROLLER_MODE ((uint8) 0x04U) |
Eth_GetControllerMode() API Service ID.
#define ETH_SID_WRITE_MII ((uint8) 0x05U) |
Eth_WriteMii() API Service ID.
#define ETH_SID_READ_MII ((uint8) 0x06U) |
Eth_ReadMii() API Service ID.
#define ETH_SID_GET_COUNTER_STATE ((uint8) 0x07U) |
Eth_GetCounterState() API Service ID.
#define ETH_SID_GET_PHYS_ADDR ((uint8) 0x08U) |
Eth_GetPhysAddr() API Service ID.
#define ETH_SID_PROVIDE_TX_BUFFER ((uint8) 0x09U) |
Eth_ProvideTxBuffer() API Service ID.
#define ETH_SID_MAIN_FUNCTION ((uint8) 0x0AU) |
Eth_MainFunction() API Service ID.
#define ETH_SID_TRANSMIT ((uint8) 0x0BU) |
Eth_Transmit() API Service ID.
#define ETH_SID_RECEIVE ((uint8) 0x0CU) |
Eth_Receive() API Service ID.
#define ETH_SID_TX_CONFIRMATION ((uint8) 0x0EU) |
Eth_TxConfirmation() API Service ID.
#define ETH_SID_GET_VERSION_INFO ((uint8) 0x0FU) |
Eth_GetVersionInfo() API Service ID.
#define ETH_SID_RX_IRQ_HDLR ((uint8) 0x10U) |
Eth_RxIrqHdlr_<CtrlIdx>() API Service ID.
#define ETH_SID_TX_IRQ_HDLR ((uint8) 0x11U) |
Eth_TxIrqHdlr_<CtrlIdx>() API Service ID.
#define ETH_SID_UPDATE_PHYS_ADDR_FILTER ((uint8) 0x12U) |
Eth_UpdatePhysAddrFilter() API Service ID.
#define ETH_SID_SET_PHYS_ADDR ((uint8) 0x13U) |
Eth_SetPhysAddr() API Service ID.
#define ETH_SID_GET_COUNTER_VALUES ((uint8) 0x14U) |
Eth_GetCounterValues() API Service ID.
#define ETH_SID_GET_RX_STATS ((uint8) 0x15U) |
Eth_GetRxStats() API Service ID.
#define ETH_SID_GET_TX_STATS ((uint8) 0x1CU) |
Eth_GetTxStats() API Service ID.
#define ETH_SID_GET_TXERROR_COUNTERVALUES ((uint8) 0x1DU) |
Eth_GetTxErrorCounterValues() API Service ID.
#define ETH_SID_GET_CURRENT_TIME ((uint8) 0x16U) |
Eth_GetCurrentTime() API Service ID.
#define ETH_SID_ENABLE_EGRESS_TIMESTAMP ((uint8) 0x17U) |
Eth_EnableEgressTimeStamp() API Service ID.
#define ETH_SID_GET_EGRESS_TIMESTAMP ((uint8) 0x18U) |
Eth_GetEgressTimeStamp() API Service ID.
#define ETH_SID_GET_INGRESS_TIMESTAMP ((uint8) 0x19U) |
Eth_GetIngressTimeStamp() API Service ID.
#define ETH_SID_SET_CORRECTION_TIME ((uint8) 0x1AU) |
Eth_SetCorrectionTime() API Service ID.
#define ETH_SID_SET_GLOBAL_TIME ((uint8) 0x1BU) |
Eth_SetGlobalTime() API Service ID.
#define ETH_SID_DISPATCH_VIRTMAC_INIT ((uint8) 0x1CU) |
Eth_DispatchVirtmacInit() API Service ID.
#define ETH_SID_DISPATCH_VIRTMAC_DEINIT ((uint8) 0x1DU) |
Eth_DispatchVirtmacDeinit() API Service ID.
#define ETH_SID_NOTIFY_VIRTMAC_MSGRECV ((uint8) 0x1EU) |
Eth_NotifyVirtmacMsgRecv() API Service ID.
#define ETH_SID_DISPATCH_VIRTMAC_SUBSCRIBE_ALLTRAFFIC ((uint8) 0x1FU) |
Eth_DispatchVirtmacSubscribeAllTraffic() API Service ID.
#define ETH_SID_DISPATCH_VIRTMAC_UNSUBSCRIBE_ALLTRAFFIC ((uint8) 0x20U) |
Eth_DispatchVirtmacUnsubscribeAllTraffic() API Service ID.
#define ETH_SID_DISPATCH_VIRTMAC_SUBSCRIBE_DSTMAC ((uint8) 0x21U) |
Eth_DispatchVirtmacSubscribeDstMac() API Service ID.
#define ETH_SID_DISPATCH_VIRTMAC_UNSUBSCRIBE_DSTMAC ((uint8) 0x22U) |
Eth_DispatchVirtmacUnsubscribeDstMac() API Service ID.
#define ETH_SID_DISPATCH_VIRTMAC_IPV4_MACADDR_ASSOCIATE ((uint8) 0x23U) |
Eth_DispatchVirtmacIPv4MacAddrAssociate() API Service ID.
#define ETH_SID_DISPATCH_VIRTMAC_IPV4_MACADDR_DISASSOCIATE ((uint8) 0x24U) |
Eth_DispatchVirtmacIPv4MacAddrDisassociate() API Service ID.
#define ETH_SID_DISPATCH_VIRTMAC_ADD_UNICAST_MACADDR ((uint8) 0x25U) |
Eth_DispatchVirtmacAddUnicastMacAddr() API Service ID.
#define ETH_SID_DISPATCH_VIRTMAC_ADD_MCAST_MACADDR ((uint8) 0x26U) |
Eth_DispatchVirtmacAddMcastMacAddr() API Service ID.
#define ETH_SID_DISPATCH_VIRTMAC_DEL_MACADDR ((uint8) 0x27U) |
Eth_DispatchVirtmacDelMacAddr() API Service ID.
#define ETH_SID_DISPATCH_VIRTMAC_ADD_VLAN ((uint8) 0x28U) |
Eth_DispatchVirtmacAddVlan() API Service ID.
#define ETH_SID_DISPATCH_VIRTMAC_DEL_VLAN ((uint8) 0x29U) |
Eth_DispatchVirtmacDelVlan() API Service ID.
#define ETH_SID_SEND_CUSTOM_NOTIFY ((uint8) 0x2AU) |
Eth_SendCustomNotify() API Service ID.
#define ETH_SID_VIRTMAC_RPC_INIT ((uint8) 0x2BU) |
Eth_VirtMacRpcInit() API Service ID.
#define ETH_SID_SET_BANDWIDTH_LIMIT ((uint8) 0x2CU) |
Eth_SetBandwidthLimit() API Service ID.
#define ETH_SID_GET_BANDWIDTH_LIMIT ((uint8) 0x2DU) |
Eth_GetBandwidthLimit() API Service ID.
#define ETH_VERSION_INFO_API (STD_ON) |
Enable/disable SPI get version info API.
#define ETH_GLOBALTIMESUPPORT_API (STD_ON) |
Enable/disable Eth time sync related API.
#define ETH_DEV_ERROR_DETECT (STD_ON) |
Enable/Disable Development Error Detection.
#define ETH_GET_COUNTER_VALUES_API (STD_ON) |
Enable/disable Eth get counter values API.
#define ETH_GET_RX_STATS_API (STD_ON) |
Enable/disable Eth get RX stats count API.
#define ETH_GET_TX_STATS_API (STD_ON) |
Enable/disable Eth get TX stats count API.
#define ETH_GET_TX_ERROR_COUNTERSVALUES_API (STD_ON) |
Enable/disable Eth get TX error stats count API.
#define ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_ICMP (STD_OFF) |
Enable/disable Hardware Offloading for ICMP checksums.
#define ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_IPV4 (STD_OFF) |
Enable/disable Hardware offloading for IPv4 Header checksums.
#define ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_TCP (STD_OFF) |
Enable/disable Hardware offloading for TCP checksums.
#define ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_UDP (STD_OFF) |
Enable/disable Hardware offloading for UDP checksums.
#define ETH_ENABLE_MII_API (STD_ON) |
Enable/disable Eth MII related API.
#define ETH_UPDATE_PHYS_ADDR_FILTER_API (STD_ON) |
Enable/disable optional API Eth_UpdatePhysAddrFilter.
#define ETH_VIRTUALMAC_NOTIFYMSGRECEIVED_API (STD_OFF) |
Enable/disable optional API Eth_NotifyVirtmacMsgReceived.
#define ETH_VIRTUALMAC_SUBSCRIBEALLTRAFFIC_API (STD_OFF) |
Enable/disable optional API Eth_DispatchVirtmacSubscribeAllTraffic.
#define ETH_VIRTUALMAC_UNSUBSCRIBEALLTRAFFIC_API (STD_OFF) |
Enable/disable optional API Eth_DispatchVirtmacUnsubscribeAllTraffic.
#define ETH_VIRTUALMAC_SUBSCRIBEDSTMAC_API (STD_OFF) |
Enable/disable optional API Eth_DispatchVirtmacSubscribeDstMac.
#define ETH_VIRTUALMAC_UNSUBSCRIBEDSTMAC_API (STD_OFF) |
Enable/disable optional API Eth_DispatchVirtmacUnsubscribeDstMac.
#define ETH_VIRTUALMAC_ASSOCIATEIPV4MACADDR_API (STD_OFF) |
Enable/disable optional API Eth_DispatchVirtmacAssociateIPv4Macaddr.
#define ETH_VIRTUALMAC_DISASSOCIATEIPV4MACADDR_API (STD_OFF) |
Enable/disable optional API Eth_DispatchVirtmacDisassociateIPv4Macaddr.
#define ETH_VIRTUALMAC_ADD_UNICAST_MACADDR_API (STD_OFF) |
Enable/disable optional API Eth_DispatchVirtmacAddUnicastAddr.
#define ETH_VIRTUALMAC_ADD_MCAST_MACADDR_API (STD_OFF) |
Enable/disable optional API Eth_DispatchVirtmacAddMcastAddr.
#define ETH_VIRTUALMAC_DEL_MACADDR_API (STD_OFF) |
Enable/disable optional API Eth_DispatchVirtmacDelAddr.
#define ETH_VIRTUALMAC_SEND_CUSTOM_NOTIFY_API (STD_OFF) |
Enable/disable optional API Eth_SendCustomNotify.
#define ETH_VIRTUALMAC_ADD_VLAN_API (STD_OFF) |
Enable/disable optional API Eth_DispatchVirtmacAddVlan.
#define ETH_VIRTUALMAC_DEL_VLAN_API (STD_OFF) |
Enable/disable optional API Eth_DispatchVirtmacDelVlan.
#define ETH_ISR_TYPE (ETH_ISR_CAT2) |
ISR type.
#define ETH_OS_COUNTER_ID ((CounterType)OsCounter_0) |
Counter ID for counter used to count wait ticks.
#define ETH_OS_COUNTER_FREQ (1000000000U) |
Frequency in Hz of the counter specified in ETH_OS_COUNTER_ID.
#define ETH_VIRTUALMAC_SUPPORT (STD_OFF) |
Enable/disable Virtual MAC support.
#define ETH_VIRTUALMAC_FWINFO_TIMEOUT (0U) |
Timeout value for Firmware Attach msg received from server.
#define EthConf_EthCtrlConfig_EthConfig_0 (0U) |
Eth controller ID Configured controller ID(s)
Controller config
#define ETH_PRE_COMPILE_VARIANT (STD_ON) |
Eth configuration variant.
#define ETH_LINK_TIME_VARIANT (STD_OFF) |
#define ETH_POST_BUILD_VARIANT (STD_OFF) |
#define ETH_CTRL_ID_MAX (1u) |
Eth max controller ID.
#define ETH_DMA_IR_SUPPORT (STD_ON) |
Eth DMA feature flag support.
#define ETH_DMA_CQ_RING_SUPPORT (STD_ON) |
#define ETH_DMA_TEARDOWN_SUPPORT (STD_ON) |
#define UDMA_DEVICE_ID_RING (235U) |
Eth DMA devices ID.
#define UDMA_DEVICE_ID_UDMA (236U) |
#define UDMA_DEVICE_ID_PSIL (232U) |
#define UDMA_DEVICE_ID_IA (233U) |
#define UDMA_DEVICE_ID_IR (237U) |
#define UDMA_DEVICE_ID_CORE (250U) |
#define UDMA_TX_CHANNEL_PEER_OFFSET (0xf000U) |
Eth DMA peer and thread offset.
#define UDMA_RX_CHANNEL_PEER_OFFSET (0x7000U) |
#define UDMA_SOURCE_THREAD_OFFSET (0x6000U) |
#define UDMA_DEST_THREAD_OFFSET (0xe000U) |
#define ETH_DMA_TX_BASE_REG (0x2aa00000U) |
Eth DMA base register address.
#define ETH_DMA_RX_BASE_REG (0x2a800000U) |
#define ETH_DMA_RINGRT_BASE (0x2b800000U) |
#define ETH_DMA_RINGCFG_BASE (0x28440000U) |
#define ETH_DMA_INTAGGR_INTR_BASE (0x2a700000U) |
#define ETH_DMA_TXCRT_CHAN_CTL | ( | CHAN | ) | (0x00000000U + ((CHAN) * 0x1000U)) |
Eth DMA macro to calculate register address for DMA register address.
#define ETH_DMA_TXCRT_CHAN_PEER8 | ( | CHAN | ) | (0x00000220U + ((CHAN) * 0x1000U)) |
#define ETH_DMA_RXCRT_CHAN_CTL | ( | CHAN | ) | (0x00000000U + ((CHAN) * 0x1000U)) |
#define ETH_DMA_RXCRT_CHAN_PEER8 | ( | CHAN | ) | (0x00000220U + ((CHAN) * 0x1000U)) |
#define ETH_DMA_RINGRT_RING_FDB | ( | RING | ) | (0x00000010U + ((RING) * 0x1000U)) |
#define ETH_DMA_RINGRT_RING_FOCC | ( | RING | ) | (0x00000018U + ((RING) * 0x1000U)) |
#define ETH_DMA_RINGRT_RING_RDB | ( | RING | ) | (0x00000010U + ((RING) * 0x1000U)) |
#define ETH_DMA_RINGRT_RING_ROCC | ( | RING | ) | (0x00000018U + ((RING) * 0x1000U)) |
#define ETH_DMA_RINGCFG_RING_SIZE | ( | RING | ) | (0x00000048U + ((RING) * 0x100U)) |
#define ETH_DMA_INTAGGR_INTR_VINT_ENABLE_SET | ( | VINT | ) | (ETH_DMA_INTAGGR_INTR_BASE + 0x00000000U + ((VINT) * 0x1000U)) |
#define ETH_DMA_INTAGGR_INTR_VINT_ENABLE_CLEAR | ( | VINT | ) | (ETH_DMA_INTAGGR_INTR_BASE + 0x00000008U + ((VINT) * 0x1000U)) |
#define ETH_DMA_INTAGGR_INTR_VINT_STATUS_SET | ( | VINT | ) | (ETH_DMA_INTAGGR_INTR_BASE + 0x00000010U + ((VINT) * 0x1000U)) |
#define ETH_DMA_INTAGGR_INTR_VINT_STATUS_CLEAR | ( | VINT | ) | (ETH_DMA_INTAGGR_INTR_BASE + 0x00000018U + ((VINT) * 0x1000U)) |
#define ETH_DMA_INTAGGR_INTR_VINT_STATUSM | ( | VINT | ) | (ETH_DMA_INTAGGR_INTR_BASE + 0x00000020U + ((VINT) * 0x1000U)) |
#define Eth_GetRingFDBReg | ( | RingNum | ) | (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_FDB((RingNum))) |
#define Eth_GetRingFOCCReg | ( | RingNum | ) | (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_FOCC((RingNum))) |
#define Eth_GetRingRDBReg | ( | RingNum | ) | (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_RDB((RingNum))) |
#define Eth_GetRingROCCReg | ( | RingNum | ) | (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_ROCC((RingNum))) |
#define Eth_GetRingSizeReg | ( | RingNum | ) | (ETH_DMA_RINGCFG_BASE + ETH_DMA_RINGCFG_RING_SIZE((RingNum))) |
#define Eth_GetTxChannelCtlRegAddress | ( | ChanId | ) | (ETH_DMA_TX_BASE_REG + ETH_DMA_TXCRT_CHAN_CTL((ChanId))) |
#define Eth_GetTxChannelPeer8RegAddress | ( | ChanId | ) | (ETH_DMA_TX_BASE_REG + ETH_DMA_TXCRT_CHAN_PEER8((ChanId))) |
#define Eth_GetRxChannelCtlRegAddress | ( | ChanId | ) | (ETH_DMA_RX_BASE_REG + ETH_DMA_RXCRT_CHAN_CTL((ChanId))) |
#define Eth_GetRxChannelPeer8RegAddress | ( | ChanId | ) | (ETH_DMA_RX_BASE_REG + ETH_DMA_RXCRT_CHAN_PEER8((ChanId))) |
#define UDMA_WAIT_TEARDOWN_COUNTER (10000u) |
Eth DMA max teardown timeout.
#define Eth_GetDem_E_HARDWARE_ERROR | ( | CtrlIndex | ) | ( ETH_DEM_NO_EVENT ) |
ETH DEM Error codes to report.
#define Eth_GetDem_E_LATECOLLISION | ( | CtrlIndex | ) | ( ETH_DEM_NO_EVENT ) |
#define Eth_GetDem_E_MULTIPLECOLLISION | ( | CtrlIndex | ) | ( ETH_DEM_NO_EVENT ) |
#define Eth_GetDem_E_SINGLECOLLISION | ( | CtrlIndex | ) | ( ETH_DEM_NO_EVENT ) |
#define Eth_GetDem_E_ALIGNMENT | ( | CtrlIndex | ) | ( ETH_DEM_NO_EVENT ) |
#define Eth_GetDem_E_OVERSIZEFRAME | ( | CtrlIndex | ) | ( ETH_DEM_NO_EVENT ) |
#define Eth_GetDem_E_UNDERSIZEFRAME | ( | CtrlIndex | ) | ( ETH_DEM_NO_EVENT ) |
#define Eth_GetDem_E_CRC | ( | CtrlIndex | ) | ( ETH_DEM_NO_EVENT ) |
#define Eth_GetDem_E_RX_FRAMES_LOST | ( | CtrlIndex | ) | ( ETH_DEM_NO_EVENT ) |
#define Eth_GetDem_E_ACCESS | ( | CtrlIndex | ) | ( ETH_DEM_NO_EVENT ) |
#define Eth_GetDem_E_TX_INTERNAL | ( | CtrlIndex | ) | ( ETH_DEM_NO_EVENT ) |
#define Eth_IsVirtualMacModeEnable | ( | CtrlIndex | ) | ( FALSE ) |
Eth function like macro to access controler configuration.
#define Eth_GetTxChannelThreadOffset | ( | CtrlIndex | ) | ( 0xf000U ) |
#define Eth_VirtMacGetEthFwRpcComChannelId | ( | CtrlIndex | ) | ( 0xFFFFU ) |
#define Eth_VirtMacGetEthPollRecvMsgInEthMain | ( | CtrlIndex | ) | ( FALSE ) |
#define Eth_VirtMacGetRpcCmdCompleteFuncPtr | ( | CtrlIndex | ) | ( (Eth_RpcCmdComplete)NULL_PTR ) |
#define Eth_VirtMacGetFwRegisterFuncPtr | ( | CtrlIndex | ) | ( (Eth_RpcFwRegistered)NULL_PTR ) |
#define Eth_GetTxEnableInterrupt | ( | CtrlIndex | ) | ( TRUE ) |
#define Eth_GetRxEnableInterrupt | ( | CtrlIndex | ) | ( TRUE ) |
#define Eth_GetEnetType | ( | CtrlIndex | ) | ( ETH_ENETTYPE_CPSW2G ) |
#define Eth_GetMacPortNum | ( | CtrlIndex | ) | ( ETH_PORT_MAC_PORT_1 ) |
#define Eth_GetMacAddressHigh | ( | CtrlIndex | ) | ( 0xaabbccddU ) |
#define Eth_GetMacAddressLow | ( | CtrlIndex | ) | ( 0xeeffU ) |
#define Eth_UseDefaultMacAddress | ( | CtrlIndex | ) | ( TRUE ) |
#define Eth_GetMiiConnectionType | ( | CtrlIndex | ) | ( ETH_MAC_CONN_TYPE_RGMII_FORCE_1000_FULL ) |
#define Eth_GetLoopBackMode | ( | CtrlIndex | ) | ( FALSE ) |
#define Eth_GetHardwareLoopTimeout | ( | CtrlIndex | ) | ( 32000U ) |
#define Eth_GetEnableCacheOps | ( | CtrlIndex | ) | ( TRUE ) |
#define Eth_GetCacheWritebackInvalidateFuncPtr | ( | CtrlIndex | ) | ( &EthApp_wbInvCache ) |
#define Eth_GetCacheWritebackFuncPtr | ( | CtrlIndex | ) | ( &EthApp_wbCache ) |
#define Eth_GetCacheInvalidateFuncPtr | ( | CtrlIndex | ) | ( &EthApp_invCache ) |
#define Eth_DescriptorGetCacheWritebackInvalidateFuncPtr | ( | CtrlIndex | ) | ( Eth_GetCacheWritebackInvalidateFuncPtr(CtrlIndex) ) |
#define Eth_DescriptorGetCacheWritebackFuncPtr | ( | CtrlIndex | ) | ( Eth_GetCacheWritebackFuncPtr(CtrlIndex) ) |
#define Eth_DescriptorGetCacheInvalidateFuncPtr | ( | CtrlIndex | ) | ( Eth_GetCacheInvalidateFuncPtr(CtrlIndex) ) |
#define Eth_RingGetCacheWritebackInvalidateFuncPtr | ( | CtrlIndex | ) | ( Eth_GetCacheWritebackInvalidateFuncPtr(CtrlIndex) ) |
#define Eth_RingGetCacheWritebackFuncPtr | ( | CtrlIndex | ) | ( Eth_GetCacheWritebackFuncPtr(CtrlIndex) ) |
#define Eth_RingGetCacheInvalidateFuncPtr | ( | CtrlIndex | ) | ( Eth_GetCacheInvalidateFuncPtr(CtrlIndex) ) |
#define Eth_Cpsw_GetPhyMacRegAddr | ( | ) | ( 0x40f00200U ) |
#define Eth_Cpsw_GetAleRegAddr | ( | ) | ( 0x4603e000U ) |
#define Eth_Cpsw_GetCptsRegAddr | ( | ) | ( 0x4603d000U ) |
#define Eth_Cpsw_GetMdioRegAddr | ( | ) | ( 0x46000f00U ) |
#define Eth_Cpsw_GetCtrlRegAddr | ( | ) | ( 0x46020000U ) |
#define Eth_Cpsw_GetCptsRefClockFreq | ( | ) | ( 1U ) |
#define Eth_Cpsw_GetCppiClockFreq | ( | ) | ( 333333333U ) |
#define Eth_Cpsw_GetMdioBusClockFreq | ( | CtrlIndex | ) | ( 2200000U ) |
#define Eth_Cpsw_GetMdioOpMode | ( | CtrlIndex | ) | ( ETH_MDIO_OPMODE_MANUAL ) |
#define Eth_GetRxMtuLength | ( | CtrlIndex | ) | ( 1522U ) |
#define Eth_GetTxChanStartNum | ( | CtrlIndex | ) | ( 30U ) |
#define Eth_GetRxChanStartNum | ( | CtrlIndex | ) | ( 30U ) |
#define Eth_GetEgressFifoTotalNum | ( | CtrlIndex | ) | ( 1U ) |
#define Eth_GetIngressFifoTotalNum | ( | CtrlIndex | ) | ( 1U ) |
#define Eth_GetRingTotalNum | ( | CtrlIndex | ) | ( 6U ) |
#define Eth_GetTxChanTotalNum | ( | CtrlIndex | ) | ( 1U ) |
#define Eth_GetRxChanTotalNum | ( | CtrlIndex | ) | ( 1U ) |
#define Eth_GetFlowTotalNumber | ( | CtrlIndex | ) | ( 1U ) |
#define Eth_GetEventTotalNum | ( | CtrlIndex | ) | ( 2U ) |
#define Eth_GetRingEventTotalNum | ( | CtrlIndex | ) | ( 2U ) |
#define Eth_GetEgressFifoPacketNum | ( | CtrlIndex, | |
FifoIdx | |||
) | ( 128U ) |
#define Eth_GetEgressFifoPacketSize | ( | CtrlIndex, | |
FifoIdx | |||
) | ( 1522U ) |
#define Eth_GetIngressFifoPacketNum | ( | CtrlIndex, | |
FifoIdx | |||
) | ( 128U ) |
#define Eth_GetIngressFifoPacketSize | ( | CtrlIndex, | |
FifoIdx | |||
) | ( 1522U ) |
#define Eth_GetEgressFifoDescAddress | ( | CtrlIndex, | |
FifoIdx, | |||
DescIdx | |||
) | (&Eth_Ctrl_0_Egress_Descriptor_0[(DescIdx)] ) |
#define Eth_GetEgressFifoDescUserInfoAddress | ( | CtrlIndex, | |
FifoIdx, | |||
DescIdx | |||
) | (&Eth_Ctrl_0_Egress_Descriptor_0[(DescIdx)].bufferInfo ) |
#define Eth_GetEgressFifoBufferDataAddress | ( | CtrlIndex, | |
FifoIdx, | |||
DescIdx | |||
) | (&Eth_Ctrl_0_Egress_BufferMem_0[(DescIdx) * 1536U] ) |
#define Eth_GetEgressFifoQueueAddress | ( | CtrlIndex, | |
FifoIdx | |||
) | ( Eth_Ctrl_0_Egress_Queue_0 ) |
#define Eth_GetEgressFifoBufferState | ( | CtrlIndex, | |
FifoIdx, | |||
BufferIdx | |||
) | ( Eth_Ctrl_0_Egress_BufferState_0[BufferIdx] ) |
#define Eth_SetEgressFifoBufferState | ( | CtrlIndex, | |
FifoIdx, | |||
BufferIdx, | |||
Val | |||
) | ( Eth_Ctrl_0_Egress_BufferState_0[BufferIdx] = Val ) |
#define Eth_GetIngressFifoDescAddress | ( | CtrlIndex, | |
FifoIdx, | |||
DescIdx | |||
) | (&Eth_Ctrl_0_Ingress_Descriptor_0[(DescIdx)] ) |
#define Eth_GetIngressFifoDescUserInfoAddress | ( | CtrlIndex, | |
FifoIdx, | |||
DescIdx | |||
) | (&Eth_Ctrl_0_Ingress_Descriptor_0[(DescIdx)].bufferInfo ) |
#define Eth_GetIngressFifoBufferDataAddress | ( | CtrlIndex, | |
FifoIdx, | |||
DescIdx | |||
) | (&Eth_Ctrl_0_Ingress_BufferMem_0[(DescIdx) * 1536U] ) |
#define Eth_GetIngressFifoQueueAddress | ( | CtrlIndex, | |
FifoIdx | |||
) | ( Eth_Ctrl_0_Ingress_Queue_0 ) |
#define Eth_GetIngressFifoBufferState | ( | CtrlIndex, | |
FifoIdx, | |||
BufferIdx | |||
) | ( Eth_Ctrl_0_Ingress_BufferState_0[(BufferIdx)] ) |
#define Eth_SetIngressFifoBufferState | ( | CtrlIndex, | |
FifoIdx, | |||
BufferIdx, | |||
Val | |||
) | ( Eth_Ctrl_0_Ingress_BufferState_0[(BufferIdx)] = Val ) |
#define Eth_GetEgressFifoCqIdx | ( | CtrlIndex, | |
FifoIdx | |||
) | ( 0U ) |
#define Eth_GetEgressFifoFqIdx | ( | CtrlIndex, | |
FifoIdx | |||
) | ( 2U ) |
#define Eth_GetIngressFifoCqIdx | ( | CtrlIndex, | |
FifoIdx | |||
) | ( 1U ) |
#define Eth_GetIngressFifoFqIdx | ( | CtrlIndex, | |
FifoIdx | |||
) | ( 3U ) |
#define Eth_GetTxChanId | ( | CtrlIndex, | |
ChIdx | |||
) | ( 30U ) |
#define Eth_GetTxChanTdCqRingIdx | ( | CtrlIndex, | |
ChIdx | |||
) | ( 4U ) |
#define Eth_GetTxChanDepth | ( | CtrlIndex, | |
ChIdx | |||
) | ( 128U ) |
#define Eth_GetRxChanId | ( | CtrlIndex, | |
ChIdx | |||
) | ( 30U ) |
#define Eth_GetRxChanTdCqRingIdx | ( | CtrlIndex, | |
ChIdx | |||
) | ( 5U ) |
#define Eth_GetRxChanFlowTotalNum | ( | CtrlIndex, | |
ChIdx | |||
) | ( 1U ) |
#define Eth_GetRxChanFlowStartNum | ( | CtrlIndex, | |
ChIdx | |||
) | ( 60U ) |
#define Eth_GetFlowId | ( | CtrlIndex, | |
FlowIdx | |||
) | ( 60U ) |
#define Eth_GetFlowCqRingIdx | ( | CtrlIndex, | |
FlowIdx | |||
) | ( 1U ) |
#define Eth_GetFlowFqRingIdx | ( | CtrlIndex, | |
FlowIdx | |||
) | ( 3U ) |
#define Eth_GetDynRingElemAddress | ( | CtrlIndex, | |
RingIdx | |||
) | ( &Eth_RingDyn_Ctrl_0[(RingIdx)] ) |
#define Eth_GetRingHwId | ( | CtrlIndex, | |
RingIdx | |||
) | ( Eth_Udma_RingCfg_0[(RingIdx)].hwId ) |
#define Eth_GetRingTotalElemNum | ( | CtrlIndex, | |
RingIdx | |||
) | ( Eth_Udma_RingCfg_0[(RingIdx)].size ) |
#define Eth_GetRingPriority | ( | CtrlIndex, | |
RingIdx | |||
) | ( Eth_Udma_RingCfg_0[(RingIdx)].priority ) |
#define Eth_GetRingMemBaseAddress | ( | CtrlIndex, | |
RingIdx | |||
) | ( Eth_Udma_RingCfg_0[(RingIdx)].memPtr ) |
#define Eth_GetRingEventRingIdx | ( | CtrlIndex, | |
RingEvtIdx | |||
) | ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].ringIdx ) |
#define Eth_GetRingEventGlobalEventNum | ( | CtrlIndex, | |
RingEvtIdx | |||
) | ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].globalEvent ) |
#define Eth_GetRingEventVirtBitNum | ( | CtrlIndex, | |
RingEvtIdx | |||
) | ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].virtBitNum ) |
#define Eth_GetRingEventEventIdx | ( | CtrlIndex, | |
RingEvtIdx | |||
) | ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].eventIdx ) |
#define Eth_GetRingEventSrcOffsetNum | ( | CtrlIndex, | |
RingEvtIdx | |||
) | ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].srcOffset ) |
#define Eth_GetEventCoreIntrNum | ( | CtrlIndex, | |
EvtIdx | |||
) | ( Eth_EventCfg_Ctrl_0[(EvtIdx)].coreIntrNum ) |
#define Eth_GetEventVirtIntrNum | ( | CtrlIndex, | |
EvtIdx | |||
) | ( Eth_EventCfg_Ctrl_0[(EvtIdx)].virtIntrNum ) |
#define Eth_GetEventIrIntrNum | ( | CtrlIndex, | |
EvtIdx | |||
) | ( Eth_EventCfg_Ctrl_0[(EvtIdx)].IrIntrNum ) |
#define Eth_GetTxEventCoreIntrNum | ( | CtrlIndex | ) | ( 80U ) |
#define Eth_GetRxEventCoreIntrNum | ( | CtrlIndex | ) | ( 81U ) |
#define Eth_GetHwTimerTotalNum | ( | CtrlIndex | ) | ( 0U ) |
#define Eth_GetHwTimerId | ( | CtrlIndex, | |
Index | |||
) | ( 0xFFU ) |
#define Eth_GetHwTimerCounter | ( | CtrlIndex, | |
Index | |||
) | ( 0xFFU ) |
#define Eth_GetHwTimerIntervalMs | ( | CtrlIndex, | |
Index | |||
) | ( 0xFFFFFFFFU ) |
#define Eth_GetHwTimerBaseAddr | ( | CtrlIndex, | |
Index | |||
) | ( 0xFFFFFFFFU ) |
#define Eth_GetHwTimerDynRunningState | ( | CtrlIndex, | |
Index | |||
) | ( FALSE ) |
#define Eth_SetHwTimerDynRunningState | ( | CtrlIndex, | |
Index, | |||
Val | |||
) | ( (void)(CtrlIndex) ) |
#define Eth_GetRxIrqPacingEnable | ( | CtrlIndex | ) | ( FALSE ) |
#define Eth_GetTxIrqPacingEnable | ( | CtrlIndex | ) | ( FALSE ) |
#define Eth_GetRxHwTimerIdx | ( | CtrlIndex | ) | ( 255U ) |
#define Eth_GetTxHwTimerIdx | ( | CtrlIndex | ) | ( 255U ) |
#define Eth_GetIrqPacingEnable | ( | CtrlIndex | ) | ( Eth_GetTxIrqPacingEnable(CtrlIndex) || Eth_GetRxIrqPacingEnable(CtrlIndex) ) |
#define ETH_START_SEC_CONST_UNSPECIFIED |
#define ETH_STOP_SEC_CONST_UNSPECIFIED |
#define ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED_128 |
#define ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED_128 |
#define ETH_START_SEC_VAR_NO_INIT_8 |
#define ETH_STOP_SEC_VAR_NO_INIT_8 |
#define ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED |
#define ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED |
#define ETH_START_SEC_CODE |
#define ETH_STOP_SEC_CODE |
enum Eth_MdioOperModeType |
VAR | ( | uint8 | , |
ETH_VAR_NO_INIT_128 | |||
) |
VAR | ( | Eth_DescType | , |
ETH_VAR_NO_INIT_128 | |||
) |
VAR | ( | uint8 | , |
ETH_VAR_NO_INIT | |||
) |
VAR | ( | Eth_QueueType | , |
ETH_VAR_NO_INIT | |||
) |
VAR | ( | Eth_Udma_RingDynType | , |
ETH_VAR_NO_INIT | |||
) |
void EthApp_wbInvCache | ( | uint8 * | buf, |
uint16 | len | ||
) |
Function to write-back and invalidate cache.
void EthApp_wbCache | ( | uint8 * | buf, |
uint16 | len | ||
) |
Function to write-back cache.
void EthApp_invCache | ( | uint8 * | buf, |
uint16 | len | ||
) |
Function to invalidate cache.
const Eth_Udma_RingCfgType Eth_Udma_RingCfg_0[6U] |
const Eth_Udma_EventCfgType Eth_EventCfg_Ctrl_0[2U] |
const Eth_Udma_RingEventCfgType Eth_RingEventCfg_Ctrl_0[2U] |