SDL API Guide for J721E
sdl_ecc.h File Reference

Introduction

Header file contains enumerations, structure definitions and function

declarations for SDL ECC interface.

Go to the source code of this file.

Data Structures

struct  SDL_ECC_InitConfig_t
 This structure defines the elements of ECC Init configuration. More...
 
struct  SDL_ECC_InjectErrorConfig_t
 This structure defines the inject error configuration. More...
 
struct  SDL_ECC_ErrorInfo_t
 This structure defines the error status information. More...
 

Macros

#define SDL_ECC_MEMTYPE_MCU_R5F0_CORE   (0u)
 
#define SDL_ECC_MEMTYPE_MCU_R5F1_CORE   (1u)
 
#define SDL_ECC_MEMTYPE_MCU_ADC0   (2u)
 
#define SDL_ECC_MEMTYPE_MCU_ADC1   (3u)
 
#define SDL_ECC_MEMTYPE_MCU_CPSW0   (4u)
 
#define SDL_ECC_MEMTYPE_MCU_FSS0_HPB0   (5u)
 
#define SDL_ECC_MEMTYPE_MCU_FSS0_OSPI0   (6u)
 
#define SDL_ECC_MEMTYPE_MCU_FSS0_OSPI1   (7u)
 
#define SDL_ECC_MEMTYPE_MCU_MCAN0   (8u)
 
#define SDL_ECC_MEMTYPE_MCU_MCAN1   (9u)
 
#define SDL_ECC_MEMTYPE_MCU_MSRAM0   (10u)
 
#define SDL_ECC_MEMTYPE_MCU_NAVSS0   (11u)
 
#define SDL_ECC_MEMTYPE_MCU_PSRAM0   (12u)
 
#define SDL_ECC_MEMTYPE_MCU_CBASS_ECC_AGGR0   (13u)
 
#define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR   (14u)
 
#define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR   (15u)
 
#define SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR   (16u)
 
#define SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR   (17u)
 
#define SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR   (18u)
 
#define SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR   (19u)
 
#define SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR   (20u)
 
#define SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR   (21u)
 
#define SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR   (22u)
 
#define SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR   (23u)
 
#define SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR   (24u)
 
#define SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR   (25u)
 
#define SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR   (26u)
 
#define SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR   (27u)
 
#define SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR   (28u)
 
#define SDL_PCIE0_ECC_AGGR_CORE_AXI_0   (29u)
 
#define SDL_PCIE0_ECC_AGGR_CORE_0   (30u)
 
#define SDL_PCIE1_ECC_AGGR_CORE_AXI_0   (31u)
 
#define SDL_PCIE1_ECC_AGGR_CORE_0   (32u)
 
#define SDL_PCIE2_ECC_AGGR_CORE_AXI_0   (33u)
 
#define SDL_PCIE2_ECC_AGGR_CORE_0   (34u)
 
#define SDL_PCIE3_ECC_AGGR_CORE_AXI_0   (35u)
 
#define SDL_PCIE3_ECC_AGGR_CORE_0   (36u)
 
#define SDL_I3C0_I3C_S_ECC_AGGR   (37u)
 
#define SDL_I3C0_I3C_P_ECC_AGGR   (38u)
 
#define SDL_MCU_I3C0_I3C_P_ECC_AGGR   (39u)
 
#define SDL_MCU_I3C0_I3C_S_ECC_AGGR   (40u)
 
#define SDL_MCU_I3C1_I3C_P_ECC_AGGR   (41u)
 
#define SDL_MCU_I3C1_I3C_S_ECC_AGGR   (42u)
 
#define SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR   (43u)
 
#define SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR   (44u)
 
#define SDL_CBASS_ECC_AGGR0   (45u)
 
#define SDL_MAIN_RC_ECC_AGGR0   (46u)
 
#define SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR   (47u)
 
#define SDL_DMPAC0_ECC_AGGR   (48u)
 
#define SDL_MAIN_HC_ECC_AGGR0   (49u)
 
#define SDL_VPAC0_ECC_AGGR   (50u)
 
#define SDL_VPAC0_VISS_ECC_AGGR   (51u)
 
#define SDL_VPAC0_LDC_ECC_AGGR   (52u)
 
#define SDL_R5FSS0_CORE0_ECC_AGGR   (53u)
 
#define SDL_R5FSS1_CORE0_ECC_AGGR   (54u)
 
#define SDL_R5FSS0_CORE1_ECC_AGGR   (55u)
 
#define SDL_R5FSS1_CORE1_ECC_AGGR   (56u)
 
#define SDL_NAVSS_VIRTSS_ECC_AGGR0   (57u)
 
#define SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR   (58u)
 
#define SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR   (59u)
 
#define SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR   (60u)
 
#define SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR   (61u)
 
#define SDL_MAIN_AC_ECC_AGGR0   (62u)
 
#define SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR   (63u)
 
#define SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM   (64u)
 
#define SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM   (65u)
 
#define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM   (66u)
 
#define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM   (67u)
 
#define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM   (68u)
 
#define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM   (69u)
 
#define SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE   (70u)
 
#define SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY   (71u)
 
#define SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC   (72u)
 
#define SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR   (73u)
 
#define SDL_CSI_RX_IF0_ECC_AGGR_0   (74u)
 
#define SDL_CSI_RX_IF1_ECC_AGGR_0   (75u)
 
#define SDL_NAVSS0_MODSS_ECC_AGGR0   (76u)
 
#define SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR   (77u)
 
#define SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR   (78u)
 
#define SDL_NAVSS0_VIRTSS_ECC_AGGR0   (79u)
 
#define SDL_NAVSS0_NBSS_ECC_AGGR0   (80u)
 
#define SDL_IDOM1_ECC_AGGR0   (81u)
 
#define SDL_IDOM1_ECC_AGGR1   (82u)
 
#define SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR   (83u)
 
#define SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR   (84u)
 
#define SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR   (85u)
 
#define SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR   (86u)
 
#define SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE   (87u)
 
#define SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR   (88u)
 
#define SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS   (89u)
 
#define SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0   (90u)
 
#define SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR   (91u)
 
#define SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR   (92u)
 
#define SDL_NAVSS0_UDMASS_ECC_AGGR0   (93u)
 
#define SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR0   (94u)
 
#define SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR1   (95u)
 
#define SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR2   (96u)
 
#define SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR   (97u)
 
#define SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR   (98u)
 
#define SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR   (99u)
 
#define SDL_COMPUTE_CLUSTER0_DDR32SSC_EW_BRCTL_SC_ECC_AGGR_VBUS   (100u)
 
#define SDL_COMPUTE_CLUSTER0_DDR32SSC_EW_BRCTL_SC_ECC_AGGR_CTL   (101u)
 
#define SDL_COMPUTE_CLUSTER0_DDR32SSC_EW_BRCTL_SC_ECC_AGGR_CFG   (102u)
 
#define SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR   (103u)
 
#define SDL_ECC_MEMTYPE_MAX   (SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR + 1U)
 
#define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK0_VECTOR_ID   (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID)
 Select memory subtype ATCM0 BANK0. More...
 
#define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK1_VECTOR_ID   (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID)
 Select memory subtype ATCM0 BANK1. More...
 
#define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK0_VECTOR_ID   (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID)
 Select memory subtype B0TCM0 BANK0. More...
 
#define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK1_VECTOR_ID   (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID)
 Select memory subtype B0TCM0 BANK1. More...
 
#define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK0_VECTOR_ID   (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID)
 Select memory subtype B1TCM0 BANK0. More...
 
#define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK1_VECTOR_ID   (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID)
 Select memory subtype B1TCM0 BANK1. More...
 
#define SDL_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID   (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID)
 Select memory subtype VIM RAM. More...
 

Typedefs

typedef uint32_t SDL_ECC_MemType
 This enumerator indicate ECC memory type. More...
 
typedef uint32_t SDL_ECC_MemSubType
 This enumerator indicate ECC memory Sub Type. More...
 
typedef void(* SDL_ECC_ErrorCallback_t) (uint32_t errorSrc, uint32_t address)
 
typedef void(* SDL_ECC_VIMDEDVector_t) (void)
 

Enumerations

enum  SDL_ECC_AggregatorType { SDL_ECC_AGGR_TYPE_INJECT_ONLY = 1, SDL_ECC_AGGR_TYPE_FULL_FUNCTION = 2 }
 This enumerator defines the different ECC aggregator types. More...
 
enum  SDL_ECC_InjectErrorType {
  SDL_INJECT_ECC_NO_ERROR = 0, SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE = 1, SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE = 2, SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_ONCE = 3,
  SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_ONCE = 4, SDL_INJECT_ECC_ERROR_FORCING_1BIT_REPEAT = 5, SDL_INJECT_ECC_ERROR_FORCING_2BIT_REPEAT = 6, SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_REPEAT = 7,
  SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_REPEAT = 8
}
 ECC Inject error types. More...
 
enum  SDL_ECC_RamIdType { SDL_ECC_RAM_ID_TYPE_WRAPPER = 0, SDL_ECC_RAM_ID_TYPE_INTERCONNECT = 1 }
 This enumerator defines the different ECC RAM ID types. More...
 

Functions

int32_t SDL_ECC_initEsm (const SDL_ESM_Inst esmInstType)
 Initializes an module for usage with ECC module. More...
 
int32_t SDL_ECC_init (SDL_ECC_MemType eccMemType, const SDL_ECC_InitConfig_t *pECCInitConfig)
 Initializes ECC module for ECC detection. More...
 
int32_t SDL_ECC_initMemory (SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType)
 Initializes Memory to be ready for ECC error detection. Assumes ECC is already enabled. More...
 
int32_t SDL_ECC_selfTest (SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType, SDL_ECC_InjectErrorType errorType, const SDL_ECC_InjectErrorConfig_t *pECCErrorConfig, uint32_t selfTestTimeOut)
 Runs self test by injecting and error and monitor response Assumes ECC is already enabled. More...
 
int32_t SDL_ECC_injectError (SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType, SDL_ECC_InjectErrorType errorType, const SDL_ECC_InjectErrorConfig_t *pECCErrorConfig)
 Injects ECC error at specified location Assumes ECC is already enabled. More...
 
int32_t SDL_ECC_getStaticRegisters (SDL_ECC_MemType eccMemType, SDL_ECC_staticRegs *pStaticRegs)
 Gets the static registers for the specified ECC instance. More...
 
int32_t SDL_ECC_getErrorInfo (SDL_ECC_MemType eccMemType, SDL_Ecc_AggrIntrSrc intrSrc, SDL_ECC_ErrorInfo_t *pErrorInfo)
 Retrieves the ECC error information for the specified memtype and interrupt source. More...
 
int32_t SDL_ECC_ackIntr (SDL_ECC_MemType eccMemType, SDL_Ecc_AggrIntrSrc intrSrc)
 Acknowledge the ECC interrupt. More...
 
int32_t SDL_ECC_getESMErrorInfo (SDL_ESM_Inst instance, uint32_t intSrc, SDL_ECC_MemType *eccMemType, SDL_Ecc_AggrIntrSrc *intrSrcType)
 Retrieves the ECC error information for the specified ESM error. If it isn't an ECC error or the ECC error is not supported an error is returned. More...
 
int32_t SDL_ECC_clearNIntrPending (SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType, SDL_Ecc_AggrIntrSrc intrSrc, SDL_Ecc_AggrEDCErrorSubType subType, uint32_t numEvents)
 Clears N pending interrupts for the specified memtype, subtype and interrupt source. More...
 
void SDL_ECC_registerVIMDEDHandler (SDL_ECC_VIMDEDVector_t VIMDEDHandler)
 Register Handler for VIM DED ECC error. More...
 
void SDL_ECC_applicationCallbackFunction (SDL_ECC_MemType eccMemType, uint32_t errorSrc, uint32_t address, uint32_t ramId, uint64_t bitErrorOffset, uint32_t bitErrorGroup)
 Application provided external callback function for ECC handling Called inside the reference functions when ECC errors occur. NOTE: This is application supplied and not part of the SDL If not supplied by application this will result in an linker error. More...