Introduction

Typedefs
typedef uint32_t	SDL_ECC_MemType
	This enumerator indicate ECC memory type. More...

typedef uint32_t	SDL_ECC_MemSubType
	This enumerator indicate ECC memory Sub Type. More...

typedef void(*	SDL_ECC_ErrorCallback_t) (uint32_t errorSrc, uint32_t address)

typedef void(*	SDL_ECC_VIMDEDVector_t) (void)

Macros
#define	SDL_ECC_MEMTYPE_MCU_R5F0_CORE (0u)

#define	SDL_ECC_MEMTYPE_MCU_R5F1_CORE (1u)

#define	SDL_ECC_MEMTYPE_MCU_ADC0 (2u)

#define	SDL_ECC_MEMTYPE_MCU_ADC1 (3u)

#define	SDL_ECC_MEMTYPE_MCU_CPSW0 (4u)

#define	SDL_ECC_MEMTYPE_MCU_FSS0_HPB0 (5u)

#define	SDL_ECC_MEMTYPE_MCU_FSS0_OSPI0 (6u)

#define	SDL_ECC_MEMTYPE_MCU_FSS0_OSPI1 (7u)

#define	SDL_ECC_MEMTYPE_MCU_MCAN0 (8u)

#define	SDL_ECC_MEMTYPE_MCU_MCAN1 (9u)

#define	SDL_ECC_MEMTYPE_MCU_MSRAM0 (10u)

#define	SDL_ECC_MEMTYPE_MCU_NAVSS0 (11u)

#define	SDL_ECC_MEMTYPE_MCU_PSRAM0 (12u)

#define	SDL_ECC_MEMTYPE_MCU_CBASS_ECC_AGGR0 (13u)

#define	SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR (14u)

#define	SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR (15u)

#define	SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR (16u)

#define	SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR (17u)

#define	SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR (18u)

#define	SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR (19u)

#define	SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR (20u)

#define	SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR (21u)

#define	SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR (22u)

#define	SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR (23u)

#define	SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR (24u)

#define	SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR (25u)

#define	SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR (26u)

#define	SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR (27u)

#define	SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR (28u)

#define	SDL_PCIE0_ECC_AGGR_CORE_AXI_0 (29u)

#define	SDL_PCIE0_ECC_AGGR_CORE_0 (30u)

#define	SDL_PCIE1_ECC_AGGR_CORE_AXI_0 (31u)

#define	SDL_PCIE1_ECC_AGGR_CORE_0 (32u)

#define	SDL_PCIE2_ECC_AGGR_CORE_AXI_0 (33u)

#define	SDL_PCIE2_ECC_AGGR_CORE_0 (34u)

#define	SDL_PCIE3_ECC_AGGR_CORE_AXI_0 (35u)

#define	SDL_PCIE3_ECC_AGGR_CORE_0 (36u)

#define	SDL_I3C0_I3C_S_ECC_AGGR (37u)

#define	SDL_I3C0_I3C_P_ECC_AGGR (38u)

#define	SDL_MCU_I3C0_I3C_P_ECC_AGGR (39u)

#define	SDL_MCU_I3C0_I3C_S_ECC_AGGR (40u)

#define	SDL_MCU_I3C1_I3C_P_ECC_AGGR (41u)

#define	SDL_MCU_I3C1_I3C_S_ECC_AGGR (42u)

#define	SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR (43u)

#define	SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR (44u)

#define	SDL_CBASS_ECC_AGGR0 (45u)

#define	SDL_MAIN_RC_ECC_AGGR0 (46u)

#define	SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR (47u)

#define	SDL_DMPAC0_ECC_AGGR (48u)

#define	SDL_MAIN_HC_ECC_AGGR0 (49u)

#define	SDL_VPAC0_ECC_AGGR (50u)

#define	SDL_VPAC0_VISS_ECC_AGGR (51u)

#define	SDL_VPAC0_LDC_ECC_AGGR (52u)

#define	SDL_R5FSS0_CORE0_ECC_AGGR (53u)

#define	SDL_R5FSS1_CORE0_ECC_AGGR (54u)

#define	SDL_R5FSS0_CORE1_ECC_AGGR (55u)

#define	SDL_R5FSS1_CORE1_ECC_AGGR (56u)

#define	SDL_NAVSS_VIRTSS_ECC_AGGR0 (57u)

#define	SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR (58u)

#define	SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR (59u)

#define	SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR (60u)

#define	SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR (61u)

#define	SDL_MAIN_AC_ECC_AGGR0 (62u)

#define	SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR (63u)

#define	SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM (64u)

#define	SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM (65u)

#define	SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM (66u)

#define	SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM (67u)

#define	SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM (68u)

#define	SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM (69u)

#define	SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE (70u)

#define	SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY (71u)

#define	SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC (72u)

#define	SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR (73u)

#define	SDL_CSI_RX_IF0_ECC_AGGR_0 (74u)

#define	SDL_CSI_RX_IF1_ECC_AGGR_0 (75u)

#define	SDL_NAVSS0_MODSS_ECC_AGGR0 (76u)

#define	SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR (77u)

#define	SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR (78u)

#define	SDL_NAVSS0_VIRTSS_ECC_AGGR0 (79u)

#define	SDL_NAVSS0_NBSS_ECC_AGGR0 (80u)

#define	SDL_IDOM1_ECC_AGGR0 (81u)

#define	SDL_IDOM1_ECC_AGGR1 (82u)

#define	SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR (83u)

#define	SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR (84u)

#define	SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR (85u)

#define	SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR (86u)

#define	SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE (87u)

#define	SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR (88u)

#define	SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS (89u)

#define	SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0 (90u)

#define	SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR (91u)

#define	SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR (92u)

#define	SDL_NAVSS0_UDMASS_ECC_AGGR0 (93u)

#define	SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR0 (94u)

#define	SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR1 (95u)

#define	SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR2 (96u)

#define	SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR (97u)

#define	SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR (98u)

#define	SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR (99u)

#define	SDL_COMPUTE_CLUSTER0_DDR32SSC_EW_BRCTL_SC_ECC_AGGR_VBUS (100u)

#define	SDL_COMPUTE_CLUSTER0_DDR32SSC_EW_BRCTL_SC_ECC_AGGR_CTL (101u)

#define	SDL_COMPUTE_CLUSTER0_DDR32SSC_EW_BRCTL_SC_ECC_AGGR_CFG (102u)

#define	SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR (103u)

#define	SDL_ECC_MEMTYPE_MAX (SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR + 1U)

#define	SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK0_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID)
	Select memory subtype ATCM0 BANK0. More...

#define	SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK1_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID)
	Select memory subtype ATCM0 BANK1. More...

#define	SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK0_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID)
	Select memory subtype B0TCM0 BANK0. More...

#define	SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK1_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID)
	Select memory subtype B0TCM0 BANK1. More...

#define	SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK0_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID)
	Select memory subtype B1TCM0 BANK0. More...

#define	SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK1_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID)
	Select memory subtype B1TCM0 BANK1. More...

#define	SDL_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID)
	Select memory subtype VIM RAM. More...

Macro Definition Documentation

◆ SDL_ECC_MEMTYPE_MCU_R5F0_CORE

#define SDL_ECC_MEMTYPE_MCU_R5F0_CORE (0u)

◆ SDL_ECC_MEMTYPE_MCU_R5F1_CORE

#define SDL_ECC_MEMTYPE_MCU_R5F1_CORE (1u)

◆ SDL_ECC_MEMTYPE_MCU_ADC0

#define SDL_ECC_MEMTYPE_MCU_ADC0 (2u)

◆ SDL_ECC_MEMTYPE_MCU_ADC1

#define SDL_ECC_MEMTYPE_MCU_ADC1 (3u)

◆ SDL_ECC_MEMTYPE_MCU_CPSW0

#define SDL_ECC_MEMTYPE_MCU_CPSW0 (4u)

◆ SDL_ECC_MEMTYPE_MCU_FSS0_HPB0

#define SDL_ECC_MEMTYPE_MCU_FSS0_HPB0 (5u)

◆ SDL_ECC_MEMTYPE_MCU_FSS0_OSPI0

#define SDL_ECC_MEMTYPE_MCU_FSS0_OSPI0 (6u)

◆ SDL_ECC_MEMTYPE_MCU_FSS0_OSPI1

#define SDL_ECC_MEMTYPE_MCU_FSS0_OSPI1 (7u)

◆ SDL_ECC_MEMTYPE_MCU_MCAN0

#define SDL_ECC_MEMTYPE_MCU_MCAN0 (8u)

◆ SDL_ECC_MEMTYPE_MCU_MCAN1

#define SDL_ECC_MEMTYPE_MCU_MCAN1 (9u)

◆ SDL_ECC_MEMTYPE_MCU_MSRAM0

#define SDL_ECC_MEMTYPE_MCU_MSRAM0 (10u)

◆ SDL_ECC_MEMTYPE_MCU_NAVSS0

#define SDL_ECC_MEMTYPE_MCU_NAVSS0 (11u)

◆ SDL_ECC_MEMTYPE_MCU_PSRAM0

#define SDL_ECC_MEMTYPE_MCU_PSRAM0 (12u)

◆ SDL_ECC_MEMTYPE_MCU_CBASS_ECC_AGGR0

#define SDL_ECC_MEMTYPE_MCU_CBASS_ECC_AGGR0 (13u)

◆ SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR

#define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR (14u)

◆ SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR

#define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR (15u)

◆ SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR

#define SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR (16u)

◆ SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR

#define SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR (17u)

◆ SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR

#define SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR (18u)

◆ SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR

#define SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR (19u)

◆ SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR

#define SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR (20u)

◆ SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR

#define SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR (21u)

◆ SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR

#define SDL_MCAN8_MCANSS_MSGMEM_WRAP_ECC_AGGR (22u)

◆ SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR

#define SDL_MCAN9_MCANSS_MSGMEM_WRAP_ECC_AGGR (23u)

◆ SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR

#define SDL_MCAN10_MCANSS_MSGMEM_WRAP_ECC_AGGR (24u)

◆ SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR

#define SDL_MCAN11_MCANSS_MSGMEM_WRAP_ECC_AGGR (25u)

◆ SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR

#define SDL_MCAN12_MCANSS_MSGMEM_WRAP_ECC_AGGR (26u)

◆ SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR

#define SDL_MCAN13_MCANSS_MSGMEM_WRAP_ECC_AGGR (27u)

◆ SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR

#define SDL_MSRAM_512K0_MSRAM16KX256E_ECC_AGGR (28u)

◆ SDL_PCIE0_ECC_AGGR_CORE_AXI_0

#define SDL_PCIE0_ECC_AGGR_CORE_AXI_0 (29u)

◆ SDL_PCIE0_ECC_AGGR_CORE_0

#define SDL_PCIE0_ECC_AGGR_CORE_0 (30u)

◆ SDL_PCIE1_ECC_AGGR_CORE_AXI_0

#define SDL_PCIE1_ECC_AGGR_CORE_AXI_0 (31u)

◆ SDL_PCIE1_ECC_AGGR_CORE_0

#define SDL_PCIE1_ECC_AGGR_CORE_0 (32u)

◆ SDL_PCIE2_ECC_AGGR_CORE_AXI_0

#define SDL_PCIE2_ECC_AGGR_CORE_AXI_0 (33u)

◆ SDL_PCIE2_ECC_AGGR_CORE_0

#define SDL_PCIE2_ECC_AGGR_CORE_0 (34u)

◆ SDL_PCIE3_ECC_AGGR_CORE_AXI_0

#define SDL_PCIE3_ECC_AGGR_CORE_AXI_0 (35u)

◆ SDL_PCIE3_ECC_AGGR_CORE_0

#define SDL_PCIE3_ECC_AGGR_CORE_0 (36u)

◆ SDL_I3C0_I3C_S_ECC_AGGR

#define SDL_I3C0_I3C_S_ECC_AGGR (37u)

◆ SDL_I3C0_I3C_P_ECC_AGGR

#define SDL_I3C0_I3C_P_ECC_AGGR (38u)

◆ SDL_MCU_I3C0_I3C_P_ECC_AGGR

#define SDL_MCU_I3C0_I3C_P_ECC_AGGR (39u)

◆ SDL_MCU_I3C0_I3C_S_ECC_AGGR

#define SDL_MCU_I3C0_I3C_S_ECC_AGGR (40u)

◆ SDL_MCU_I3C1_I3C_P_ECC_AGGR

#define SDL_MCU_I3C1_I3C_P_ECC_AGGR (41u)

◆ SDL_MCU_I3C1_I3C_S_ECC_AGGR

#define SDL_MCU_I3C1_I3C_S_ECC_AGGR (42u)

◆ SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR

#define SDL_PRU_ICSSG0_ICSS_G_CORE_BORG_ECC_AGGR (43u)

◆ SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR

#define SDL_PRU_ICSSG1_ICSS_G_CORE_BORG_ECC_AGGR (44u)

◆ SDL_CBASS_ECC_AGGR0

#define SDL_CBASS_ECC_AGGR0 (45u)

◆ SDL_MAIN_RC_ECC_AGGR0

#define SDL_MAIN_RC_ECC_AGGR0 (46u)

◆ SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR

#define SDL_NAVSS_NBSS_ECC_AGGR0_NAVSS512L_NBSS_PHYS_ECC_AGGR (47u)

◆ SDL_DMPAC0_ECC_AGGR

#define SDL_DMPAC0_ECC_AGGR (48u)

◆ SDL_MAIN_HC_ECC_AGGR0

#define SDL_MAIN_HC_ECC_AGGR0 (49u)

◆ SDL_VPAC0_ECC_AGGR

#define SDL_VPAC0_ECC_AGGR (50u)

◆ SDL_VPAC0_VISS_ECC_AGGR

#define SDL_VPAC0_VISS_ECC_AGGR (51u)

◆ SDL_VPAC0_LDC_ECC_AGGR

#define SDL_VPAC0_LDC_ECC_AGGR (52u)

◆ SDL_R5FSS0_CORE0_ECC_AGGR

#define SDL_R5FSS0_CORE0_ECC_AGGR (53u)

◆ SDL_R5FSS1_CORE0_ECC_AGGR

#define SDL_R5FSS1_CORE0_ECC_AGGR (54u)

◆ SDL_R5FSS0_CORE1_ECC_AGGR

#define SDL_R5FSS0_CORE1_ECC_AGGR (55u)

◆ SDL_R5FSS1_CORE1_ECC_AGGR

#define SDL_R5FSS1_CORE1_ECC_AGGR (56u)

◆ SDL_NAVSS_VIRTSS_ECC_AGGR0

#define SDL_NAVSS_VIRTSS_ECC_AGGR0 (57u)

◆ SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR

#define SDL_CBASS_ECC_AGGR0_MSRAM32KX256E_ECC_AGGR (58u)

◆ SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR

#define SDL_MCU_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR (59u)

◆ SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR

#define SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR (60u)

◆ SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR

#define SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR (61u)

◆ SDL_MAIN_AC_ECC_AGGR0

#define SDL_MAIN_AC_ECC_AGGR0 (62u)

◆ SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR

#define SDL_WKUP_VTM0_K3VTM_NC_ECCAGGR (63u)

◆ SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM

#define SDL_MMCSD0_EMMC8SSC_ECC_AGGR_RXMEM (64u)

◆ SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM

#define SDL_MMCSD0_EMMC8SSC_ECC_AGGR_TXMEM (65u)

◆ SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM

#define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM (66u)

◆ SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM

#define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM (67u)

◆ SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM

#define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_RXMEM (68u)

◆ SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM

#define SDL_MMCSD2_EMMCSD4SS_ECC_AGGR_TXMEM (69u)

◆ SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE

#define SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_CORE (70u)

◆ SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY

#define SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_PHY (71u)

◆ SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC

#define SDL_DSS_EDP0_K3_DSS_EDP_MHDPTX_WRAPPER_ECC_AGGR_DSC (72u)

◆ SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR

#define SDL_UFS0_UFSHCI2P1SSC_HCLK_ECC_AGGR (73u)

◆ SDL_CSI_RX_IF0_ECC_AGGR_0

#define SDL_CSI_RX_IF0_ECC_AGGR_0 (74u)

◆ SDL_CSI_RX_IF1_ECC_AGGR_0

#define SDL_CSI_RX_IF1_ECC_AGGR_0 (75u)

◆ SDL_NAVSS0_MODSS_ECC_AGGR0

#define SDL_NAVSS0_MODSS_ECC_AGGR0 (76u)

◆ SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR

#define SDL_USB0_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR (77u)

◆ SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR

#define SDL_USB1_USB3P0SSC_USB3P0SS_CORE_A_ECC_AGGR (78u)

◆ SDL_NAVSS0_VIRTSS_ECC_AGGR0

#define SDL_NAVSS0_VIRTSS_ECC_AGGR0 (79u)

◆ SDL_NAVSS0_NBSS_ECC_AGGR0

#define SDL_NAVSS0_NBSS_ECC_AGGR0 (80u)

◆ SDL_IDOM1_ECC_AGGR0

#define SDL_IDOM1_ECC_AGGR0 (81u)

◆ SDL_IDOM1_ECC_AGGR1

#define SDL_IDOM1_ECC_AGGR1 (82u)

◆ SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR

#define SDL_WKUP_CBASS_ECC_AGGR0_K3VTM_NC_ECCAGGR (83u)

◆ SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR

#define SDL_IDOM0_ECC_AGGR0_IDOM0_ECC_AGGR (84u)

◆ SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR

#define SDL_IDOM0_ECC_AGGR1_IDOM0_ECC_AGGR (85u)

◆ SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR

#define SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR (86u)

◆ SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE

#define SDL_CSI_TX_IF0_CSI_TX_IF_ECC_AGGR_BYTE (87u)

◆ SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR

#define SDL_WKUP_CBASS_ECC_AGGR0_WAKEUP_ECC_AGGR (88u)

◆ SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS

#define SDL_DSS_DSI0_K3_DSS_DSI_TOP_ECC_AGGR_SYS (89u)

◆ SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0

#define SDL_MCU_NAVSS0_UDMASS_ECC_AGGR0 (90u)

◆ SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR

#define SDL_PDMA5_PDMA_MAIN_MCAN_ECCAGGR (91u)

◆ SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR

#define SDL_PSRAMECC0_PSRAM256X32EC_ECC_AGGR (92u)

◆ SDL_NAVSS0_UDMASS_ECC_AGGR0

#define SDL_NAVSS0_UDMASS_ECC_AGGR0 (93u)

◆ SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR0

#define SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR0 (94u)

◆ SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR1

#define SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR1 (95u)

◆ SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR2

#define SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR2 (96u)

◆ SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR

#define SDL_COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR (97u)

◆ SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR

#define SDL_COMPUTE_CLUSTER0_A72SS0_CORE0_ECC_AGGR (98u)

◆ SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR

#define SDL_COMPUTE_CLUSTER0_A72SS0_CORE1_ECC_AGGR (99u)

◆ SDL_COMPUTE_CLUSTER0_DDR32SSC_EW_BRCTL_SC_ECC_AGGR_VBUS

#define SDL_COMPUTE_CLUSTER0_DDR32SSC_EW_BRCTL_SC_ECC_AGGR_VBUS (100u)

◆ SDL_COMPUTE_CLUSTER0_DDR32SSC_EW_BRCTL_SC_ECC_AGGR_CTL

#define SDL_COMPUTE_CLUSTER0_DDR32SSC_EW_BRCTL_SC_ECC_AGGR_CTL (101u)

◆ SDL_COMPUTE_CLUSTER0_DDR32SSC_EW_BRCTL_SC_ECC_AGGR_CFG

#define SDL_COMPUTE_CLUSTER0_DDR32SSC_EW_BRCTL_SC_ECC_AGGR_CFG (102u)

◆ SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR

#define SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR (103u)

◆ SDL_ECC_MEMTYPE_MAX

#define SDL_ECC_MEMTYPE_MAX (SDL_COMPUTE_CLUSTER0_C71SS0_ECC_AGGR + 1U)

◆ SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK0_VECTOR_ID

#define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK0_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID)

Select memory subtype ATCM0 BANK0.

◆ SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK1_VECTOR_ID

#define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK1_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID)

Select memory subtype ATCM0 BANK1.

◆ SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK0_VECTOR_ID

#define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK0_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID)

Select memory subtype B0TCM0 BANK0.

◆ SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK1_VECTOR_ID

#define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK1_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID)

Select memory subtype B0TCM0 BANK1.

◆ SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK0_VECTOR_ID

#define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK0_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID)

Select memory subtype B1TCM0 BANK0.

◆ SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK1_VECTOR_ID

#define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK1_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID)

Select memory subtype B1TCM0 BANK1.

◆ SDL_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID

#define SDL_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID)

Select memory subtype VIM RAM.

Typedef Documentation

◆ SDL_ECC_MemType

typedef uint32_t SDL_ECC_MemType

This enumerator indicate ECC memory type.

◆ SDL_ECC_MemSubType

typedef uint32_t SDL_ECC_MemSubType

This enumerator indicate ECC memory Sub Type.

◆ SDL_ECC_ErrorCallback_t

typedef void(* SDL_ECC_ErrorCallback_t) (uint32_t errorSrc, uint32_t address)

/brief Format of ECC error Call back function

◆ SDL_ECC_VIMDEDVector_t

typedef void(* SDL_ECC_VIMDEDVector_t) (void)

/brief Format of VIM DED vector function