2.3. Release Notes - 08_00_00¶

2.3.3.1. FreeRTOS¶

See FreeRTOS Chapter for more details.

2.3.3.2. lwIP¶

This release introduces lwIP TCP/IP stack support for J721E on R5F, C66x, C7x cores. lwIP is supported and validated with FreeRTOS, it’s not supported on TI-RTOS (SysBIOS).

Enet LLD implements the lwIP driver interface which enables lwIP stack to run transparently on top of the Ethernet peripherals supported by Enet driver. Enet LLD provides a lwIP example application which showcases lwIP integration on peripherals supported by Enet driver, where user can run tests such as ping, UDP/TCP echo and iperf. This example supports DHCP and static IP. For more information, see Enet LLD examples section.

lwIP stack is enabled for CPSW_2G and CPSW_9G.

This is the last release with TI NDK TCP/IP stack support. Enet LLD NIMU example has been validated as well on supported cores in this release. TI NDK stack support will be scoped out starting from next release.

2.3.3.3. OSAL¶

As part of FreeRTOS Migration, following new OSAL modules are added

• ClockP <= SW Timer
• MailboxP <= Software Mailbox
• MutexP <= Mutex
• HeapP <= For creating arbitrary heaps
• LoadP <= Task / CPU Load measurement [FreeRTOS Only]

Also following are the updates for existing OSAL modules.

• EventP

  • New API EventP_wait()
  • EventP_pend() supports only SysBIOS. This will be obsolete in next release. Migrate to new similar API EventP_wait()

• QueueP

  • Header file is renamed to QueueP.h from Queue.h
  • Following OSAL Queue APIs supports only SysBIOS and will be obsolete in next release. Migrate to new QueueP APIs

  Old API	New API
  Osal_Queue_Handle	QueueP_Handle
  Osal_Queue_Elem	QueueP_Elem
  -NA-	QueueP_Params
  -NA-	QueueP_Params_init
  Osal_Queue_construct + Osal_Queue_handle	QueueP_create
  -NA-	QueueP_delete
  Osal_Queue_put	QueueP_put
  Osal_Queue_get	QueueP_get
  Osal_Queue_empty	QueueP_isEmpty

2.3.3.4. DDR¶

DDR Boot time(initialization + training) is optimized in this release and is now in the range of ~35 ms.

This includes:-

• DDR Register Settings updates and
• Disabled DDR Register write verification, given there is DDR inline ECC. (Support for register Verification post init/training will be provided in future release.)

Priming of DDR for ECC is now optimized by usage of UDMA.

Following in PDK_INSTALL_DIR/packages/ti/board/src/j721e_evm/include/board_cfg.h can be modified as per the user requirement.

/* Note with ECC enabled, all memory is not usable: 1/8 memory used for inline ECC */
#define BOARD_DDR_ECC_END_ADDR                          (0xF1FFFFFFU)
/* Enable/Disable DDR Memory Prime for ECC. Define the following macro to enable. */
#undef BOARD_DDR_ENABLE_DDR_MEM_PRIME

2.3.3.5. XIP¶

A new twin appimage bootflow has been introduced. There is one appimage for RAM sections and one appimage for xip sections.

• For each CPU, the compiler+linker toolchain is used to create the application .out “ELF” file which can be loaded and run via CCS
• The below “post build” steps are then used to convert the application .out into a “flash” friendly format - For each CPU, out2rpc is used to convert the ELF .out to a binary file containing only the loadable sections. This is called a RPRC file. - For each CPU, xipGen is used to split this RPRC file into two RPRC files. - One RPRC, containing the section that during boot need to be loaded to RAM - Second RPRC, containing the section that during boot are not loaded to RAM but are instead “eXecuted In Place”, i.e XIP - multiCoreGen is then used to combine all the non-XIP RPRC files per CPU into a single .appimage file which is a concatenation of the individual CPU specific RPRC files. - multiCoreGen is used again to combine all the XIP RPRC files per CPU into a single .appimage_xip file which is a concatenation of the individual CPU specific RPRC XIP files.
• This .appimage and .appimage_xip is then flashed to the EVM using Uniflash
• Upon booting, the SBL interpets the .appimage and loads the RAM sections into respective memory.
• The .appimage_xip contains the sections that are executed in place.

See XIP Programming Guide for more details.

2.3.3.6. SMP mode¶

• SMP Support is de-scoped and PDK Examples will not support execution in SMP mode

2.3.3.7. Board Diagnostics¶

• Board diagnostics stress test is not supported

2.3.3.8. PCIe, USB¶

• PCIE and USB Support is removed for J721E.

2.3.10.1. PDK¶

• PDK examples do not support SMP mode. Some of examples still support build in SMP mode but these binaries are not supported or validated.

2.3.10.2. ENET¶

• lwIP stack integration doesn’t support checksum hardware-offload feature.
• ICSSG integration with lwIP and NDK is done only for ICSSG Dual-MAC. Driver level support is available for Dual-MAC and Switch.
• TimeSync PTP integration is done only for ICSSG-Dual MAC.
• TimeSync is possible only in one MAC port at a time.
• Different VLAN modes are not supported in Dual-MAC mode (within given ICSSG MAC ports). Both MACs should either be in VLAN aware or VLAN unaware mode.
• Independent VLAN learning is not supported in Dual-MAC mode.