9.5. XIP Using Two Appimages¶

9.5.1. Rom An Application¶

ROMing an application or running from XIP is running from a read-only memory - essentially XIP boils down to running an application from a read-only memory.

9.5.2. What is XIP?¶

In order to take advantage of the XIP mode, two conditions must be fulfilled:

1. The NOR flash (or flash device in general) device must support DAC mode

2. The microcontroller’s SPI controller must support XIP mode

   1. Burst mode of access - no byte access but a 32bit accesses only in XIP mode
   2. As code must be in memory to be executed, XIP requires a memory-mappable device such as a RAM, ROM, or a NOR Flash.
   3. The serial NOR flash memory is mapped in the microcontroller’s memory space and is seen as another memory by the processor.

9.5.3. Why XIP?¶

• Improve startup/boot time - Initial time of copying code from flash to RAM is saved
• Size of on-chip RAM will not limit the application size
• NOTE: Slower than internal memory - 2.5 - 3x times worse than OCM

9.5.4. TWIN APPIMAGE GENERATION¶

The xx_component.mk must have these two present for twin appimage generation.

export *_testapp_SBL_APPIMAGEGEN = yes
export *_testapp_SBL_XIP_APPIMAGEGEN = yes

• For each CPU, the compiler+linker toolchain is used to create the application .out “ELF” file which can be loaded and run via CCS

• The below “post build” steps are then used to convert the application .out into a “flash” friendly format

  • For each CPU, out2rpc is used to convert the ELF .out to a binary file containing only the loadable sections. This is called a RPRC file.
  • For each CPU, xipGen is used to split this RPRC file into two RPRC files.
  • One RPRC, containing the section that during boot need to be loaded to RAM
  • Second RPRC, containing the section that during boot are not loaded to RAM but are instead “eXecuted In Place”, i.e XIP
  • multiCoreGen is then used to combine all the non-XIP RPRC files per CPU into a single .appimage file which is a concatenation of the individual CPU specific RPRC files.
  • multiCoreGen is used again to combine all the XIP RPRC files per CPU into a single .appimage_xip file which is a concatenation of the individual CPU specific RPRC XIP files.

• This .appimage and .appimage_xip is then flashed to the EVM

9.5.4.1. MULTICORE APPIMAGE GENERATION¶

Add this to your multicore generation script

MULTICORE_IMG_PARAMS_XIP = $(foreach SOC_CORE_ID, $(ipc_perf_test_$(SOC)_CORELIST), $(SBL_CORE_ID_$(SOC_CORE_ID)) $(BINDIR)/$(RPRC_PREFIX)_$(SOC_CORE_ID)_$(BUILD_PROFILE_$(CORE)).rprc_xip)
$(ECHO) "# MULTICORE_IMG_PARAMS_XIP are $(MULTICORE_IMG_PARAMS_XIP)"
$(SBL_IMAGE_GEN) LE $(SBL_DEV_ID) $(BINDIR)/$(RPRC_PREFIX)_all_cores_$(BUILD_PROFILE_$(CORE)).appimage_xip $(MULTICORE_IMG_PARAMS_XIP)
$(ECHO) "#"
$(ECHO) "# Multicore IPC App image $(BINDIR)/$(RPRC_PREFIX)_all_cores_$(BUILD_PROFILE_$(CORE)).appimage_xip created."
$(ECHO) "#"
$(ECHO) "# Signing the multicore image...."

MEMORY
{
    ...
    ...

    XIP_FLASH_1               : origin=0x501C0000 length=0x40000
    XIP_FLASH_2               : origin=0x50200000 length=0x10000

    ...
    ...
}

SECTIONS
{
    ...
    ...

    .text       : {} palign(8)      > XIP_FLASH_1
    .const      : {} palign(8)      > XIP_FLASH_2

    ...
    ...
}

#include <ti/csl/arch/csl_arch.h>
const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
{
    ...
    ...

    {
        //Region x configuration: Covers first 64MB of EVM Flash (FSS DAT0) *
        .regionId         = xU,
        .enable           = 1U,
        .baseAddr         = 0x50000000,
        .size             = CSL_ARM_R5_MPU_REGION_SIZE_64MB,
        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,
        .exeNeverControl  = 0U,
        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
        .shareable        = 0U,
        .cacheable        = (uint32_t)TRUE,
        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_WB_WA,
        .memAttr          = 0U,
    },

    ...
    ...
}

cd <pathToPDKRepo>/packages/ti/board/utils/uniflash/host/
make all (Linux) or gmake all (Windows)
copy ProcessorSDKSerialFlash (Linux) or ProcessorSDKSerialFlash.exe (Windows) to <pathToUniflashDirectory>\processors\
cd <pathToPDKRepo>/packages/ti/build/
make board_utils_uart_flash_programmer BOARD=j7xx_evm CORE=mcu1_0 -sj8
copy <pathToPDKRepo>/packages/ti/binary/uart_j7xx_evm_flash_programmer_release.tiimage to <pathToUniflashDirectory>\processors\FlashWriter\j7xx_evm

9.5.5. Known Issues¶

Closing the flash doesn’t work if the OSPI controller is in XIP mode.

9.5.6. Useful Links¶

• XIP wiki: https://en.wikipedia.org/wiki/Execute_in_place
• XIP blog: http://www.vlsiip.com/c/embedded_c/xip.html
• Linker command file: http://downloads.ti.com/docs/esd/SPRU513J/Content/SPRU513J_HTML/linker_description.html
• Linker command file basic: https://software-dl.ti.com/ccs/esd/documents/sdto_cgt_Linker-Command-File-Primer.html
• Load and run section: http://downloads.ti.com/docs/esd/SPRU513/load-and-run-addresses-slau1317366.html
• Micrium documentation: https://doc.micrium.com/display/TECHOV/NOR+Flash+XIP