sdl_ecc_soc.h File Reference

Go to the source code of this file.

Macros
#define	SDL_PULSAR_CPU_RAM_ID_TABLE_MAX_ENTRIES   (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_RAM_ID+1u)
#define	SDL_MSMC_AGGR0_RAM_ID_TABLE_MAX_ENTRIES   (SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_RAM_ID+1u)
#define	SDL_MCU_CBASS_RAM_ID_TABLE_MAX_ENTRIES   (SDL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_RAM_ID+1u)
#define	SDL_PULSAR_CPU_WRAPPER_RAM_IDS_TOTAL_ENTRIES   (28U)
#define	SDL_MSMC_AGGR0_WRAPPER_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCU_CBASS_WRAPPER_RAM_IDS_TOTAL_ENTRIES   (2U)
#define	SDL_PULSAR_CPU_RAM_ID_VBUSM2_AXI_EDC_VECTOR_GRP_MAX_ENTRIES   (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_MAX_NUM_CHECKERS)
#define	SDL_MSMC_AGGR0_RAM_ID_MSMC_MMR_BUSECC_GRP_MAX_ENTRIES   (SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_MAX_NUM_CHECKERS)
#define	SDL_MSMC_AGGR0_CACHE_TAG_MEM_INTERCONN_SUBTYPEGRP_MAX_ENTRIES   (SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_MAX_NUM_CHECKERS)
#define	SDL_MSMC_AGGR0_CLEC_EDC_CTRL_BUSECC_INTERCONN_SUBTYPEGRP_MAX_ENTRIES   (SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS)
#define	SDL_ECC_VIM_RAM_ID_WIDTH_CORRECTION   (2U)
	This structure holds the memory config for each memory subtype in MCU domain More...
#define	SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES   (SDL_ECC_MEMTYPE_MCU_CBASS_ECC_AGGR0+1u)
#define	SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES
#define	SDL_ECC_AGGREGATOR_MAX_ENTRIES
#define	SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_GROUP_0_CHECKER_TYPE   SDL_ECC_AGGR_CHECKER_TYPE_REDUNDANT
#define	SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_GROUP_0_WIDTH   (6U)
#define	SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_MAX_NUM_CHECKERS   (1U)
#define	SDL_MCU_CBASS_ECC_AGGR_IMCU_COR_FW_GRP_MAX_ENTRIES   SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_MAX_NUM_CHECKERS

Variables
const SDL_RAMIdEntry_t	SDL_ECC_mcuArmssRamIdTable [SDL_PULSAR_CPU_RAM_ID_TABLE_MAX_ENTRIES]
	This structure holds the list of Ram Ids for each memory subtype in MCU domain More...
const SDL_MemConfig_t	SDL_ECC_mcuArmssMemEntries [SDL_PULSAR_CPU_WRAPPER_RAM_IDS_TOTAL_ENTRIES]
SDL_ecc_aggrRegs *const	SDL_ECC_aggrBaseAddressTable [SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES]
	This structure holds the base addresses for each memory subtype in MCU domain More...
uint64_t const	SDL_ECC_aggrHighBaseAddressTable [SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES]
SDL_ecc_aggrRegs *	SDL_ECC_aggrHighBaseAddressTableTrans [SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES]
const SDL_RAMIdEntry_t	SDL_ECC_mainMsmcAggr0RamIdTable [SDL_MSMC_AGGR0_RAM_ID_TABLE_MAX_ENTRIES]
	This structure holds the list of Ram Ids for each memory subtype in MSMC AGGR0 More...
const SDL_RAMIdEntry_t	SDL_ECC_mcuEccAggr0RamIdTable [SDL_MSMC_AGGR0_RAM_ID_TABLE_MAX_ENTRIES]
const SDL_MemConfig_t	SDL_ECC_mainMsmcAggr0MemEntries [SDL_MSMC_AGGR0_WRAPPER_RAM_IDS_TOTAL_ENTRIES]
	This structure holds the memory config for each memory subtype in MCU domain More...
const SDL_MemConfig_t	SDL_ECC_MCUCBASSMemEntries [SDL_MCU_CBASS_WRAPPER_RAM_IDS_TOTAL_ENTRIES]
	This structure holds the memory config for each memory subtype in MCU CBASS More...
const SDL_GrpChkConfig_t	SDL_ECC_ramIdVbusM2AxiEdcVectorGrpEntries [SDL_PULSAR_CPU_RAM_ID_VBUSM2_AXI_EDC_VECTOR_GRP_MAX_ENTRIES]
	This structure holds the ECC interconnect Group Checker information for. More...
const SDL_GrpChkConfig_t	SDL_ECC_ramIdMsmcMMRBuseccGrpEntries [SDL_MSMC_AGGR0_RAM_ID_MSMC_MMR_BUSECC_GRP_MAX_ENTRIES]
	This structure holds the ECC interconnect Group Checker information for. More...
const SDL_GrpChkConfig_t	SDL_ECC_ramIdMsmccachetagMemGrpEntries [SDL_MSMC_AGGR0_CACHE_TAG_MEM_INTERCONN_SUBTYPEGRP_MAX_ENTRIES]
	This structure holds the ECC interconnect Group Checker information for. More...
const SDL_GrpChkConfig_t	SDL_ECC_ramIdMsmcClecMemGrpEntries [SDL_MSMC_AGGR0_CLEC_EDC_CTRL_BUSECC_INTERCONN_SUBTYPEGRP_MAX_ENTRIES]
	This structure holds the ECC interconnect Group Checker information for. More...
const SDL_GrpChkConfig_t	SDL_ECC_MCU_CBASS_ramId2GrpEntries [SDL_MCU_CBASS_ECC_AGGR_IMCU_COR_FW_GRP_MAX_ENTRIES]

Macro Definition Documentation

SDL_PULSAR_CPU_RAM_ID_TABLE_MAX_ENTRIES

#define SDL_PULSAR_CPU_RAM_ID_TABLE_MAX_ENTRIES   (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_RAM_ID+1u)

SDL_MSMC_AGGR0_RAM_ID_TABLE_MAX_ENTRIES

#define SDL_MSMC_AGGR0_RAM_ID_TABLE_MAX_ENTRIES   (SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_RAM_ID+1u)

SDL_MCU_CBASS_RAM_ID_TABLE_MAX_ENTRIES

#define SDL_MCU_CBASS_RAM_ID_TABLE_MAX_ENTRIES   (SDL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_RAM_ID+1u)

SDL_PULSAR_CPU_WRAPPER_RAM_IDS_TOTAL_ENTRIES

#define SDL_PULSAR_CPU_WRAPPER_RAM_IDS_TOTAL_ENTRIES   (28U)

SDL_MSMC_AGGR0_WRAPPER_RAM_IDS_TOTAL_ENTRIES

#define SDL_MSMC_AGGR0_WRAPPER_RAM_IDS_TOTAL_ENTRIES   (1U)

SDL_MCU_CBASS_WRAPPER_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_CBASS_WRAPPER_RAM_IDS_TOTAL_ENTRIES   (2U)

SDL_PULSAR_CPU_RAM_ID_VBUSM2_AXI_EDC_VECTOR_GRP_MAX_ENTRIES

#define SDL_PULSAR_CPU_RAM_ID_VBUSM2_AXI_EDC_VECTOR_GRP_MAX_ENTRIES   (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_MAX_NUM_CHECKERS)

SDL_MSMC_AGGR0_RAM_ID_MSMC_MMR_BUSECC_GRP_MAX_ENTRIES

#define SDL_MSMC_AGGR0_RAM_ID_MSMC_MMR_BUSECC_GRP_MAX_ENTRIES   (SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_MAX_NUM_CHECKERS)

SDL_MSMC_AGGR0_CACHE_TAG_MEM_INTERCONN_SUBTYPEGRP_MAX_ENTRIES

#define SDL_MSMC_AGGR0_CACHE_TAG_MEM_INTERCONN_SUBTYPEGRP_MAX_ENTRIES   (SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_MAX_NUM_CHECKERS)

SDL_MSMC_AGGR0_CLEC_EDC_CTRL_BUSECC_INTERCONN_SUBTYPEGRP_MAX_ENTRIES

#define SDL_MSMC_AGGR0_CLEC_EDC_CTRL_BUSECC_INTERCONN_SUBTYPEGRP_MAX_ENTRIES   (SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS)

SDL_ECC_VIM_RAM_ID_WIDTH_CORRECTION

#define SDL_ECC_VIM_RAM_ID_WIDTH_CORRECTION   (2U)

This structure holds the memory config for each memory subtype in MCU domain

---

SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES

#define SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES   (SDL_ECC_MEMTYPE_MCU_CBASS_ECC_AGGR0+1u)

SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES

#define SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES

Value:

(SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR2 - \
                                           SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR0 + 1u)

SDL_ECC_AGGREGATOR_MAX_ENTRIES

#define SDL_ECC_AGGREGATOR_MAX_ENTRIES

Value:

(SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES + \
                                        SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES)

SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_GROUP_0_CHECKER_TYPE

#define SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_GROUP_0_CHECKER_TYPE   SDL_ECC_AGGR_CHECKER_TYPE_REDUNDANT

SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_GROUP_0_WIDTH

#define SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_GROUP_0_WIDTH   (6U)

SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_MAX_NUM_CHECKERS

#define SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_MAX_NUM_CHECKERS   (1U)

SDL_MCU_CBASS_ECC_AGGR_IMCU_COR_FW_GRP_MAX_ENTRIES

#define SDL_MCU_CBASS_ECC_AGGR_IMCU_COR_FW_GRP_MAX_ENTRIES   SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_MAX_NUM_CHECKERS

Variable Documentation

SDL_ECC_mcuArmssRamIdTable

const SDL_RAMIdEntry_t SDL_ECC_mcuArmssRamIdTable[SDL_PULSAR_CPU_RAM_ID_TABLE_MAX_ENTRIES]

This structure holds the list of Ram Ids for each memory subtype in MCU domain

---

SDL_ECC_mcuArmssMemEntries

const SDL_MemConfig_t SDL_ECC_mcuArmssMemEntries[SDL_PULSAR_CPU_WRAPPER_RAM_IDS_TOTAL_ENTRIES]

SDL_ECC_aggrBaseAddressTable

SDL_ecc_aggrRegs* const SDL_ECC_aggrBaseAddressTable[SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES]

Initial value:

=
{
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_R5FSS0_CORE0_ECC_AGGR_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)0U)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_ADC0_ECC_REGS_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_ADC1_ECC_REGS_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_CPSW0_ECC_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_FSS0_HPB_ECC_AGGR_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_FSS0_OSPI0_ECC_AGGR_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_FSS0_OSPI1_ECC_AGGR_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_MCAN0_ECC_AGGR_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_MCAN1_ECC_AGGR_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_MSRAM_1MB0_ECC_AGGR_REGS_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_NAVSS0_ECCAGGR0_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)0U)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)0U)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PSRAMECC0_ECC_AGGR_BASE)),
    ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_CBASS_ECC_AGGR0_REGS_BASE)),
}

This structure holds the base addresses for each memory subtype in MCU domain

---

SDL_ECC_aggrHighBaseAddressTable

uint64_t const SDL_ECC_aggrHighBaseAddressTable[SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES]

Initial value:

=
{
    (uint64_t)SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_BASE,
    (uint64_t)SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_BASE,
    (uint64_t)SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_BASE,
}

SDL_ECC_aggrHighBaseAddressTableTrans

SDL_ecc_aggrRegs* SDL_ECC_aggrHighBaseAddressTableTrans[SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES]

SDL_ECC_mainMsmcAggr0RamIdTable

const SDL_RAMIdEntry_t SDL_ECC_mainMsmcAggr0RamIdTable[SDL_MSMC_AGGR0_RAM_ID_TABLE_MAX_ENTRIES]

This structure holds the list of Ram Ids for each memory subtype in MSMC AGGR0

---

SDL_ECC_mcuEccAggr0RamIdTable

const SDL_RAMIdEntry_t SDL_ECC_mcuEccAggr0RamIdTable[SDL_MSMC_AGGR0_RAM_ID_TABLE_MAX_ENTRIES]

Initial value:

=
{
 { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_RAM_ID,
       SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_INJECT_TYPE,
       SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_ECC_TYPE }, 
 { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_RAM_ID,
       SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_INJECT_TYPE,
       SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_ECC_TYPE }, 
 { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_RAM_ID,
       SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_INJECT_TYPE,
       SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_ECC_TYPE }, 
}

SDL_ECC_mainMsmcAggr0MemEntries

const SDL_MemConfig_t SDL_ECC_mainMsmcAggr0MemEntries[SDL_MSMC_AGGR0_WRAPPER_RAM_IDS_TOTAL_ENTRIES]

Initial value:

=
{
    {SDL_ECC_MAIN_MSMC_MEM_WRAPPER_SUBTYPE, 0u,
         SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_RAM_SIZE, 4u,
         SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_ROW_WIDTH, ((bool)false) },
}

This structure holds the memory config for each memory subtype in MCU domain

---

SDL_ECC_MCUCBASSMemEntries

const SDL_MemConfig_t SDL_ECC_MCUCBASSMemEntries[SDL_MCU_CBASS_WRAPPER_RAM_IDS_TOTAL_ENTRIES]

Initial value:

=
{
    {SDL_ECC_MCU_CBASS_MEM_SUBTYPE_WR_RAMECC_ID, 0u,
         SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_RAM_SIZE, 4u, ((bool)false)  },
    {SDL_ECC_MCU_CBASS_MEM_SUBTYPE_RD_RAMECC_ID, 0u,
        SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_RAM_SIZE, 4u, ((bool)false)   },
}

This structure holds the memory config for each memory subtype in MCU CBASS

---

SDL_ECC_ramIdVbusM2AxiEdcVectorGrpEntries

const SDL_GrpChkConfig_t SDL_ECC_ramIdVbusM2AxiEdcVectorGrpEntries[SDL_PULSAR_CPU_RAM_ID_VBUSM2_AXI_EDC_VECTOR_GRP_MAX_ENTRIES]

This structure holds the ECC interconnect Group Checker information for.

---

SDL_ECC_R5F_MEM_SUBTYPE_VBUSM2AXI_EDC_VECTOR_ID RAM ID

SDL_ECC_ramIdMsmcMMRBuseccGrpEntries

const SDL_GrpChkConfig_t SDL_ECC_ramIdMsmcMMRBuseccGrpEntries[SDL_MSMC_AGGR0_RAM_ID_MSMC_MMR_BUSECC_GRP_MAX_ENTRIES]

This structure holds the ECC interconnect Group Checker information for.

---

SDL_ECC_MAIN_MSMC_MEM_INTERCONN_SUBTYPE RAM ID

SDL_ECC_ramIdMsmccachetagMemGrpEntries

const SDL_GrpChkConfig_t SDL_ECC_ramIdMsmccachetagMemGrpEntries[SDL_MSMC_AGGR0_CACHE_TAG_MEM_INTERCONN_SUBTYPEGRP_MAX_ENTRIES]

This structure holds the ECC interconnect Group Checker information for.

---

SDL_ECC_MAIN_MSMC_CACHE_TAG_MEM_INTERCONN_SUBTYPE RAM ID

SDL_ECC_ramIdMsmcClecMemGrpEntries

const SDL_GrpChkConfig_t SDL_ECC_ramIdMsmcClecMemGrpEntries[SDL_MSMC_AGGR0_CLEC_EDC_CTRL_BUSECC_INTERCONN_SUBTYPEGRP_MAX_ENTRIES]

Initial value:

=
{
    {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
     SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_GROUP_0_WIDTH},
}

This structure holds the ECC interconnect Group Checker information for.

---

SDL_ECC_MAIN_MSMC_CACHE_TAG_MEM_INTERCONN_SUBTYPE RAM ID

SDL_ECC_MCU_CBASS_ramId2GrpEntries

const SDL_GrpChkConfig_t SDL_ECC_MCU_CBASS_ramId2GrpEntries[SDL_MCU_CBASS_ECC_AGGR_IMCU_COR_FW_GRP_MAX_ENTRIES]

Initial value:

=
{
    {SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_GROUP_0_CHECKER_TYPE,
     SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_GROUP_0_WIDTH },
}