SDL API Guide for J721E
sdl_ecc_soc.h
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1 /*
2  * SDL ECC
3  *
4  * Software Diagnostics Library module for ECC
5  *
6  * Copyright (c) Texas Instruments Incorporated 2021
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  *
12  * Redistributions of source code must retain the above copyright
13  * notice, this list of conditions and the following disclaimer.
14  *
15  * Redistributions in binary form must reproduce the above copyright
16  * notice, this list of conditions and the following disclaimer in the
17  * documentation and/or other materials provided with the
18  * distribution.
19  *
20  * Neither the name of Texas Instruments Incorporated nor the names of
21  * its contributors may be used to endorse or promote products derived
22  * from this software without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35  *
36  */
37 
38 #ifndef INCLUDE_SDL_ECC_SOC_H_
39 #define INCLUDE_SDL_ECC_SOC_H_
40 
41 #include <stdint.h>
42 #include <sdl_ecc.h>
43 #include <src/ip/sdl_ip_ecc.h>
44 #include <soc.h>
45 
46 #include "ecc/sdl_ecc_priv.h"
47 
48 /* define MAX entry based on list of Subtypes */
49 #define SDL_PULSAR_CPU_RAM_ID_TABLE_MAX_ENTRIES (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_RAM_ID+1u)
50 #define SDL_MSMC_AGGR0_RAM_ID_TABLE_MAX_ENTRIES (SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_RAM_ID+1u)
51 #define SDL_MCU_CBASS_RAM_ID_TABLE_MAX_ENTRIES (SDL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_RAM_ID+1u)
52 
53 /* define Max memEntries for each aggregator (i.e. the number of RAM ID's with
54  * Wrapper type) */
55 #define SDL_PULSAR_CPU_WRAPPER_RAM_IDS_TOTAL_ENTRIES (28U)
56 #define SDL_MSMC_AGGR0_WRAPPER_RAM_IDS_TOTAL_ENTRIES (1U)
57 #define SDL_MCU_CBASS_WRAPPER_RAM_IDS_TOTAL_ENTRIES (2U)
58 
59 #define SDL_PULSAR_CPU_RAM_ID_VBUSM2_AXI_EDC_VECTOR_GRP_MAX_ENTRIES (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_MAX_NUM_CHECKERS)
60 
61 #define SDL_MSMC_AGGR0_RAM_ID_MSMC_MMR_BUSECC_GRP_MAX_ENTRIES (SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_MAX_NUM_CHECKERS)
62 
63 #define SDL_MSMC_AGGR0_CACHE_TAG_MEM_INTERCONN_SUBTYPEGRP_MAX_ENTRIES (SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_MAX_NUM_CHECKERS)
64 
65 #define SDL_MSMC_AGGR0_CLEC_EDC_CTRL_BUSECC_INTERCONN_SUBTYPEGRP_MAX_ENTRIES (SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS)
66 
71 const SDL_RAMIdEntry_t SDL_ECC_mcuArmssRamIdTable[SDL_PULSAR_CPU_RAM_ID_TABLE_MAX_ENTRIES] =
72 {
73  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
74  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
75  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE },
76  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
77  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
78  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE },
79  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
80  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
81  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE },
82  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
83  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
84  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE },
85  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
86  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
87  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE },
88  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
89  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
90  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE },
91  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
92  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
93  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE },
94  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
95  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
96  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE },
97  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
98  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
99  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE },
100  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
101  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
102  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE },
103  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
104  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
105  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE },
106  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
107  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
108  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE },
109  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
110  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
111  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE },
112  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
113  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
114  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE },
115  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
116  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
117  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE },
118  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
119  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
120  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE },
121  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
122  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
123  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE },
124  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
125  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
126  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE },
127  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
128  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
129  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE },
130  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
131  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
132  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE },
133  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
134  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
135  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE },
136  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID,
137  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_INJECT_TYPE,
138  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ECC_TYPE },
139  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID,
140  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_INJECT_TYPE,
141  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ECC_TYPE },
142  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID,
143  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_INJECT_TYPE,
144  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ECC_TYPE },
145  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID,
146  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_INJECT_TYPE,
147  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ECC_TYPE },
148  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID,
149  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_INJECT_TYPE,
150  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ECC_TYPE },
151  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID,
152  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_INJECT_TYPE,
153  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ECC_TYPE },
154  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID,
155  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_INJECT_TYPE,
156  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ECC_TYPE },
157  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_RAM_ID,
158  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_INJECT_TYPE,
159  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_ECC_TYPE }, // 28 - Interconnect Type
160  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_RAM_ID,
161  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_INJECT_TYPE,
162  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_ECC_TYPE }, // 29 - Interconnect Type
163  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_RAM_ID,
164  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_INJECT_TYPE,
165  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_ECC_TYPE }, // 30 - Interconnect Type
166  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_RAM_ID,
167  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_INJECT_TYPE,
168  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_ECC_TYPE }, // 31 - Interconnect Type
169  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_RAM_ID,
170  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_INJECT_TYPE,
171  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_ECC_TYPE }, // 32 - Interconnect Type
172  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_RAM_ID,
173  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_INJECT_TYPE,
174  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_ECC_TYPE }, // 33 - Interconnect Type
175  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_RAM_ID,
176  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_INJECT_TYPE,
177  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_ECC_TYPE }, // 34 - Interconnect Type
178  { SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_RAM_ID,
179  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
180  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_ECC_TYPE }, // 35 - Interconnect Type
181 };
182 
188 /* NOTE: For VIM RAM Id, with a 32 bit vector, the 2 LSB bits are not used.
189 ECC is done only on 30 bits. But need to add a correction of 2 to get the address
190 calculation to be right */
191 #define SDL_ECC_VIM_RAM_ID_WIDTH_CORRECTION (2U)
192 
193 const SDL_MemConfig_t SDL_ECC_mcuArmssMemEntries[SDL_PULSAR_CPU_WRAPPER_RAM_IDS_TOTAL_ENTRIES] =
194 {
195  {SDL_ECC_R5F_MEM_SUBTYPE_ITAG_RAM0_VECTOR_ID, 0u,
196  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
197  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
198  {SDL_ECC_R5F_MEM_SUBTYPE_ITAG_RAM1_VECTOR_ID, 0u,
199  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
200  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
201  {SDL_ECC_R5F_MEM_SUBTYPE_ITAG_RAM2_VECTOR_ID, 0u,
202  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
203  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
204  {SDL_ECC_R5F_MEM_SUBTYPE_ITAG_RAM3_VECTOR_ID, 0u,
205  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
206  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
207  {SDL_ECC_R5F_MEM_SUBTYPE_IDATA_BANK0_VECTOR_ID, 0u,
208  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 4u,
209  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)false) },
210  {SDL_ECC_R5F_MEM_SUBTYPE_IDATA_BANK1_VECTOR_ID, 0u,
211  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 4u,
212  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)false) },
213  {SDL_ECC_R5F_MEM_SUBTYPE_IDATA_BANK2_VECTOR_ID, 0u,
214  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 4u,
215  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)false) },
216  {SDL_ECC_R5F_MEM_SUBTYPE_IDATA_BANK3_VECTOR_ID, 0u,
217  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 4u,
218  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)false) },
219  {SDL_ECC_R5F_MEM_SUBTYPE_DTAG_RAM0_VECTOR_ID, 0u,
220  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
221  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
222  {SDL_ECC_R5F_MEM_SUBTYPE_DTAG_RAM1_VECTOR_ID, 0u,
223  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
224  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
225  {SDL_ECC_R5F_MEM_SUBTYPE_DTAG_RAM2_VECTOR_ID, 0u,
226  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
227  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
228  {SDL_ECC_R5F_MEM_SUBTYPE_DTAG_RAM3_VECTOR_ID, 0u,
229  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
230  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
231  {SDL_ECC_R5F_MEM_SUBTYPE_DDIRTY_RAM_VECTOR_ID, 0u,
232  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
233  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
234  {SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM0_VECTOR_ID, 0u,
235  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
236  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)false) },
237  {SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM1_VECTOR_ID, 0u,
238  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
239  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)false) },
240  {SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM2_VECTOR_ID, 0u,
241  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
242  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)false) },
243  {SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM3_VECTOR_ID, 0u,
244  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
245  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)false) },
246  {SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM4_VECTOR_ID,0u,
247  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
248  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)false) },
249  {SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM5_VECTOR_ID, 0u,
250  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
251  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)false) },
252  {SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM6_VECTOR_ID, 0u,
253  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
254  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)false) },
255  {SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM7_VECTOR_ID, 0u,
256  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
257  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)false) },
258  {SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK0_VECTOR_ID, 0u,
259  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_SIZE, 8u,
260  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ROW_WIDTH, ((bool)true) },
261  {SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK1_VECTOR_ID, 0x4u,
262  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_SIZE, 8u,
263  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ROW_WIDTH, ((bool)true) },
264  {SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK0_VECTOR_ID, 0x41010000u,
265  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_SIZE, 16u,
266  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ROW_WIDTH, ((bool)true) },
267  {SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK1_VECTOR_ID, 0x41010004u,
268  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_SIZE, 16u,
269  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ROW_WIDTH, ((bool)true) },
270  {SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK0_VECTOR_ID, 0x41010008u,
271  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_SIZE, 16u,
272  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ROW_WIDTH, ((bool)true) },
273  {SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK1_VECTOR_ID, 0x4101000cu,
274  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_SIZE, 16u,
275  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ROW_WIDTH, ((bool)true) },
276  /* NOTE: VIM width and size needs correction: see note above */
277  {SDL_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID, 0x40f82000u,
278  ((SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_SIZE
279  *(SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH
280  +SDL_ECC_VIM_RAM_ID_WIDTH_CORRECTION))
281  /SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH),
282  4u,
283  (SDL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH+SDL_ECC_VIM_RAM_ID_WIDTH_CORRECTION), ((bool)true) },
284 };
285 
286 /* Max entries based on max mem type */
287 #define SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES (SDL_ECC_MEMTYPE_MCU_CBASS_ECC_AGGR0+1u)
288 
289 #define SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES (SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR2 - \
290  SDL_ECC_MEMTYPE_MAIN_MSMC_AGGR0 + 1u)
291 
292 /* Max entries based on max mem type */
293 #define SDL_ECC_AGGREGATOR_MAX_ENTRIES (SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES + \
294  SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES)
295 
300 SDL_ecc_aggrRegs * const SDL_ECC_aggrBaseAddressTable[SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES] =
301 {
302  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_R5FSS0_CORE0_ECC_AGGR_BASE)),
303  ((SDL_ecc_aggrRegs *)((uintptr_t)0U)),
304  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_ADC0_ECC_REGS_BASE)),
305  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_ADC1_ECC_REGS_BASE)),
306  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_CPSW0_ECC_BASE)),
307  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_FSS0_HPB_ECC_AGGR_BASE)),
308  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_FSS0_OSPI0_ECC_AGGR_BASE)),
309  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_FSS0_OSPI1_ECC_AGGR_BASE)),
310  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_MCAN0_ECC_AGGR_BASE)),
311  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_MCAN1_ECC_AGGR_BASE)),
312  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_MSRAM_1MB0_ECC_AGGR_REGS_BASE)),
313  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_NAVSS0_ECCAGGR0_BASE)),
314  ((SDL_ecc_aggrRegs *)((uintptr_t)0U)),
315  ((SDL_ecc_aggrRegs *)((uintptr_t)0U)),
316  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_PSRAMECC0_ECC_AGGR_BASE)),
317  ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCU_CBASS_ECC_AGGR0_REGS_BASE)),
318 };
319 
320 /* Addresses will be cast to SDL_ecc_aggrRegs after RAT translation */
321 uint64_t const SDL_ECC_aggrHighBaseAddressTable[SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES] =
322 {
323  (uint64_t)SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_BASE,
324  (uint64_t)SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_BASE,
325  (uint64_t)SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_BASE,
326 };
327 
328 SDL_ecc_aggrRegs * SDL_ECC_aggrHighBaseAddressTableTrans[SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES];
329 
334 /* Note: While this table lists all the possible RAM ID's for the MSMC AGGR0, only the following
335  * 2 RAM ID's have been tested:
336  * SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_RAM_ID = 20 (Interconnect type)
337  * SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_RAM_ID = 100 (Wrapper type) */
338 const SDL_RAMIdEntry_t SDL_ECC_mainMsmcAggr0RamIdTable[SDL_MSMC_AGGR0_RAM_ID_TABLE_MAX_ENTRIES] =
339 {
340  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_RAM_ID,
341  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_INJECT_TYPE,
342  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EDC_CTRL_ECCAGGR0_ECC_TYPE }, // 0
343  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_RAM_ID,
344  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_INJECT_TYPE,
345  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SCR_EDC_ECC_TYPE }, // 1
346  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_RAM_ID,
347  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_INJECT_TYPE,
348  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_ECC_TYPE }, // 2
349  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_RAM_ID,
350  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_INJECT_TYPE,
351  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_ECC_TYPE }, // 3
352  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_RAM_ID,
353  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_INJECT_TYPE,
354  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_ECC_TYPE }, // 4
355  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_RAM_ID,
356  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_INJECT_TYPE,
357  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_ECC_TYPE }, // 5
358  { SDL_ECC_RAMID_INVALID,
359  SDL_ECC_INJECTTYPE_INVALID,
360  SDL_ECC_ECC_TYPE_INVALD }, // 6
361  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_CFG_EDC_RAM_ID,
362  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_CFG_EDC_INJECT_TYPE,
363  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_CFG_EDC_ECC_TYPE }, // 7
364  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_RAM_ID,
365  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_INJECT_TYPE,
366  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_ECC_TYPE }, // 8
367  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_RAM_ID,
368  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_INJECT_TYPE,
369  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_ECC_TYPE }, // 9
370  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_RAM_ID,
371  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_INJECT_TYPE,
372  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_ECC_TYPE }, // 10
373  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_RAM_ID,
374  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_INJECT_TYPE,
375  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_ECC_TYPE }, // 11
376  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_RAM_ID,
377  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_INJECT_TYPE,
378  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_ECC_TYPE }, // 12
379  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_RAM_ID,
380  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_INJECT_TYPE,
381  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_ECC_TYPE }, // 13
382  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_RAM_ID,
383  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_INJECT_TYPE,
384  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_ECC_TYPE }, // 14
385  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_RAM_ID,
386  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_INJECT_TYPE,
387  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_ECC_TYPE }, // 15
388  { SDL_ECC_RAMID_INVALID,
389  SDL_ECC_INJECTTYPE_INVALID,
390  SDL_ECC_ECC_TYPE_INVALD }, // 16
391  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_RAM_ID,
392  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_INJECT_TYPE,
393  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_ECC_TYPE }, // 17
394  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_RAM_ID,
395  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_INJECT_TYPE,
396  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_ECC_TYPE }, // 18
397  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_RAM_ID,
398  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_INJECT_TYPE,
399  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_ECC_TYPE }, // 19
400  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_RAM_ID,
401  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_INJECT_TYPE,
402  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_ECC_TYPE }, // 20
403  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_RAM_ID,
404  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_INJECT_TYPE,
405  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_ECC_TYPE }, // 21
406  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_RAM_ID,
407  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_INJECT_TYPE,
408  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_ECC_TYPE }, // 22
409  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_RAM_ID,
410  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_INJECT_TYPE,
411  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_ECC_TYPE }, // 23
412  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_RAM_ID,
413  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_INJECT_TYPE,
414  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_ECC_TYPE }, // 24
415  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_RAM_ID,
416  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_INJECT_TYPE,
417  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_ECC_TYPE }, // 25
418  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_RAM_ID,
419  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_INJECT_TYPE,
420  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_ECC_TYPE }, // 26
421  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_RAM_ID,
422  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_INJECT_TYPE,
423  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_ECC_TYPE }, // 27
424  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_RAM_ID,
425  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_INJECT_TYPE,
426  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_ECC_TYPE }, // 28
427  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_RAM_ID,
428  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_INJECT_TYPE,
429  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_ECC_TYPE }, // 29
430  { SDL_ECC_RAMID_INVALID,
431  SDL_ECC_INJECTTYPE_INVALID,
432  SDL_ECC_ECC_TYPE_INVALD }, // 30
433  { SDL_ECC_RAMID_INVALID,
434  SDL_ECC_INJECTTYPE_INVALID,
435  SDL_ECC_ECC_TYPE_INVALD }, // 31
436  { SDL_ECC_RAMID_INVALID,
437  SDL_ECC_INJECTTYPE_INVALID,
438  SDL_ECC_ECC_TYPE_INVALD }, // 32
439  { SDL_ECC_RAMID_INVALID,
440  SDL_ECC_INJECTTYPE_INVALID,
441  SDL_ECC_ECC_TYPE_INVALD }, // 33
442  { SDL_ECC_RAMID_INVALID,
443  SDL_ECC_INJECTTYPE_INVALID,
444  SDL_ECC_ECC_TYPE_INVALD }, // 34
445  { SDL_ECC_RAMID_INVALID,
446  SDL_ECC_INJECTTYPE_INVALID,
447  SDL_ECC_ECC_TYPE_INVALD }, // 35
448  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_RAM_ID,
449  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_INJECT_TYPE,
450  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_ECC_TYPE }, // 36
451  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_RAM_ID,
452  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_INJECT_TYPE,
453  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_ECC_TYPE }, // 37
454  { SDL_ECC_RAMID_INVALID,
455  SDL_ECC_INJECTTYPE_INVALID,
456  SDL_ECC_ECC_TYPE_INVALD }, // 38
457  { SDL_ECC_RAMID_INVALID,
458  SDL_ECC_INJECTTYPE_INVALID,
459  SDL_ECC_ECC_TYPE_INVALD }, // 39
460  { SDL_ECC_RAMID_INVALID,
461  SDL_ECC_INJECTTYPE_INVALID,
462  SDL_ECC_ECC_TYPE_INVALD }, // 40
463  { SDL_ECC_RAMID_INVALID,
464  SDL_ECC_INJECTTYPE_INVALID,
465  SDL_ECC_ECC_TYPE_INVALD }, // 41
466  { SDL_ECC_RAMID_INVALID,
467  SDL_ECC_INJECTTYPE_INVALID,
468  SDL_ECC_ECC_TYPE_INVALD }, // 42
469  { SDL_ECC_RAMID_INVALID,
470  SDL_ECC_INJECTTYPE_INVALID,
471  SDL_ECC_ECC_TYPE_INVALD }, // 43
472  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_RAM_ID,
473  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_INJECT_TYPE,
474  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_ECC_TYPE }, // 44
475  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_RAM_ID,
476  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_INJECT_TYPE,
477  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_ECC_TYPE }, // 45
478  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_RAM_ID,
479  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_INJECT_TYPE,
480  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_ECC_TYPE }, // 46
481  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_RAM_ID,
482  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_INJECT_TYPE,
483  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_ECC_TYPE }, // 47
484  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_RAM_ID,
485  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_INJECT_TYPE,
486  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_ECC_TYPE }, // 48
487  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_RAM_ID,
488  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_INJECT_TYPE,
489  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_ECC_TYPE }, // 49
490  { SDL_ECC_RAMID_INVALID,
491  SDL_ECC_INJECTTYPE_INVALID,
492  SDL_ECC_ECC_TYPE_INVALD }, // 50
493  { SDL_ECC_RAMID_INVALID,
494  SDL_ECC_INJECTTYPE_INVALID,
495  SDL_ECC_ECC_TYPE_INVALD }, // 51
496  { SDL_ECC_RAMID_INVALID,
497  SDL_ECC_INJECTTYPE_INVALID,
498  SDL_ECC_ECC_TYPE_INVALD }, // 52
499  { SDL_ECC_RAMID_INVALID,
500  SDL_ECC_INJECTTYPE_INVALID,
501  SDL_ECC_ECC_TYPE_INVALD }, // 53
502  { SDL_ECC_RAMID_INVALID,
503  SDL_ECC_INJECTTYPE_INVALID,
504  SDL_ECC_ECC_TYPE_INVALD }, // 54
505  { SDL_ECC_RAMID_INVALID,
506  SDL_ECC_INJECTTYPE_INVALID,
507  SDL_ECC_ECC_TYPE_INVALD }, // 55
508  { SDL_ECC_RAMID_INVALID,
509  SDL_ECC_INJECTTYPE_INVALID,
510  SDL_ECC_ECC_TYPE_INVALD }, // 56
511  { SDL_ECC_RAMID_INVALID,
512  SDL_ECC_INJECTTYPE_INVALID,
513  SDL_ECC_ECC_TYPE_INVALD }, // 57
514  { SDL_ECC_RAMID_INVALID,
515  SDL_ECC_INJECTTYPE_INVALID,
516  SDL_ECC_ECC_TYPE_INVALD }, // 58
517  { SDL_ECC_RAMID_INVALID,
518  SDL_ECC_INJECTTYPE_INVALID,
519  SDL_ECC_ECC_TYPE_INVALD }, // 59
520  { SDL_ECC_RAMID_INVALID,
521  SDL_ECC_INJECTTYPE_INVALID,
522  SDL_ECC_ECC_TYPE_INVALD }, // 60
523  { SDL_ECC_RAMID_INVALID,
524  SDL_ECC_INJECTTYPE_INVALID,
525  SDL_ECC_ECC_TYPE_INVALD }, // 61
526  { SDL_ECC_RAMID_INVALID,
527  SDL_ECC_INJECTTYPE_INVALID,
528  SDL_ECC_ECC_TYPE_INVALD }, // 62
529  { SDL_ECC_RAMID_INVALID,
530  SDL_ECC_INJECTTYPE_INVALID,
531  SDL_ECC_ECC_TYPE_INVALD }, // 63
532  { SDL_ECC_RAMID_INVALID,
533  SDL_ECC_INJECTTYPE_INVALID,
534  SDL_ECC_ECC_TYPE_INVALD }, // 64
535  { SDL_ECC_RAMID_INVALID,
536  SDL_ECC_INJECTTYPE_INVALID,
537  SDL_ECC_ECC_TYPE_INVALD }, // 65
538  { SDL_ECC_RAMID_INVALID,
539  SDL_ECC_INJECTTYPE_INVALID,
540  SDL_ECC_ECC_TYPE_INVALD }, // 66
541  { SDL_ECC_RAMID_INVALID,
542  SDL_ECC_INJECTTYPE_INVALID,
543  SDL_ECC_ECC_TYPE_INVALD }, // 67
544  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_RAM_ID,
545  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_INJECT_TYPE,
546  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_ECC_TYPE }, // 68
547  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_RAM_ID,
548  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_INJECT_TYPE,
549  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_ECC_TYPE }, // 69
550  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_RAM_ID,
551  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_INJECT_TYPE,
552  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_ECC_TYPE }, // 70
553  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_RAM_ID,
554  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_INJECT_TYPE,
555  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_ECC_TYPE }, // 71
556  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_RAM_ID,
557  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_INJECT_TYPE,
558  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_ECC_TYPE }, // 72
559  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_RAM_ID,
560  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_INJECT_TYPE,
561  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_ECC_TYPE }, // 73
562  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_RAM_ID,
563  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_INJECT_TYPE,
564  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_ECC_TYPE }, // 74
565  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_RAM_ID,
566  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_INJECT_TYPE,
567  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_ECC_TYPE }, // 75
568  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_RAM_ID,
569  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_INJECT_TYPE,
570  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_ECC_TYPE }, // 76
571  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_RAM_ID,
572  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_INJECT_TYPE,
573  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_ECC_TYPE }, // 77
574  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_RAM_ID,
575  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_INJECT_TYPE,
576  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_ECC_TYPE }, // 78
577  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_RAM_ID,
578  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_INJECT_TYPE,
579  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_ECC_TYPE }, // 79
580  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_RAM_ID,
581  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_INJECT_TYPE,
582  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_ECC_TYPE }, // 80
583  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_RAM_ID,
584  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_INJECT_TYPE,
585  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_ECC_TYPE }, // 81
586  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_RAM_ID,
587  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_INJECT_TYPE,
588  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_ECC_TYPE }, // 82
589  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_RAM_ID,
590  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_INJECT_TYPE,
591  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_ECC_TYPE }, // 83
592  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_RAM_ID,
593  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_INJECT_TYPE,
594  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_ECC_TYPE }, // 84
595  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_RAM_ID,
596  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_INJECT_TYPE,
597  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_ECC_TYPE }, // 85
598  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_RAM_ID,
599  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_INJECT_TYPE,
600  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_ECC_TYPE }, // 86
601  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_RAM_ID,
602  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_INJECT_TYPE,
603  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_ECC_TYPE }, // 87
604  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_RAM_ID,
605  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_INJECT_TYPE,
606  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_ECC_TYPE }, // 88
607  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_RAM_ID,
608  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_INJECT_TYPE,
609  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_ECC_TYPE }, // 89
610  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_RAM_ID,
611  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_INJECT_TYPE,
612  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_ECC_TYPE }, // 90
613  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_RAM_ID,
614  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_INJECT_TYPE,
615  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_ECC_TYPE }, // 91
616  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_RAM_ID,
617  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_INJECT_TYPE,
618  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_ECC_TYPE }, // 92
619  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_RAM_ID,
620  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_INJECT_TYPE,
621  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_ECC_TYPE }, // 93
622  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_RAM_ID,
623  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_INJECT_TYPE,
624  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_ECC_TYPE }, // 94
625  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_RAM_ID,
626  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_INJECT_TYPE,
627  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_ECC_TYPE }, // 95
628  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_RAM_ID,
629  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_INJECT_TYPE,
630  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_ECC_TYPE }, // 96
631  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_RAM_ID,
632  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_INJECT_TYPE,
633  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_ECC_TYPE }, // 97
634  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_RAM_ID,
635  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_INJECT_TYPE,
636  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_ECC_TYPE }, // 98
637  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_RAM_ID,
638  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_INJECT_TYPE,
639  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_ECC_TYPE }, // 99
640  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_RAM_ID,
641  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_INJECT_TYPE,
642  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_ECC_TYPE }, // 100
643  { SDL_ECC_RAMID_INVALID,
644  SDL_ECC_INJECTTYPE_INVALID,
645  SDL_ECC_ECC_TYPE_INVALD }, // 101
646  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_RAM_ID,
647  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
648  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE }, // 102
649  { SDL_ECC_RAMID_INVALID,
650  SDL_ECC_INJECTTYPE_INVALID,
651  SDL_ECC_ECC_TYPE_INVALD }, // 103
652  { SDL_ECC_RAMID_INVALID,
653  SDL_ECC_INJECTTYPE_INVALID,
654  SDL_ECC_ECC_TYPE_INVALD }, // 104
655  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_RAM_ID,
656  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_INJECT_TYPE,
657  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_ECC_TYPE }, // 105
658  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_RAM_ID,
659  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_INJECT_TYPE,
660  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_ECC_TYPE }, // 106
661  { SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_RAM_ID,
662  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_INJECT_TYPE,
663  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_ECC_TYPE }, // 107
664 };
665 
666 const SDL_RAMIdEntry_t SDL_ECC_mcuEccAggr0RamIdTable[SDL_MSMC_AGGR0_RAM_ID_TABLE_MAX_ENTRIES] =
667 {
668  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_RAM_ID,
669  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_INJECT_TYPE,
670  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_ECC_TYPE }, // 0 - Wrapper Type
671  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_RAM_ID,
672  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_INJECT_TYPE,
673  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_ECC_TYPE }, // 1 - Wrapper Type
674  { SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_RAM_ID,
675  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_INJECT_TYPE,
676  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_ECC_TYPE }, // 2 - Interconnect Type
677 };
678 
683 const SDL_MemConfig_t SDL_ECC_mainMsmcAggr0MemEntries[SDL_MSMC_AGGR0_WRAPPER_RAM_IDS_TOTAL_ENTRIES] =
684 {
685  {SDL_ECC_MAIN_MSMC_MEM_WRAPPER_SUBTYPE, 0u,
686  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_RAM_SIZE, 4u,
687  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_ROW_WIDTH, ((bool)false) },
688 };
689 
694 const SDL_MemConfig_t SDL_ECC_MCUCBASSMemEntries[SDL_MCU_CBASS_WRAPPER_RAM_IDS_TOTAL_ENTRIES] =
695 {
696  {SDL_ECC_MCU_CBASS_MEM_SUBTYPE_WR_RAMECC_ID, 0u,
697  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_RAM_SIZE, 4u, ((bool)false) },
698  {SDL_ECC_MCU_CBASS_MEM_SUBTYPE_RD_RAMECC_ID, 0u,
699  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_RAM_SIZE, 4u, ((bool)false) },
700 };
701 
707 const SDL_GrpChkConfig_t SDL_ECC_ramIdVbusM2AxiEdcVectorGrpEntries[SDL_PULSAR_CPU_RAM_ID_VBUSM2_AXI_EDC_VECTOR_GRP_MAX_ENTRIES] =
708 {
709  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_0_CHECKER_TYPE,
710  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_0_WIDTH},
711  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_1_CHECKER_TYPE,
712  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_1_WIDTH},
713  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_2_CHECKER_TYPE,
714  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_2_WIDTH},
715  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_3_CHECKER_TYPE,
716  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_3_WIDTH},
717  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_4_CHECKER_TYPE,
718  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_4_WIDTH},
719  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_5_CHECKER_TYPE,
720  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_5_WIDTH},
721  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_6_CHECKER_TYPE,
722  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_6_WIDTH},
723  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_7_CHECKER_TYPE,
724  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_7_WIDTH},
725  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_8_CHECKER_TYPE,
726  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_8_WIDTH},
727  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_9_CHECKER_TYPE,
728  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_9_WIDTH},
729  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_10_CHECKER_TYPE,
730  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_10_WIDTH},
731  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_11_CHECKER_TYPE,
732  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_11_WIDTH},
733  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_12_CHECKER_TYPE,
734  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_12_WIDTH},
735  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_13_CHECKER_TYPE,
736  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_13_WIDTH},
737  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_14_CHECKER_TYPE,
738  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_14_WIDTH},
739  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_15_CHECKER_TYPE,
740  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_15_WIDTH},
741  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_16_CHECKER_TYPE,
742  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_16_WIDTH},
743  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_17_CHECKER_TYPE,
744  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_17_WIDTH},
745  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_18_CHECKER_TYPE,
746  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_18_WIDTH},
747  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_19_CHECKER_TYPE,
748  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_19_WIDTH},
749  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_20_CHECKER_TYPE,
750  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_20_WIDTH},
751  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_21_CHECKER_TYPE,
752  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_21_WIDTH},
753  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_22_CHECKER_TYPE,
754  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_22_WIDTH},
755  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_23_CHECKER_TYPE,
756  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_23_WIDTH},
757  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_24_CHECKER_TYPE,
758  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_24_WIDTH},
759  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_25_CHECKER_TYPE,
760  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_25_WIDTH},
761  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_26_CHECKER_TYPE,
762  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_26_WIDTH},
763  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_27_CHECKER_TYPE,
764  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_27_WIDTH},
765  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_28_CHECKER_TYPE,
766  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_28_WIDTH},
767  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_29_CHECKER_TYPE,
768  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_29_WIDTH},
769  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_30_CHECKER_TYPE,
770  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_30_WIDTH},
771  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_31_CHECKER_TYPE,
772  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_31_WIDTH},
773  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_32_CHECKER_TYPE,
774  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_32_WIDTH},
775  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_33_CHECKER_TYPE,
776  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_33_WIDTH},
777  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_34_CHECKER_TYPE,
778  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_34_WIDTH},
779  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_35_CHECKER_TYPE,
780  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_35_WIDTH},
781  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_36_CHECKER_TYPE,
782  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_36_WIDTH},
783  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_37_CHECKER_TYPE,
784  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_37_WIDTH},
785  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_38_CHECKER_TYPE,
786  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_38_WIDTH},
787  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_39_CHECKER_TYPE,
788  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_39_WIDTH},
789  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_40_CHECKER_TYPE,
790  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_40_WIDTH},
791  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_41_CHECKER_TYPE,
792  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_41_WIDTH},
793  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_42_CHECKER_TYPE,
794  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_42_WIDTH},
795  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_43_CHECKER_TYPE,
796  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_43_WIDTH},
797  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_44_CHECKER_TYPE,
798  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_44_WIDTH},
799  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_45_CHECKER_TYPE,
800  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_45_WIDTH},
801  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_46_CHECKER_TYPE,
802  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_46_WIDTH},
803  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_47_CHECKER_TYPE,
804  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_47_WIDTH},
805  {SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_48_CHECKER_TYPE,
806  SDL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_GROUP_48_WIDTH},
807 };
808 
814 const SDL_GrpChkConfig_t SDL_ECC_ramIdMsmcMMRBuseccGrpEntries[SDL_MSMC_AGGR0_RAM_ID_MSMC_MMR_BUSECC_GRP_MAX_ENTRIES] =
815 {
816  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_0_CHECKER_TYPE,
817  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_0_WIDTH},
818  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_1_CHECKER_TYPE,
819  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_1_WIDTH},
820  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_2_CHECKER_TYPE,
821  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_2_WIDTH},
822  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_3_CHECKER_TYPE,
823  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_3_WIDTH},
824  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_4_CHECKER_TYPE,
825  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_4_WIDTH},
826  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_5_CHECKER_TYPE,
827  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_5_WIDTH},
828  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_6_CHECKER_TYPE,
829  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_6_WIDTH},
830  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_7_CHECKER_TYPE,
831  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_7_WIDTH},
832  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_8_CHECKER_TYPE,
833  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_8_WIDTH},
834  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_9_CHECKER_TYPE,
835  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_9_WIDTH},
836  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_10_CHECKER_TYPE,
837  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_10_WIDTH},
838  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_11_CHECKER_TYPE,
839  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_11_WIDTH},
840  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_12_CHECKER_TYPE,
841  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_12_WIDTH},
842  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_13_CHECKER_TYPE,
843  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_13_WIDTH},
844  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_14_CHECKER_TYPE,
845  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_14_WIDTH},
846  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_15_CHECKER_TYPE,
847  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_15_WIDTH},
848  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_16_CHECKER_TYPE,
849  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_16_WIDTH},
850  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_17_CHECKER_TYPE,
851  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_17_WIDTH},
852  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_18_CHECKER_TYPE,
853  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_18_WIDTH},
854  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_19_CHECKER_TYPE,
855  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_19_WIDTH},
856  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_20_CHECKER_TYPE,
857  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_20_WIDTH},
858  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_21_CHECKER_TYPE,
859  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_21_WIDTH},
860  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_22_CHECKER_TYPE,
861  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_22_WIDTH},
862  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_23_CHECKER_TYPE,
863  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_23_WIDTH},
864  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_24_CHECKER_TYPE,
865  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_24_WIDTH},
866  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_25_CHECKER_TYPE,
867  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_25_WIDTH},
868  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_26_CHECKER_TYPE,
869  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_26_WIDTH},
870  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_27_CHECKER_TYPE,
871  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_27_WIDTH},
872  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_28_CHECKER_TYPE,
873  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_28_WIDTH},
874  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_29_CHECKER_TYPE,
875  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_29_WIDTH},
876  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_30_CHECKER_TYPE,
877  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_30_WIDTH},
878  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_31_CHECKER_TYPE,
879  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_31_WIDTH},
880  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_32_CHECKER_TYPE,
881  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_32_WIDTH},
882  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_33_CHECKER_TYPE,
883  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_GROUP_33_WIDTH},
884 };
885 
891 const SDL_GrpChkConfig_t SDL_ECC_ramIdMsmccachetagMemGrpEntries[SDL_MSMC_AGGR0_CACHE_TAG_MEM_INTERCONN_SUBTYPEGRP_MAX_ENTRIES] =
892 {
893  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_0_CHECKER_TYPE,
894  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_0_WIDTH},
895  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_1_CHECKER_TYPE,
896  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_1_WIDTH},
897  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_2_CHECKER_TYPE,
898  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_2_WIDTH},
899  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_3_CHECKER_TYPE,
900  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_3_WIDTH},
901  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_4_CHECKER_TYPE,
902  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_4_WIDTH},
903  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_5_CHECKER_TYPE,
904  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_5_WIDTH},
905  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_6_CHECKER_TYPE,
906  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_6_WIDTH},
907  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_7_CHECKER_TYPE,
908  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_7_WIDTH},
909  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_8_CHECKER_TYPE,
910  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_8_WIDTH},
911  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_9_CHECKER_TYPE,
912  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_9_WIDTH},
913  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_10_CHECKER_TYPE,
914  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_10_WIDTH},
915  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_11_CHECKER_TYPE,
916  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_11_WIDTH},
917  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_12_CHECKER_TYPE,
918  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_12_WIDTH},
919  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_13_CHECKER_TYPE,
920  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_13_WIDTH},
921  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_14_CHECKER_TYPE,
922  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_14_WIDTH},
923  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_15_CHECKER_TYPE,
924  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_15_WIDTH},
925  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_16_CHECKER_TYPE,
926  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_16_WIDTH},
927  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_17_CHECKER_TYPE,
928  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_17_WIDTH},
929  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_18_CHECKER_TYPE,
930  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_18_WIDTH},
931  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_19_CHECKER_TYPE,
932  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_19_WIDTH},
933  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_20_CHECKER_TYPE,
934  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_20_WIDTH},
935  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_21_CHECKER_TYPE,
936  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_21_WIDTH},
937  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_22_CHECKER_TYPE,
938  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_22_WIDTH},
939  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_23_CHECKER_TYPE,
940  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_23_WIDTH},
941  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_24_CHECKER_TYPE,
942  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_24_WIDTH},
943  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_25_CHECKER_TYPE,
944  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_25_WIDTH},
945  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_26_CHECKER_TYPE,
946  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_26_WIDTH},
947  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_27_CHECKER_TYPE,
948  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_27_WIDTH},
949  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_28_CHECKER_TYPE,
950  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_28_WIDTH},
951  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_29_CHECKER_TYPE,
952  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_29_WIDTH},
953  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_30_CHECKER_TYPE,
954  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_30_WIDTH},
955  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_31_CHECKER_TYPE,
956  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_31_WIDTH},
957  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_32_CHECKER_TYPE,
958  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_32_WIDTH},
959  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_33_CHECKER_TYPE,
960  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_33_WIDTH},
961  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_34_CHECKER_TYPE,
962  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_34_WIDTH},
963  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_35_CHECKER_TYPE,
964  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_35_WIDTH},
965  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_36_CHECKER_TYPE,
966  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_36_WIDTH},
967  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_37_CHECKER_TYPE,
968  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_37_WIDTH},
969  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_38_CHECKER_TYPE,
970  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_38_WIDTH},
971  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_39_CHECKER_TYPE,
972  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_39_WIDTH},
973  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_40_CHECKER_TYPE,
974  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_40_WIDTH},
975  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_41_CHECKER_TYPE,
976  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_41_WIDTH},
977  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_42_CHECKER_TYPE,
978  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_42_WIDTH},
979  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_43_CHECKER_TYPE,
980  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_43_WIDTH},
981  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_44_CHECKER_TYPE,
982  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_44_WIDTH},
983  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_45_CHECKER_TYPE,
984  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_45_WIDTH},
985  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_46_CHECKER_TYPE,
986  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_46_WIDTH},
987  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_47_CHECKER_TYPE,
988  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_GROUP_47_WIDTH},
989 };
990 
996 const SDL_GrpChkConfig_t SDL_ECC_ramIdMsmcClecMemGrpEntries[SDL_MSMC_AGGR0_CLEC_EDC_CTRL_BUSECC_INTERCONN_SUBTYPEGRP_MAX_ENTRIES] =
997 {
998  {SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
999  SDL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_GROUP_0_WIDTH},
1000 };
1001 
1002 /* NOTE: Checkers information is not available currently for MCU CBASS ECC aggregator in SDLR.
1003  This is a table added to demonstrate functionality and local defines are used */
1004 
1005 #define SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_GROUP_0_CHECKER_TYPE SDL_ECC_AGGR_CHECKER_TYPE_REDUNDANT
1006 #define SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_GROUP_0_WIDTH (6U)
1007 
1008 #define SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_MAX_NUM_CHECKERS (1U)
1009 
1010 #define SDL_MCU_CBASS_ECC_AGGR_IMCU_COR_FW_GRP_MAX_ENTRIES \
1011  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_MAX_NUM_CHECKERS
1012 
1013 const SDL_GrpChkConfig_t SDL_ECC_MCU_CBASS_ramId2GrpEntries[SDL_MCU_CBASS_ECC_AGGR_IMCU_COR_FW_GRP_MAX_ENTRIES] =
1014 {
1015  {SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_GROUP_0_CHECKER_TYPE,
1016  SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_GROUP_0_WIDTH },
1017 };
1018 
1019 #endif /* INCLUDE_SDL_ECC_SOC_H_ */
SDL_ECC_R5F_MEM_SUBTYPE_ITAG_RAM1_VECTOR_ID
#define SDL_ECC_R5F_MEM_SUBTYPE_ITAG_RAM1_VECTOR_ID
Select memory subtype ITAG RAM1.
Definition: sdl_ecc.h:218
SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK1_VECTOR_ID
#define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK1_VECTOR_ID
Select memory subtype B1TCM0 BANK1.
Definition: sdl_ecc.h:268
SDL_ECC_R5F_MEM_SUBTYPE_DTAG_RAM1_VECTOR_ID
#define SDL_ECC_R5F_MEM_SUBTYPE_DTAG_RAM1_VECTOR_ID
Select memory subtype DTAG RAM1.
Definition: sdl_ecc.h:234
SDL_ECC_ramIdVbusM2AxiEdcVectorGrpEntries
const SDL_GrpChkConfig_t SDL_ECC_ramIdVbusM2AxiEdcVectorGrpEntries[SDL_PULSAR_CPU_RAM_ID_VBUSM2_AXI_EDC_VECTOR_GRP_MAX_ENTRIES]
This structure holds the ECC interconnect Group Checker information for.
Definition: sdl_ecc_soc.h:707
SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM4_VECTOR_ID
#define SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM4_VECTOR_ID
Select memory subtype DDATA RAM4.
Definition: sdl_ecc.h:250
SDL_ECC_R5F_MEM_SUBTYPE_DTAG_RAM2_VECTOR_ID
#define SDL_ECC_R5F_MEM_SUBTYPE_DTAG_RAM2_VECTOR_ID
Select memory subtype DTAG RAM2.
Definition: sdl_ecc.h:236
SDL_PULSAR_CPU_WRAPPER_RAM_IDS_TOTAL_ENTRIES
#define SDL_PULSAR_CPU_WRAPPER_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:55
SDL_ECC_R5F_MEM_SUBTYPE_IDATA_BANK3_VECTOR_ID
#define SDL_ECC_R5F_MEM_SUBTYPE_IDATA_BANK3_VECTOR_ID
Select memory subtype IDATA BANK3.
Definition: sdl_ecc.h:230
SDL_ECC_R5F_MEM_SUBTYPE_DDIRTY_RAM_VECTOR_ID
#define SDL_ECC_R5F_MEM_SUBTYPE_DDIRTY_RAM_VECTOR_ID
Select memory subtype DDIRTY RAM.
Definition: sdl_ecc.h:240
SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK1_VECTOR_ID
#define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK1_VECTOR_ID
Select memory subtype B0TCM0 BANK1.
Definition: sdl_ecc.h:264
SDL_ECC_aggrBaseAddressTable
SDL_ecc_aggrRegs *const SDL_ECC_aggrBaseAddressTable[SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES]
This structure holds the base addresses for each memory subtype in MCU domain
Definition: sdl_ecc_soc.h:300
SDL_ECC_R5F_MEM_SUBTYPE_ITAG_RAM0_VECTOR_ID
#define SDL_ECC_R5F_MEM_SUBTYPE_ITAG_RAM0_VECTOR_ID
Select memory subtype ITAG RAM0.
Definition: sdl_ecc.h:216
SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_GROUP_0_CHECKER_TYPE
#define SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_GROUP_0_CHECKER_TYPE
Definition: sdl_ecc_soc.h:1005
SDL_ECC_R5F_MEM_SUBTYPE_ITAG_RAM3_VECTOR_ID
#define SDL_ECC_R5F_MEM_SUBTYPE_ITAG_RAM3_VECTOR_ID
Select memory subtype ITAG RAM3.
Definition: sdl_ecc.h:222
SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM7_VECTOR_ID
#define SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM7_VECTOR_ID
Select memory subtype DDATA RAM7.
Definition: sdl_ecc.h:256
SDL_ECC_R5F_MEM_SUBTYPE_ITAG_RAM2_VECTOR_ID
#define SDL_ECC_R5F_MEM_SUBTYPE_ITAG_RAM2_VECTOR_ID
Select memory subtype ITAG RAM2.
Definition: sdl_ecc.h:220
SDL_ECC_R5F_MEM_SUBTYPE_IDATA_BANK2_VECTOR_ID
#define SDL_ECC_R5F_MEM_SUBTYPE_IDATA_BANK2_VECTOR_ID
Select memory subtype IDATA BANK2.
Definition: sdl_ecc.h:228
SDL_MSMC_AGGR0_CACHE_TAG_MEM_INTERCONN_SUBTYPEGRP_MAX_ENTRIES
#define SDL_MSMC_AGGR0_CACHE_TAG_MEM_INTERCONN_SUBTYPEGRP_MAX_ENTRIES
Definition: sdl_ecc_soc.h:63
SDL_ECC_mainMsmcAggr0MemEntries
const SDL_MemConfig_t SDL_ECC_mainMsmcAggr0MemEntries[SDL_MSMC_AGGR0_WRAPPER_RAM_IDS_TOTAL_ENTRIES]
This structure holds the memory config for each memory subtype in MCU domain
Definition: sdl_ecc_soc.h:683
SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM5_VECTOR_ID
#define SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM5_VECTOR_ID
Select memory subtype DDATA RAM5.
Definition: sdl_ecc.h:252
SDL_ECC_VIM_RAM_ID_WIDTH_CORRECTION
#define SDL_ECC_VIM_RAM_ID_WIDTH_CORRECTION
This structure holds the memory config for each memory subtype in MCU domain
Definition: sdl_ecc_soc.h:191
SDL_ECC_MCUCBASSMemEntries
const SDL_MemConfig_t SDL_ECC_MCUCBASSMemEntries[SDL_MCU_CBASS_WRAPPER_RAM_IDS_TOTAL_ENTRIES]
This structure holds the memory config for each memory subtype in MCU CBASS
Definition: sdl_ecc_soc.h:694
SDL_ECC_R5F_MEM_SUBTYPE_IDATA_BANK1_VECTOR_ID
#define SDL_ECC_R5F_MEM_SUBTYPE_IDATA_BANK1_VECTOR_ID
Select memory subtype IDATA BANK1.
Definition: sdl_ecc.h:226
SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES
#define SDL_ECC_AGGREGATOR_MAX_LOW_ENTRIES
Definition: sdl_ecc_soc.h:287
SDL_ECC_mcuEccAggr0RamIdTable
const SDL_RAMIdEntry_t SDL_ECC_mcuEccAggr0RamIdTable[SDL_MSMC_AGGR0_RAM_ID_TABLE_MAX_ENTRIES]
Definition: sdl_ecc_soc.h:666
SDL_ECC_R5F_MEM_SUBTYPE_DTAG_RAM3_VECTOR_ID
#define SDL_ECC_R5F_MEM_SUBTYPE_DTAG_RAM3_VECTOR_ID
Select memory subtype DTAG RAM3.
Definition: sdl_ecc.h:238
SDL_ECC_MCU_CBASS_MEM_SUBTYPE_WR_RAMECC_ID
#define SDL_ECC_MCU_CBASS_MEM_SUBTYPE_WR_RAMECC_ID
Select memory subtype write ramecc.
Definition: sdl_ecc.h:301
SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES
#define SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES
Definition: sdl_ecc_soc.h:289
SDL_ECC_mainMsmcAggr0RamIdTable
const SDL_RAMIdEntry_t SDL_ECC_mainMsmcAggr0RamIdTable[SDL_MSMC_AGGR0_RAM_ID_TABLE_MAX_ENTRIES]
This structure holds the list of Ram Ids for each memory subtype in MSMC AGGR0
Definition: sdl_ecc_soc.h:338
SDL_ECC_R5F_MEM_SUBTYPE_IDATA_BANK0_VECTOR_ID
#define SDL_ECC_R5F_MEM_SUBTYPE_IDATA_BANK0_VECTOR_ID
Select memory subtype IDATA BANK0.
Definition: sdl_ecc.h:224
SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM1_VECTOR_ID
#define SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM1_VECTOR_ID
Select memory subtype DDATA RAM1.
Definition: sdl_ecc.h:244
SDL_MSMC_AGGR0_RAM_ID_TABLE_MAX_ENTRIES
#define SDL_MSMC_AGGR0_RAM_ID_TABLE_MAX_ENTRIES
Definition: sdl_ecc_soc.h:50
SDL_MCU_CBASS_WRAPPER_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCU_CBASS_WRAPPER_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:57
SDL_ECC_ramIdMsmccachetagMemGrpEntries
const SDL_GrpChkConfig_t SDL_ECC_ramIdMsmccachetagMemGrpEntries[SDL_MSMC_AGGR0_CACHE_TAG_MEM_INTERCONN_SUBTYPEGRP_MAX_ENTRIES]
This structure holds the ECC interconnect Group Checker information for.
Definition: sdl_ecc_soc.h:891
SDL_ECC_aggrHighBaseAddressTableTrans
SDL_ecc_aggrRegs * SDL_ECC_aggrHighBaseAddressTableTrans[SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES]
Definition: sdl_ecc_soc.h:328
SDL_ECC_ramIdMsmcMMRBuseccGrpEntries
const SDL_GrpChkConfig_t SDL_ECC_ramIdMsmcMMRBuseccGrpEntries[SDL_MSMC_AGGR0_RAM_ID_MSMC_MMR_BUSECC_GRP_MAX_ENTRIES]
This structure holds the ECC interconnect Group Checker information for.
Definition: sdl_ecc_soc.h:814
SDL_MSMC_AGGR0_WRAPPER_RAM_IDS_TOTAL_ENTRIES
#define SDL_MSMC_AGGR0_WRAPPER_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:56
sdl_ecc.h
Header file contains enumerations, structure definitions and function.
SDL_MCU_CBASS_ECC_AGGR_IMCU_COR_FW_GRP_MAX_ENTRIES
#define SDL_MCU_CBASS_ECC_AGGR_IMCU_COR_FW_GRP_MAX_ENTRIES
Definition: sdl_ecc_soc.h:1010
SDL_ECC_MAIN_MSMC_MEM_WRAPPER_SUBTYPE
#define SDL_ECC_MAIN_MSMC_MEM_WRAPPER_SUBTYPE
Select memory subtype MSMC CLEC SRAM ECC.
Definition: sdl_ecc.h:293
SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM2_VECTOR_ID
#define SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM2_VECTOR_ID
Select memory subtype DDATA RAM2.
Definition: sdl_ecc.h:246
SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM6_VECTOR_ID
#define SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM6_VECTOR_ID
Select memory subtype DDATA RAM6.
Definition: sdl_ecc.h:254
SDL_PULSAR_CPU_RAM_ID_VBUSM2_AXI_EDC_VECTOR_GRP_MAX_ENTRIES
#define SDL_PULSAR_CPU_RAM_ID_VBUSM2_AXI_EDC_VECTOR_GRP_MAX_ENTRIES
Definition: sdl_ecc_soc.h:59
SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK1_VECTOR_ID
#define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK1_VECTOR_ID
Select memory subtype ATCM0 BANK1.
Definition: sdl_ecc.h:260
SDL_ECC_aggrHighBaseAddressTable
uint64_t const SDL_ECC_aggrHighBaseAddressTable[SDL_ECC_AGGREGATOR_MAX_HIGH_ENTRIES]
Definition: sdl_ecc_soc.h:321
SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM0_VECTOR_ID
#define SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM0_VECTOR_ID
Select memory subtype DDATA RAM0.
Definition: sdl_ecc.h:242
SDL_MSMC_AGGR0_RAM_ID_MSMC_MMR_BUSECC_GRP_MAX_ENTRIES
#define SDL_MSMC_AGGR0_RAM_ID_MSMC_MMR_BUSECC_GRP_MAX_ENTRIES
Definition: sdl_ecc_soc.h:61
SDL_ECC_MCU_CBASS_ramId2GrpEntries
const SDL_GrpChkConfig_t SDL_ECC_MCU_CBASS_ramId2GrpEntries[SDL_MCU_CBASS_ECC_AGGR_IMCU_COR_FW_GRP_MAX_ENTRIES]
Definition: sdl_ecc_soc.h:1013
soc.h
This file contains SOC specific defintions.
SDL_ecc_aggrRegs
Definition: sdlr_ecc.h:53
SDL_ECC_R5F_MEM_SUBTYPE_DTAG_RAM0_VECTOR_ID
#define SDL_ECC_R5F_MEM_SUBTYPE_DTAG_RAM0_VECTOR_ID
Select memory subtype DTAG RAM0.
Definition: sdl_ecc.h:232
SDL_ECC_mcuArmssMemEntries
const SDL_MemConfig_t SDL_ECC_mcuArmssMemEntries[SDL_PULSAR_CPU_WRAPPER_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:193
SDL_ECC_mcuArmssRamIdTable
const SDL_RAMIdEntry_t SDL_ECC_mcuArmssRamIdTable[SDL_PULSAR_CPU_RAM_ID_TABLE_MAX_ENTRIES]
This structure holds the list of Ram Ids for each memory subtype in MCU domain
Definition: sdl_ecc_soc.h:71
SDL_ECC_MCU_CBASS_MEM_SUBTYPE_RD_RAMECC_ID
#define SDL_ECC_MCU_CBASS_MEM_SUBTYPE_RD_RAMECC_ID
Select memory subtype read ramecc.
Definition: sdl_ecc.h:303
SDL_ECC_ramIdMsmcClecMemGrpEntries
const SDL_GrpChkConfig_t SDL_ECC_ramIdMsmcClecMemGrpEntries[SDL_MSMC_AGGR0_CLEC_EDC_CTRL_BUSECC_INTERCONN_SUBTYPEGRP_MAX_ENTRIES]
This structure holds the ECC interconnect Group Checker information for.
Definition: sdl_ecc_soc.h:996
SDL_MSMC_AGGR0_CLEC_EDC_CTRL_BUSECC_INTERCONN_SUBTYPEGRP_MAX_ENTRIES
#define SDL_MSMC_AGGR0_CLEC_EDC_CTRL_BUSECC_INTERCONN_SUBTYPEGRP_MAX_ENTRIES
Definition: sdl_ecc_soc.h:65
SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK0_VECTOR_ID
#define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK0_VECTOR_ID
Select memory subtype B1TCM0 BANK0.
Definition: sdl_ecc.h:266
SDL_PULSAR_CPU_RAM_ID_TABLE_MAX_ENTRIES
#define SDL_PULSAR_CPU_RAM_ID_TABLE_MAX_ENTRIES
Definition: sdl_ecc_soc.h:49
SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM3_VECTOR_ID
#define SDL_ECC_R5F_MEM_SUBTYPE_DDATA_RAM3_VECTOR_ID
Select memory subtype DDATA RAM3.
Definition: sdl_ecc.h:248
SDL_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID
#define SDL_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID
Select memory subtype VIM RAM.
Definition: sdl_ecc.h:270
SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_GROUP_0_WIDTH
#define SDL_MCU_CBASS_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_GROUP_0_WIDTH
Definition: sdl_ecc_soc.h:1006
SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK0_VECTOR_ID
#define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK0_VECTOR_ID
Select memory subtype B0TCM0 BANK0.
Definition: sdl_ecc.h:262
SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK0_VECTOR_ID
#define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK0_VECTOR_ID
Select memory subtype ATCM0 BANK0.
Definition: sdl_ecc.h:258