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PDK API Guide for J721E
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Functions | |
| void | CSL_CPSW_getCpswVersionInfo (CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_VERSION *pVersionInfo) |
| Uint32 | CSL_CPSW_isVlanAwareEnabled (CSL_Xge_cpswRegs *hCpswRegs) |
| void | CSL_CPSW_enableVlanAware (CSL_Xge_cpswRegs *hCpswRegs) |
| void | CSL_CPSW_setVlanType (CSL_Xge_cpswRegs *hCpswRegs, Uint32 vlanType) |
| void | CSL_CPSW_disableVlanAware (CSL_Xge_cpswRegs *hCpswRegs) |
| Uint32 | CSL_CPSW_isPort0Enabled (CSL_Xge_cpswRegs *hCpswRegs) |
| void | CSL_CPSW_enablePort0 (CSL_Xge_cpswRegs *hCpswRegs) |
| void | CSL_CPSW_disablePort0 (CSL_Xge_cpswRegs *hCpswRegs) |
| Uint32 | CSL_CPSW_isPort0PassPriTagEnabled (CSL_Xge_cpswRegs *hCpswRegs) |
| void | CSL_CPSW_enablePort0PassPriTag (CSL_Xge_cpswRegs *hCpswRegs) |
| void | CSL_CPSW_disablePort0PassPriTag (CSL_Xge_cpswRegs *hCpswRegs) |
| Uint32 | CSL_CPSW_isPort1PassPriTagEnabled (CSL_Xge_cpswRegs *hCpswRegs) |
| void | CSL_CPSW_enablePortPassPriTag (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
| void | CSL_CPSW_disablePortPassPriTag (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
| void | CSL_CPSW_getCpswControlReg (CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_CONTROL *pControlRegInfo) |
| void | CSL_CPSW_setCpswControlReg (CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_CONTROL *pControlRegInfo) |
| void | CSL_CPSW_getEmulationControlReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 *pFree, Uint32 *pSoft) |
| void | CSL_CPSW_setEmulationControlReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 free, Uint32 soft) |
| void | CSL_CPSW_getPortStatsEnableReg (CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_PORTSTAT *pPortStatsCfg) |
| void | CSL_CPSW_setPortStatsEnableReg (CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_PORTSTAT *pPortStatsCfg) |
| Uint32 | CSL_CPSW_isSoftIdle (CSL_Xge_cpswRegs *hCpswRegs) |
| void | CSL_CPSW_enableSoftIdle (CSL_Xge_cpswRegs *hCpswRegs) |
| void | CSL_CPSW_disableSoftIdle (CSL_Xge_cpswRegs *hCpswRegs) |
| void | CSL_CPSW_getPortControlReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_PORT_CONTROL *pControlInfo) |
| void | CSL_CPSW_setPortControlReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_PORT_CONTROL *pControlInfo) |
| void | CSL_CPSW_getCppiSourceIdReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 *pTxSrcId) |
| void | CSL_CPSW_setCppiSourceIdReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 *pTxSrcId) |
| void | CSL_CPSW_getPort0VlanReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 *pPortVID, Uint32 *pPortCFI, Uint32 *pPortPRI) |
| void | CSL_CPSW_setPort0VlanReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portVID, Uint32 portCFI, Uint32 portPRI) |
| void | CSL_CPSW_getPort0RxPriMapReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 *pPortRxPriMap) |
| void | CSL_CPSW_setPort0RxPriMapReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 *pPortRxPriMap) |
| Uint32 | CSL_CPSW_getPort0FlowIdOffset (CSL_Xge_cpswRegs *hCpswRegs) |
| void | CSL_CPSW_setPort0FlowIdOffset (CSL_Xge_cpswRegs *hCpswRegs, Uint32 flowIdOffset) |
| Uint32 | CSL_CPSW_getPort0RxMaxLen (CSL_Xge_cpswRegs *hCpswRegs) |
| void | CSL_CPSW_setPort0RxMaxLen (CSL_Xge_cpswRegs *hCpswRegs, Uint32 rxMaxLen) |
| void | CSL_CPSW_getPortBlockCountReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pRxBlkCnt_e, Uint32 *pRxBlkCnt_p, Uint32 *pTxBlkCnt) |
| Uint32 | CSL_CPSW_getPortRxMaxLen (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum) |
| void | CSL_CPSW_setPortRxMaxLen (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 rxMaxLen) |
| void | CSL_CPSW_getPortTxPriMapReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pPortTxPriMap) |
| void | CSL_CPSW_setPortTxPriMapReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pPortTxPriMap) |
| void | CSL_CPSW_getPortRxPriMapReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pPortRxPriMap) |
| void | CSL_CPSW_setPortRxPriMapReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pPortRxPriMap) |
| void | CSL_CPSW_getPortRxDscpMap (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pRxDscpPriMap) |
| void | CSL_CPSW_setPortRxDscpMap (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pRxDscpPriMap) |
| void | CSL_CPSW_getEEEGlobConfig (CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_EEE_GLOB_CONFIG *pGlobConfig) |
| void | CSL_CPSW_setEEEGlobConfig (CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_EEE_GLOB_CONFIG *pGlobConfig) |
| void | CSL_CPSW_getEEEPortConfig (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_EEE_PORT_CONFIG *pPortConfig) |
| void | CSL_CPSW_setEEEPortConfig (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_EEE_PORT_CONFIG *pPortConfig) |
| void | CSL_CPSW_EEEPortStatus (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_EEE_PORT_STATUS *pPortStatus) |
| void | CSL_CPSW_getPortVlanReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pPortVID, Uint32 *pPortCFI, Uint32 *pPortPRI) |
| void | CSL_CPSW_setPortVlanReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 portVID, Uint32 portCFI, Uint32 portPRI) |
| void | CSL_CPSW_getPortMaxBlksReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pRxMaxBlks, Uint32 *pTxMaxBlks) |
| void | CSL_CPSW_setPortMaxBlksReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 rxMaxBlks, Uint32 txMaxBlks) |
| void | CSL_CPSW_getPortMACAddress (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint8 *pMacAddress) |
| void | CSL_CPSW_setPortMACAddress (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint8 *pMacAddress) |
| void | CSL_CPSW_getPortTimeSyncCntlReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_TSCNTL *pTimeSyncCntlCfg) |
| void | CSL_CPSW_setPortTimeSyncCntlReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_TSCNTL *pTimeSyncCntlCfg) |
| void | CSL_CPSW_getPortTimeSyncSeqIdReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pTsLtype, Uint32 *pTsSeqIdOffset) |
| void | CSL_CPSW_getVlanLTypeReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 *pVlanLtypeInner, Uint32 *pVlanLtypeOuter) |
| void | CSL_CPSW_setVlanLTypeReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pVlanLtypeInner, Uint32 pVlanLtypeOuter) |
| void | CSL_CPSW_setPortTimeSyncSeqIdReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 tsLtype, Uint32 tsSeqIdOffset) |
| void | CSL_CPSW_getPortTimeSyncVlanLTypeReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 *pTsVlanLtype1, Uint32 *pTsVlanLtype2) |
| void | CSL_CPSW_setPortTimeSyncVlanLTypeReg (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, Uint32 tsVlanLtype1, Uint32 tsVlanLtype2) |
| void | CSL_CPSW_getPortTimeSyncConfig (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_TSCONFIG *pTimeSyncConfig) |
| void | CSL_CPSW_setPortTimeSyncConfig (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_TSCONFIG *pTimeSyncConfig) |
| void | CSL_CPSW_getStats (CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_STATS *pCpswStats) |
| void | CSL_CPSW_getPortStats (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_STATS *pCpswStats) |
| void | CSL_CPSW_getRawStats (CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_STATS *pCpswStats) |
| void | CSL_CPSW_getPortRawStats (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNum, CSL_CPSW_STATS *pCpswStats) |
| void | CSL_CPSW_getAleVersionInfo (CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_VERSION *pVersionInfo) |
| Uint32 | CSL_CPSW_isAleRateLimitEnabled (CSL_AleRegs *hCpswAleRegs) |
| void | CSL_CPSW_enableAleRateLimit (CSL_AleRegs *hCpswAleRegs) |
| void | CSL_CPSW_disableAleRateLimit (CSL_AleRegs *hCpswAleRegs) |
| Uint32 | CSL_CPSW_isAleMacAuthModeEnabled (CSL_AleRegs *hCpswAleRegs) |
| void | CSL_CPSW_enableAleMacAuthMode (CSL_AleRegs *hCpswAleRegs) |
| void | CSL_CPSW_disableAleMacAuthMode (CSL_AleRegs *hCpswAleRegs) |
| Uint32 | CSL_CPSW_isAleVlanAwareEnabled (CSL_AleRegs *hCpswAleRegs) |
| void | CSL_CPSW_enableAleVlanAware (CSL_AleRegs *hCpswAleRegs) |
| void | CSL_CPSW_disableAleVlanAware (CSL_AleRegs *hCpswAleRegs) |
| Uint32 | CSL_CPSW_isAleTxRateLimitEnabled (CSL_AleRegs *hCpswAleRegs) |
| void | CSL_CPSW_enableAleTxRateLimit (CSL_AleRegs *hCpswAleRegs) |
| void | CSL_CPSW_disableAleTxRateLimit (CSL_AleRegs *hCpswAleRegs) |
| Uint32 | CSL_CPSW_isAleBypassEnabled (CSL_AleRegs *hCpswAleRegs) |
| void | CSL_CPSW_enableAleBypass (CSL_AleRegs *hCpswAleRegs) |
| void | CSL_CPSW_disableAleBypass (CSL_AleRegs *hCpswAleRegs) |
| Uint32 | CSL_CPSW_isAleOUIDenyModeEnabled (CSL_AleRegs *hCpswAleRegs) |
| void | CSL_CPSW_enableAleOUIDenyMode (CSL_AleRegs *hCpswAleRegs) |
| void | CSL_CPSW_disableAleOUIDenyMode (CSL_AleRegs *hCpswAleRegs) |
| Uint32 | CSL_CPSW_isAleVID0ModeEnabled (CSL_AleRegs *hCpswAleRegs) |
| void | CSL_CPSW_enableAleVID0Mode (CSL_AleRegs *hCpswAleRegs) |
| void | CSL_CPSW_disableAleVID0Mode (CSL_AleRegs *hCpswAleRegs) |
| Uint32 | CSL_CPSW_isAleLearnNoVIDEnabled (CSL_AleRegs *hCpswAleRegs) |
| void | CSL_CPSW_enableAleLearnNoVID (CSL_AleRegs *hCpswAleRegs) |
| void | CSL_CPSW_disableAleLearnNoVID (CSL_AleRegs *hCpswAleRegs) |
| Uint32 | CSL_CPSW_isAleUUNIToHostEnabled (CSL_AleRegs *hCpswAleRegs) |
| void | CSL_CPSW_enableAleUUNIToHost (CSL_AleRegs *hCpswAleRegs) |
| void | CSL_CPSW_disableAleUUNIToHost (CSL_AleRegs *hCpswAleRegs) |
| Uint32 | CSL_CPSW_isAleUVLANNoLearnEnabled (CSL_AleRegs *hCpswAleRegs) |
| void | CSL_CPSW_enableAleUVLANNoLearn (CSL_AleRegs *hCpswAleRegs) |
| void | CSL_CPSW_disableAleUVLANNoLearn (CSL_AleRegs *hCpswAleRegs) |
| Uint32 | CSL_CPSW_getAleUpdateBW (CSL_AleRegs *hCpswAleRegs) |
| void | CSL_CPSW_setAleUpdateBW (CSL_AleRegs *hCpswAleRegs, Uint32 aleUpdBW) |
| void | CSL_CPSW_startAleAgeOutNow (CSL_AleRegs *hCpswAleRegs) |
| Uint32 | CSL_CPSW_isAleAgeOutDone (CSL_AleRegs *hCpswAleRegs) |
| void | CSL_CPSW_clearAleTable (CSL_AleRegs *hCpswAleRegs) |
| Uint32 | CSL_CPSW_isAleEnabled (CSL_AleRegs *hCpswAleRegs) |
| void | CSL_CPSW_enableAle (CSL_AleRegs *hCpswAleRegs) |
| void | CSL_CPSW_disableAle (CSL_AleRegs *hCpswAleRegs) |
| Uint32 | CSL_CPSW_getAleControlReg (CSL_AleRegs *hCpswAleRegs) |
| void | CSL_CPSW_setAleControlReg (CSL_AleRegs *hCpswAleRegs, Uint32 aleCtrlVal) |
| void | CSL_CPSW_getAleStatusReg (CSL_AleRegs *hCpswAleRegs, Uint32 *pNumPolicers, Uint32 *pNumEntries) |
| void | CSL_CPSW_getAleStatusNumAleEntries (CSL_AleRegs *hCpswAleRegs, Uint32 *pNumEntries) |
| CSL_CPSW_ALE_RAMDEPTH_E | CSL_CPSW_getAleStatusRamDepth (CSL_AleRegs *hCpswAleRegs) |
| void | CSL_CPSW_getAleStatusVlanMask (CSL_AleRegs *hCpswAleRegs, bool *vlanMsk08, bool *vlanMsk12) |
| Uint32 | CSL_CPSW_getAlePrescaleReg (CSL_AleRegs *hCpswAleRegs) |
| void | CSL_CPSW_setAlePrescaleReg (CSL_AleRegs *hCpswAleRegs, Uint32 alePrescaleVal) |
| void | CSL_CPSW_getAleAgingTimerReg (CSL_AleRegs *hCpswAleRegs, Uint32 *pAgingPrescale, Uint32 *pAgingPeriod) |
| void | CSL_CPSW_setAleAgingTimerReg (CSL_AleRegs *hCpswAleRegs, Uint32 agingPrescale, Uint32 agingPeriod) |
| void | CSL_CPSW_getAleUnkownVlanReg (CSL_AleRegs *hCpswAleRegs, Uint32 *pUnVlanMemList, Uint32 *pUnMcastFloodMask, Uint32 *pUnRegMcastFloodMask, Uint32 *pUnForceUntagEgress) |
| void | CSL_CPSW_setAleUnkownVlanReg (CSL_AleRegs *hCpswAleRegs, Uint32 unVlanMemList, Uint32 unMcastFloodMask, Uint32 unRegMcastFloodMask, Uint32 unForceUntagEgress) |
| void | CSL_CPSW_getAleVlanMaskMuxReg (CSL_AleRegs *hCpswAleRegs, Uint32 *vlanMaskMux) |
| void | CSL_CPSW_setAleVlanMaskMuxReg (CSL_AleRegs *hCpswAleRegs, Uint32 *vlanMaskMux) |
| void | CSL_CPSW_getAleVlanMaskMuxEntryReg (CSL_AleRegs *hCpswAleRegs, Uint32 maskMuxIndex, Uint32 *vlanMaskMuxPtr) |
| void | CSL_CPSW_setAleVlanMaskMuxEntryReg (CSL_AleRegs *hCpswAleRegs, Uint32 maskMuxIndex, Uint32 vlanMaskMuxVal) |
| void | CSL_CPSW_getAleTableEntry (CSL_AleRegs *hCpswAleRegs, Uint32 index, Uint32 *pAleInfoWd0, Uint32 *pAleInfoWd1, Uint32 *pAleInfoWd2) |
| void | CSL_CPSW_setAleTableEntry (CSL_AleRegs *hCpswAleRegs, Uint32 index, Uint32 aleInfoWd0, Uint32 aleInfoWd1, Uint32 aleInfoWd2) |
| CSL_CPSW_ALE_ENTRYTYPE | CSL_CPSW_getALEEntryType (CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALETABLE_TYPE aleType) |
| CSL_CPSW_ALE_ADDRTYPE | CSL_CPSW_getALEAddressType (CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALETABLE_TYPE aleType) |
| CSL_CPSW_ALE_POLICER_ENTRYTYPE | CSL_CPSW_getALEPolicerEntryType (CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALETABLE_TYPE aleType) |
| void | CSL_CPSW_getAleMcastAddrEntry (CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_MCASTADDR_ENTRY *pMcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType) |
| void | CSL_CPSW_setAleMcastAddrEntry (CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_MCASTADDR_ENTRY *pMcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType) |
| void | CSL_CPSW_getAleVlanMcastAddrEntry (CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_VLANMCASTADDR_ENTRY *pVlanMcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType) |
| void | CSL_CPSW_setAleVlanMcastAddrEntry (CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_VLANMCASTADDR_ENTRY *pVlanMcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType) |
| void | CSL_CPSW_getAleUnicastAddrEntry (CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_UNICASTADDR_ENTRY *pUcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType) |
| void | CSL_CPSW_setAleUnicastAddrEntry (CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_UNICASTADDR_ENTRY *pUcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType) |
| void | CSL_CPSW_getAleOUIAddrEntry (CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_OUIADDR_ENTRY *pOUIAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType) |
| void | CSL_CPSW_setAleOUIAddrEntry (CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_OUIADDR_ENTRY *pOUIAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType) |
| void | CSL_CPSW_getAleVlanUnicastAddrEntry (CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_VLANUNICASTADDR_ENTRY *pVlanUcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType) |
| void | CSL_CPSW_setAleVlanUnicastAddrEntry (CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_VLANUNICASTADDR_ENTRY *pVlanUcastAddrCfg, CSL_CPSW_ALETABLE_TYPE aleType) |
| void | CSL_CPSW_getAleVlanEntry (CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_VLAN_ENTRY *pVlanCfg, CSL_CPSW_ALETABLE_TYPE aleType) |
| void | CSL_CPSW_setAleVlanEntry (CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_VLAN_ENTRY *pVlanCfg, CSL_CPSW_ALETABLE_TYPE aleType) |
| void | CSL_CPSW_getAleOutVlanEntry (CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_OUTER_VLAN_ENTRY *pOutVlanCfg, CSL_CPSW_ALETABLE_TYPE aleType) |
| void | CSL_CPSW_setAleOutVlanEntry (CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_OUTER_VLAN_ENTRY *pOutVlanCfg, CSL_CPSW_ALETABLE_TYPE aleType) |
| void | CSL_CPSW_getAleEthertypeEntry (CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_ETHERTYPE_ENTRY *pEthertypeCfg, CSL_CPSW_ALETABLE_TYPE aleType) |
| void | CSL_CPSW_setAleEthertypeEntry (CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_ETHERTYPE_ENTRY *pEthertypeCfg, CSL_CPSW_ALETABLE_TYPE aleType) |
| void | CSL_CPSW_getAleIPv4Entry (CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_IPv4_ENTRY *pIPv4Cfg, CSL_CPSW_ALETABLE_TYPE aleType) |
| void | CSL_CPSW_setAleIPv4Entry (CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_IPv4_ENTRY *pIPv4Cfg, CSL_CPSW_ALETABLE_TYPE aleType) |
| Uint32 | CSL_CPSW_getAleIPv6HighEntryOffset (CSL_AleRegs *hCpswAleRegs) |
| Uint32 | CSL_CPSW_getAleIPv6HighEntryIndex (CSL_AleRegs *hCpswAleRegs, Uint32 entryIndex) |
| Uint32 | CSL_CPSW_getAleIPv6LowEntryIndex (CSL_AleRegs *hCpswAleRegs, Uint32 entryIndex) |
| void | CSL_CPSW_getAleIPv6Entry (CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_IPv6_ENTRY *pIPv6Cfg, CSL_CPSW_ALETABLE_TYPE aleType) |
| void | CSL_CPSW_setAleIPv6Entry (CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_IPv6_ENTRY *pIPv6Cfg, CSL_CPSW_ALETABLE_TYPE aleType) |
| void | CSL_CPSW_mapTableWord2MacAddr (uint32_t word0, uint32_t word1, uint8_t *macAddr, CSL_CPSW_ALETABLE_TYPE aleType) |
| void | CSL_CPSW_mapMacAddr2TableWord (uint32_t *word0, uint32_t *word1, uint8_t *macAddr, CSL_CPSW_ALETABLE_TYPE aleType) |
| Uint32 | CSL_CPSW_extractVid (Uint32 word1, CSL_CPSW_ALETABLE_TYPE aleType) |
| Uint32 | CSL_CPSW_getEthertypeMax (CSL_CPSW_ALETABLE_TYPE aleType) |
| Uint32 | CSL_CPSW_getIpv4IgnBitsMax (CSL_CPSW_ALETABLE_TYPE aleType) |
| Uint32 | CSL_CPSW_getIpv6IgnBitsMax (CSL_CPSW_ALETABLE_TYPE aleType) |
| void | CSL_CPSW_clearAleEntry (CSL_AleRegs *hCpswAleRegs, Uint32 index) |
| void | CSL_CPSW_getAlePortControlReg (CSL_AleRegs *hCpswAleRegs, Uint32 portNo, CSL_CPSW_ALE_PORTCONTROL *pPortControlInfo) |
| void | CSL_CPSW_setAlePortControlReg (CSL_AleRegs *hCpswAleRegs, Uint32 portNo, CSL_CPSW_ALE_PORTCONTROL *pPortControlInfo) |
| void | CSL_CPSW_setAlePortControlTrunk (CSL_AleRegs *hCpswAleRegs, Uint32 portNo, bool trunkEnable, Uint32 trunkNum) |
| void | CSL_CPSW_getAlePortState (CSL_AleRegs *hCpswAleRegs, Uint32 portNo, CSL_CPSW_ALE_PORTSTATE *pPortState) |
| void | CSL_CPSW_setAlePortState (CSL_AleRegs *hCpswAleRegs, Uint32 portNo, CSL_CPSW_ALE_PORTSTATE portState) |
| void | CSL_CPSW_setAlePortMirrorSouce (CSL_AleRegs *hCpswAleRegs, Uint32 portNo, bool enableMirror) |
| void | CSL_CPSW_setAleCtrl2MirrorMatchIndex (CSL_AleRegs *hCpswAleRegs, Uint32 mirrorMatchIndex) |
| void | CSL_CPSW_setAleCtrl2TrunkParams (CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_CTRL2_TRUNK_CONFIG *trunkCfg) |
| void | CSL_CPSW_setAleCtrl2IPPktFilterConfig (CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_CTRL2_IPPKTFLT_CONFIG *ipPktFltCfg) |
| void | CSL_CPSW_setAleCtrl2MalformedFrameConfig (CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_CTRL2_MALFORMEDFRAME_CONFIG *badFrmCfg) |
| void | CSL_CPSW_setAleIPNxtHdrWhitelist (CSL_AleRegs *hCpswAleRegs, Uint8 ipNxtHdr0, Uint8 ipNxtHdr1, Uint8 ipNxtHdr2, Uint8 ipNxtHdr3) |
| void | CSL_CPSW_getAlePolicerGlobConfig (CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_POLICER_GLOB_CONFIG *pGlobConfig) |
| void | CSL_CPSW_setAlePolicerGlobConfig (CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_POLICER_GLOB_CONFIG *pGlobConfig) |
| void | CSL_CPSW_getAlePolicerEntry (CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_POLICER_ENTRY *pPolCfg) |
| void | CSL_CPSW_setAlePolicerEntry (CSL_AleRegs *hCpswAleRegs, Uint32 index, CSL_CPSW_ALE_POLICER_ENTRY *pPolCfg) |
| void | CSL_CPSW_disableAlePolicerThread (CSL_AleRegs *hCpswAleRegs, Uint32 index) |
| void | CSL_CPSW_setAleUnknwnVlanMemberReg (CSL_AleRegs *hCpswAleRegs, Uint32 aleUnknwnVlanMemberVal) |
| void | CSL_CPSW_setAleUnknwnVlanUntagReg (CSL_AleRegs *hCpswAleRegs, Uint32 aleUnknwnVlanUntagVal) |
| void | CSL_CPSW_setCppiP0Control (CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_CPPI_P0_CONTROL *pCppiP0ControlCfg) |
| void | CSL_CPSW_setAleUnknwnVlanUnregMcastReg (CSL_AleRegs *hCpswAleRegs, Uint32 aleUnknwnVlanUnregMcastVal) |
| void | CSL_CPSW_setAleUnknwnVlanRegMcastReg (CSL_AleRegs *hCpswAleRegs, Uint32 aleUnknwnVlanRegMcastVal) |
| void | CSL_CPSW_setAlePolicerControlReg (CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_POLICER_CONTROL *policerCntrlCfg) |
| void | CSL_CPSW_getAlePolicerControlReg (CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_POLICER_CONTROL *policerCntrlCfg) |
| void | CSL_CPSW_setAlePolicerTestControlReg (CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_POLICER_TEST_CONTROL *policerTestCntrlCfg) |
| void | CSL_CPSW_getAlePolicerHstatReg (CSL_AleRegs *hCpswAleRegs, CSL_CPSW_ALE_POLICER_HSTAT *policerHStatCfg) |
| void | CSL_CPSW_setAleOAMLpbkControl (CSL_AleRegs *hCpswAleRegs, Uint32 lpbkEnablePortMask) |
| void | CSL_CPSW_getAleStatusNumPolicers (CSL_AleRegs *hCpswAleRegs, Uint32 *pNumPolicers) |
| void | CSL_CPSW_setCppiPriCirEir (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 cir, Uint32 eir) |
| void | CSL_CPSW_getCppiPriCirEir (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 *cir, Uint32 *eir) |
| void | CSL_CPSW_setPriCirEir (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri, Uint32 cir, Uint32 eir) |
| void | CSL_CPSW_getPriCirEir (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri, Uint32 *cir, Uint32 *eir) |
| void | CSL_CPSW_setCppiRxPriFlowControl (CSL_Xge_cpswRegs *hCpswRegs, Uint8 pri) |
| Uint8 | CSL_CPSW_getCppiRxPriFlowControl (CSL_Xge_cpswRegs *hCpswRegs) |
| void | CSL_CPSW_setCppiTxDstThresholdSetX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal) |
| Uint32 | CSL_CPSW_getCppiTxDstThresholdSetX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri) |
| void | CSL_CPSW_setCppiTxDstThresholdClrX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal) |
| Uint32 | CSL_CPSW_getCppiDstTxThresholdClrX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri) |
| void | CSL_CPSW_setCppiTxGlobalBufThresholdSetX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal) |
| Uint32 | CSL_CPSW_getCppiTxGlobalBufThresholdSetX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri) |
| void | CSL_CPSW_setCppiTxGlobalBufThresholdClrX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal) |
| Uint32 | CSL_CPSW_getCppiTxGlobalBufThresholdClrX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri) |
| void | CSL_CPSW_setcppiTxBlksPri (CSL_Xge_cpswRegs *hCpswRegs, Uint8 pri, Uint32 blks) |
| Uint32 | CSL_CPSW_getCppiTxBlksPri (CSL_Xge_cpswRegs *hCpswRegs, Uint8 pri) |
| void | CSL_CPSW_setTxBlksPri (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint8 pri, Uint32 blks) |
| Uint32 | CSL_CPSW_getTxBlksPri (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint8 pri) |
| void | CSL_CPSW_setTxPriFlowControl (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint8 pri) |
| Uint8 | CSL_CPSW_getTxPriFlowControl (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo) |
| void | CSL_CPSW_setRxPriFlowControl (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint8 pri) |
| Uint8 | CSL_CPSW_getRxPriFlowControl (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo) |
| Uint32 | CSL_CPSW_getTxHostBlksRem (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo) |
| void | CSL_CPSW_setTxHostBlksRem (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 txBlksRem) |
| void | CSL_CPSW_setTxDstThresholdSetX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri, Uint32 setVal) |
| Uint32 | CSL_CPSW_getTxDstThresholdSetX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri) |
| void | CSL_CPSW_setTxDstThresholdClrX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri, Uint32 setVal) |
| Uint32 | CSL_CPSW_getTxDstThresholdClrX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri) |
| void | CSL_CPSW_setTxGlobalBufThresholdSetX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri, Uint32 setVal) |
| Uint32 | CSL_CPSW_getTxGlobalBufThresholdSetX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri) |
| void | CSL_CPSW_setTxGlobalBufThresholdClrX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri, Uint32 setVal) |
| Uint32 | CSL_CPSW_getTxGlobalBufThresholdClrX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri) |
| void | CSL_CPSW_setTxDstBasedOutFlowAddValX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri, Uint32 addVal) |
| Uint32 | CSL_CPSW_getTxDstBasedOutFlowAddValX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 portNo, Uint32 pri) |
| void | CSL_CPSW_setTxGlobalOutFlowThresholdSetX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal) |
| Uint32 | CSL_CPSW_getTxGlobalOutFlowThresholdSetX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri) |
| void | CSL_CPSW_setTxGlobalOutFlowThresholdClrX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal) |
| Uint32 | CSL_CPSW_getTxGlobalOutFlowThresholdClrX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri) |
| void | CSL_CPSW_setCpswTxGlobalBufThresholdSetX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal) |
| Uint32 | CSL_CPSW_getCpswTxGlobalBufThresholdSetX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri) |
| void | CSL_CPSW_setCpswTxGlobalBufThresholdClrX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri, Uint32 setVal) |
| Uint32 | CSL_CPSW_getCpswTxGlobalBufThresholdClrX (CSL_Xge_cpswRegs *hCpswRegs, Uint32 pri) |
| Uint32 | CSL_CPSW_isP0TxCastagnoliCRCEnabled (CSL_Xge_cpswRegs *hCpswRegs) |
| void | CSL_CPSW_enableP0TxCastagnoliCRC (CSL_Xge_cpswRegs *hCpswRegs) |
| void | CSL_CPSW_disableP0TxCastagnoliCRC (CSL_Xge_cpswRegs *hCpswRegs) |
| void | CSL_CPSW_getPTypeReg (CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_PTYPE *pPtypeCfg) |
| void | CSL_CPSW_setPTypeReg (CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_PTYPE *pPtypeCfg) |
| void | CSL_CPSW_getThruRateReg (CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_THRURATE *pThruRateCfg) |
| Uint32 | CSL_CPSW_getGapThreshold (CSL_Xge_cpswRegs *hCpswRegs) |
| void | CSL_CPSW_setGapThreshold (CSL_Xge_cpswRegs *hCpswRegs, Uint32 gapThreshold) |
| Uint32 | CSL_CPSW_getTxStartWords (CSL_Xge_cpswRegs *hCpswRegs) |
| Uint32 | CSL_CPSW_getTxMaxLenPerPriority (CSL_Xge_cpswRegs *hCpswRegs, Uint32 priority) |
| void | CSL_CPSW_setTxMaxLenPerPriority (CSL_Xge_cpswRegs *hCpswRegs, Uint32 priority, Uint32 maxLen) |
| void | CSL_CPSW_getCppiP0Control (CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_CPPI_P0_CONTROL *pCppiP0ControlCfg) |
| void | CSL_CPSW_setCppiRxPType (CSL_Xge_cpswRegs *hCpswRegs, Uint32 p0RxPtype) |
| Uint32 | CSL_CPSW_getCppiRxPType (CSL_Xge_cpswRegs *hCpswRegs) |
| Uint32 | CSL_CPSW_getCppiRxPacketsPriority (CSL_Xge_cpswRegs *hCpswRegs, Uint32 priority) |
| void | CSL_CPSW_setCppiRxPacketsPriority (CSL_Xge_cpswRegs *hCpswRegs, Uint32 priority, Uint32 rxPackets) |
| void | CSL_CPSW_getCppiRxGapReg (CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_CPPI_P0_RXGAP *pCppiRxGap) |
| void | CSL_CPSW_setCppiRxGapReg (CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_CPPI_P0_RXGAP *pCppiRxGap) |
| void | CSL_CPSW_getP0FifoStatus (CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_CPPI_P0_FIFOSTATUS *pCppiFifoStats) |
| void | CSL_CPSW_getP0HostBlksPri (CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_CPPI_P0_HOSTBLKSPRI *pCppiHostBlksPri) |
| void | CSL_CPSW_setP0HostBlksPri (CSL_Xge_cpswRegs *hCpswRegs, CSL_CPSW_CPPI_P0_HOSTBLKSPRI *pCppiHostBlksPri) |
| void CSL_CPSW_getCpswVersionInfo | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| CSL_CPSW_VERSION * | pVersionInfo | ||
| ) |
============================================================================
CSL_CPSW_nGF_getCpswVersionInfo
Description
This function retrieves the CPSW identification and version information.
Arguments
pVersionInfo CSL_CPSW_VERSION structure that needs to be populated
with the version info read from the hardware.
* Return Value
None
Pre Condition
None
Post Condition
None
Reads
XGE_CPSW_CPSW_ID_VER_REG_CPSW_5GF_MINOR_VER, XGE_CPSW_CPSW_ID_VER_REG_CPSW_5GF_MAJ_VER, XGE_CPSW_CPSW_ID_VER_REG_CPSW_5GF_RTL_VER, XGE_CPSW_CPSW_ID_VER_REG_CPSW_5GF_IDENT
Example
CSL_CPSW_VERSION versionInfo;
CSL_CPSW_getCpswVersionInfo (&versionInfo);| Uint32 CSL_CPSW_isVlanAwareEnabled | ( | CSL_Xge_cpswRegs * | hCpswRegs | ) |
============================================================================
CSL_CPSW_isVlanAwareEnabled
Description
This function indicates if VLAN aware mode is enabled in the CPSW control register.
Arguments
None
Return Value
TRUE VLAN aware mode enabled.
FALSE VLAN aware mode disabled.
Pre Condition
None
Post Condition
None
Reads
XGE_CPSW_CONTROL_REG_VLAN_AWARE
Example
if (CSL_CPSW_isVlanAwareEnabled (portNum) == TRUE)
{
// VLAN aware mode enabled
}
else
{
// VLAN aware mode disabled
}| void CSL_CPSW_enableVlanAware | ( | CSL_Xge_cpswRegs * | hCpswRegs | ) |
============================================================================
CSL_CPSW_enableVlanAware
Description
This function configures the CPSW control register to enable VLAN aware mode.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
XGE_CPSW_CONTROL_REG_VLAN_AWARE=1
Example
CSL_CPSW_enableVlanAware ();
| void CSL_CPSW_setVlanType | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | vlanType | ||
| ) |
| void CSL_CPSW_disableVlanAware | ( | CSL_Xge_cpswRegs * | hCpswRegs | ) |
============================================================================
CSL_CPSW_disableVlanAware
Description
This function configures the CPSW control register to disable VLAN aware mode.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
XGE_CPSW_CONTROL_REG_VLAN_AWARE=0
Example
CSL_CPSW_disableVlanAware ();
| Uint32 CSL_CPSW_isPort0Enabled | ( | CSL_Xge_cpswRegs * | hCpswRegs | ) |
============================================================================
CSL_CPSW_isPort0Enabled
Description
This function indicates if CPPI Port (Port 0) is enabled in the CPSW control register.
Arguments
None
Return Value
TRUE Port 0 enabled.
FALSE Port 0 disabled.
Pre Condition
None
Post Condition
None
Reads
XGE_CPSW_CONTROL_REG_P0_ENABLE
Example
if (CSL_CPSW_isPort0Enabled (portNum) == TRUE)
{
// Port 0 enabled
}
else
{
// Port 0 disabled
}| void CSL_CPSW_enablePort0 | ( | CSL_Xge_cpswRegs * | hCpswRegs | ) |
============================================================================
CSL_CPSW_enablePort0
Description
This function configures the CPSW control register to enable the Port 0.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
XGE_CPSW_CONTROL_REG_P0_ENABLE=1
Example
CSL_CPSW_enablePort0 ();
| void CSL_CPSW_disablePort0 | ( | CSL_Xge_cpswRegs * | hCpswRegs | ) |
============================================================================
CSL_CPSW_disablePort0
Description
This function configures the CPSW control register to disable the Port 0.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
XGE_CPSW_CONTROL_REG_P0_ENABLE=0
Example
CSL_CPSW_disablePort0 ();
| Uint32 CSL_CPSW_isPort0PassPriTagEnabled | ( | CSL_Xge_cpswRegs * | hCpswRegs | ) |
============================================================================
CSL_CPSW_isPort0PassPriTagEnabled
Description
This function indicates if priority tagging is enabled for Port 0.
Arguments
None
Return Value
TRUE Port 0 ingress priority tagging enabled.
FALSE Port 0 ingress priority tagging disabled.
Pre Condition
None
Post Condition
None
Reads
XGE_CPSW_CONTROL_REG_P0_PASS_PRI_TAGGED
Example
if (CSL_CPSW_isPort0PassPriTagEnabled () == TRUE)
{
// Port 0 pass priority tagging enabled
}
else
{
// Port 0 pass priority tagging disabled
}| void CSL_CPSW_enablePort0PassPriTag | ( | CSL_Xge_cpswRegs * | hCpswRegs | ) |
============================================================================
CSL_CPSW_enablePort0PassPriTag
Description
This function configures the CPSW control register to enable the Ingress priority tagging on Port 0.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
XGE_CPSW_CONTROL_REG_P0_PASS_PRI_TAGGED=1
Example
CSL_CPSW_enablePort0PassPriTag ();
| void CSL_CPSW_disablePort0PassPriTag | ( | CSL_Xge_cpswRegs * | hCpswRegs | ) |
============================================================================
CSL_CPSW_disablePort0PassPriTag
Description
This function configures the CPSW control register to disable the Ingress priority tagging on Port 0.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
XGE_CPSW_CONTROL_REG_P0_PASS_PRI_TAGGED=0
Example
CSL_CPSW_disablePort0PassPriTag ();
| Uint32 CSL_CPSW_isPort1PassPriTagEnabled | ( | CSL_Xge_cpswRegs * | hCpswRegs | ) |
============================================================================
CSL_CPSW_isPort1PassPriTagEnabled
Description
This function indicates if priority tagging is enabled for Port 1.
Arguments
None
Return Value
TRUE Port 1 ingress priority tagging enabled.
FALSE Port 1 ingress priority tagging disabled.
Pre Condition
None
Post Condition
None
Reads
XGE_CPSW_CONTROL_REG_P1_PASS_PRI_TAGGED
Example
if (CSL_CPSW_isPort1PassPriTagEnabled () == TRUE)
{
// Port 1 pass priority tagging enabled
}
else
{
// Port 1 pass priority tagging disabled
}| void CSL_CPSW_enablePortPassPriTag | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum | ||
| ) |
============================================================================
CSL_CPSW_enablePort1PassPriTag
Description
This function configures the CPSW control register to enable the Ingress priority tagging on Port 1.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
XGE_CPSW_CONTROL_REG_P1_PASS_PRI_TAGGED=1
Example
CSL_CPSW_enablePort1PassPriTag ();
| void CSL_CPSW_disablePortPassPriTag | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum | ||
| ) |
============================================================================
CSL_CPSW_disablePort1PassPriTag
Description
This function configures the CPSW control register to disable the Ingress priority tagging on Port 1.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
XGE_CPSW_CONTROL_REG_P1_PASS_PRI_TAGGED=0
Example
CSL_CPSW_disablePort1PassPriTag ();
| void CSL_CPSW_getCpswControlReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| CSL_CPSW_CONTROL * | pControlRegInfo | ||
| ) |
============================================================================
CSL_CPSW_getCpswControlReg
Description
This function retrieves the contents of the CPSW Control register.
Arguments
pControlRegInfo CSL_CPSW_CONTROL structure that needs to be populated
with the control register contents.
* Return Value
None
Pre Condition
None
Post Condition
None
Reads
XGE_CPSW_CONTROL_REG_VLAN_AWARE, XGE_CPSW_CONTROL_REG_P0_ENABLE, XGE_CPSW_CONTROL_REG_P0_PASS_PRI_TAGGED, XGE_CPSW_CONTROL_REG_P1_PASS_PRI_TAGGED, XGE_CPSW_CONTROL_REG_P0_RX_PAD, XGE_CPSW_CONTROL_REG_P0_RX_PASS_CRC_ERR, XGE_CPSW_CONTROL_REG_EEE_ENABLE
@b Example
CSL_CPSW_CONTROL controlRegInfo;
CSL_CPSW_getCpswControlReg (&controlRegInfo);| void CSL_CPSW_setCpswControlReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| CSL_CPSW_CONTROL * | pControlRegInfo | ||
| ) |
============================================================================
CSL_CPSW_setCpswControlReg
Description
This function populates the contents of the CPSW Control register.
Arguments
pControlRegInfo CSL_CPSW_CONTROL structure that holds the values
that need to be configured to the CPSW control register.
* Return Value
None
Pre Condition
None
Post Condition
CPSW control register modified with values provided.
Writes
XGE_CPSW_CONTROL_REG_VLAN_AWARE, XGE_CPSW_CONTROL_REG_P0_ENABLE, XGE_CPSW_CONTROL_REG_P0_PASS_PRI_TAGGED, XGE_CPSW_CONTROL_REG_P1_PASS_PRI_TAGGED, XGE_CPSW_CONTROL_REG_P1_PASS_PRI_TAGGED, XGE_CPSW_CONTROL_REG_P0_TX_CRC_REMOVE, XGE_CPSW_CONTROL_REG_P0_RX_PAD, XGE_CPSW_CONTROL_REG_P0_RX_PASS_CRC_ERR, XGE_CPSW_CONTROL_REG_EEE_ENABLE
Example
CSL_CPSW_CONTROL controlRegInfo;
controlRegInfo.vlanAware = 0;
...
CSL_CPSW_setCpswControlReg (&controlRegInfo);| void CSL_CPSW_getEmulationControlReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 * | pFree, | ||
| Uint32 * | pSoft | ||
| ) |
============================================================================
CSL_CPSW_getEmulationControlReg
Description
This function retrieves the contents of the CPSW Emulation Control register.
Arguments
pFree Emulation free bit read from the hardware.
pSoft Emulation soft bit read from the hardware.
* Return Value
None
Pre Condition
None
Post Condition
None
Reads
XGE_CPSW_EM_CONTROL_REG_FREE, XGE_CPSW_EM_CONTROL_REG_SOFT
Example
Uint32 free, soft;
CSL_CPSW_getEmulationControlReg (&free, &soft);| void CSL_CPSW_setEmulationControlReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | free, | ||
| Uint32 | soft | ||
| ) |
============================================================================
CSL_CPSW_setEmulationControlReg
Description
This function sets up the contents of the CPSW Emulation Control register.
Arguments
free Emulation free bit configuration
soft Emulation soft bit configuration
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
XGE_CPSW_EM_CONTROL_REG_FREE, XGE_CPSW_EM_CONTROL_REG_SOFT
Example
Uint32 free, soft;
free = 0;
soft = 1;
CSL_CPSW_setEmulationControlReg (free, soft);| void CSL_CPSW_getPortStatsEnableReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| CSL_CPSW_PORTSTAT * | pPortStatsCfg | ||
| ) |
============================================================================
CSL_CPSW_getPortStatsEnableReg
Description
This function retrieves the contents of the CPSW Port Statistics Enable register.
Arguments
pPortStatsCfg CSL_XGE_CPSW_PORTSTAT structure that needs to be populated
with the port statistics enable register contents.
* Return Value
None
Pre Condition
None
Post Condition
None
Reads
XGE_CPSW_STAT_PORT_EN_REG_P0_STAT_EN, XGE_CPSW_STAT_PORT_EN_REG_P1_STAT_EN,
Example
CSL_CPSW_PORTSTAT portStatsCfg;
CSL_CPSW_getPortStatsEnableReg (&portStatsCfg);| void CSL_CPSW_setPortStatsEnableReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| CSL_CPSW_PORTSTAT * | pPortStatsCfg | ||
| ) |
============================================================================
CSL_CPSW_setPortStatsEnableReg
Description
This function sets up the contents of the CPSW Port Statistics Enable register.
Arguments
pPortStatsCfg CSL_CPSW_PORTSTAT structure that contains the values
to be used to setup port statistics enable register.
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
XGE_CPSW_STAT_PORT_EN_REG_P0_STAT_EN, XGE_CPSW_STAT_PORT_EN_REG_P1_STAT_EN,
Example
CSL_CPSW_PORTSTAT portStatsCfg;
portStatsCfg.p0StatEnable = 1;
portStatsCfg.p1StatEnable = 1;
...
CSL_CPSW_setPortStatsEnableReg (&portStatsCfg);| Uint32 CSL_CPSW_isSoftIdle | ( | CSL_Xge_cpswRegs * | hCpswRegs | ) |
============================================================================
CSL_CPSW_isSoftIdle
Description
This function indicates if the CPSW is at Software Idle mode where no packets will be started to be unloaded from ports.
Arguments
None
Return Value
TRUE Software Idle mode enabled.
FALSE Software Idle mode disabled.
Pre Condition
None
Post Condition
None
Reads
XGE_CPSW_SOFT_IDLE_REG_SOFT_IDLE
Example
if (CSL_CPSW_isSoftIdle () == TRUE)
{
// Software Idle mode enabled
}
else
{
// Software Idle mode disabled
}| void CSL_CPSW_enableSoftIdle | ( | CSL_Xge_cpswRegs * | hCpswRegs | ) |
============================================================================
CSL_CPSW_enableSoftIdle
Description
This function configures the CPSW Soft Idle register to enable Software Idle mode.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
XGE_CPSW_SOFT_IDLE_REG_SOFT_IDLE=1
Example
CSL_CPSW_enableSoftIdle ();
| void CSL_CPSW_disableSoftIdle | ( | CSL_Xge_cpswRegs * | hCpswRegs | ) |
============================================================================
CSL_CPSW_disableSoftIdle
Description
This function configures the CPSW Soft Idle register to disable Software Idle mode.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
XGE_CPSW_SOFT_IDLE_REG_SOFT_IDLE=0
Example
CSL_CPSW_disableSoftIdle ();
| void CSL_CPSW_getPortControlReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| CSL_CPSW_PORT_CONTROL * | pControlInfo | ||
| ) |
============================================================================
CSL_CPSW_getPortControlReg
Description
This function retrieves the contents of the Port Control Register corresponding to the CPSW port number specified.
Arguments
portNum CPSW port number for which the register contents
must be read and returned.
pControlInfo CSL_CPSW_PORT_CONTROL structure that needs to be populated
with the control register contents.
* Return Value
None
Pre Condition
none
Post Condition
None
Reads
XGE_CPSW_P0_CONTROL_REG_DSCP_IPV4_EN, XGE_CPSW_P0_CONTROL_REG_DSCP_IPV6_EN,
XGE_CPSW_PN_CONTROL_REG_DSCP_IPV4_EN, XGE_CPSW_PN_CONTROL_REG_DSCP_IPV6_EN, XGE_CPSW_PN_CONTROL_REG_TX_LPI_CLKSTOP_EN,
@b Example
* Uint32 portNum;
CSL_CPSW_PORT_CONTROL controlInfo;
portNum = 1;
CSL_CPSW_getPortControlReg (portNum, &controlInfo);| void CSL_CPSW_setPortControlReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| CSL_CPSW_PORT_CONTROL * | pControlInfo | ||
| ) |
============================================================================
CSL_CPSW_setPortControlReg
Description
This function sets up the contents of the Port Control Register corresponding to the CPSW port number specified.
Arguments
portNum CPSW port number for which the register contents
must be read and returned.
pControlInfo CSL_CPSW_PORT_CONTROL structure that holds the values
that need to be configured to the CPSW Port
control register.
* Return Value
None
Pre Condition
none
Post Condition
None
Writes
XGE_CPSW_P0_CONTROL_REG_DSCP_IPV4_EN, XGE_CPSW_P0_CONTROL_REG_DSCP_IPV6_EN,
XGE_CPSW_PN_CONTROL_REG_DSCP_IPV4_EN, XGE_CPSW_PN_CONTROL_REG_DSCP_IPV6_EN, XGE_CPSW_PN_CONTROL_REG_TX_LPI_CLKSTOP_EN,
@b Example
* Uint32 portNum;
CSL_CPSW_PORT_CONTROL controlInfo;
portNum = 1;
controlInfo.dscpIpv4Enable = 1;
controlInfo.dscpIpv6Enable = 1;
controlInfo.txLpiClkstopEnable = 0;
CSL_CPSW_setPortControlReg (portNum, &controlInfo);| void CSL_CPSW_getCppiSourceIdReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 * | pTxSrcId | ||
| ) |
============================================================================
CSL_CPSW_getCppiSourceIdReg
Description
This function retrieves the contents of the CPPI Source Identification register.
Arguments
pTxSrcId[8] CPPI Info Word0 Source Id Value on Tx Ports respectively. *
Return Value
None
Pre Condition
None
Post Condition
None
Reads
XGE_CPSW_P0_SRC_ID_A_REG_PORT1
Example
* Uint32 txSrcId[8];
CSL_CPSW_getCppiSourceIdReg (txSrcId);| void CSL_CPSW_setCppiSourceIdReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 * | pTxSrcId | ||
| ) |
============================================================================
CSL_CPSW_setCppiSourceIdReg
Description
This function sets up the contents of the CPPI Source Identification register.
Arguments
pTxSrcId[8] CPPI Info Word0 Source Id Value on Tx Ports respectively. *
Return Value
None
Pre Condition
None
Post Condition
None
Writes
XGE_CPSW_P0_SRC_ID_A_REG_PORT1
Example
* Uint32 txSrcId[8];
txSrcId[0] = 1;
...
CSL_CPSW_setCppiSourceIdReg (txSrcId);| void CSL_CPSW_getPort0VlanReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 * | pPortVID, | ||
| Uint32 * | pPortCFI, | ||
| Uint32 * | pPortPRI | ||
| ) |
============================================================================
CSL_CPSW_getPort0VlanReg
Description
This function retrieves the contents of the Port 0 VLAN Register.
Arguments
pPortVID Port VLAN Id
pPortCFI Port CFI bit
pPortPRI Port VLAN priority (0-7, 7 is highest priority)
* Return Value
None
Pre Condition
None
Post Condition
None
Reads
XGE_CPSW_P0_PORT_VLAN_REG_PORT_VID, XGE_CPSW_P0_PORT_VLAN_REG_PORT_CFI, XGE_CPSW_P0_PORT_VLAN_REG_PORT_PRI
Example
* Uint32 portVID, portCFI, portPRI;
CSL_CPSW_getPort0VlanReg (&portVID, &portCFI, &portPRI);| void CSL_CPSW_setPort0VlanReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portVID, | ||
| Uint32 | portCFI, | ||
| Uint32 | portPRI | ||
| ) |
============================================================================
CSL_CPSW_setPort0VlanReg
Description
This function sets up the contents of the Port 0 VLAN Register.
Arguments
portVID Port VLAN Id to be configured
portCFI Port CFI bit to be configured
portPRI Port VLAN priority to be configured
(0-7, 7 is highest priority)
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
XGE_CPSW_P0_PORT_VLAN_REG_PORT_VID, XGE_CPSW_P0_PORT_VLAN_REG_PORT_CFI, XGE_CPSW_P0_PORT_VLAN_REG_PORT_PRI
Example
* Uint32 portVID, portCFI, portPRI;
portVID = 1;
portCFI = 0;
portPRI = 7;
CSL_CPSW_setPort0VlanReg (portVID, portCFI, portPRI);| void CSL_CPSW_getPort0RxPriMapReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 * | pPortRxPriMap | ||
| ) |
============================================================================
CSL_CPSW_getPort0RxPriMapReg
Description
This function retrieves the contents of the Port 0 Receive Packet Priority to Header Priority Mapping Register.
Arguments
pPortRxPriMap Array of Port 0 Rx priority map priority values
read from the register.
* Return Value
None
Pre Condition
The input parameter 'pPortRxPriMap' must be large enough to hold all the 8 priority values read from the register.
Post Condition
None
Reads
XGE_CPSW_P0_RX_PRI_MAP_REG_PRI0, XGE_CPSW_P0_RX_PRI_MAP_REG_PRI1, XGE_CPSW_P0_RX_PRI_MAP_REG_PRI2, XGE_CPSW_P0_RX_PRI_MAP_REG_PRI3, XGE_CPSW_P0_RX_PRI_MAP_REG_PRI4, XGE_CPSW_P0_RX_PRI_MAP_REG_PRI5, XGE_CPSW_P0_RX_PRI_MAP_REG_PRI6, XGE_CPSW_P0_RX_PRI_MAP_REG_PRI7
Example
* Uint32 port0RxPriMap [8];
CSL_CPSW_getPort0RxPriMapReg (port0RxPriMap);| void CSL_CPSW_setPort0RxPriMapReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 * | pPortRxPriMap | ||
| ) |
============================================================================
CSL_CPSW_setPort0RxPriMapReg
Description
This function sets up the contents of the Port 0 Receive Packet Priority to Header Priority Mapping Register.
Arguments
pPortRxPriMap Array of Port 0 Rx priority map priority values
that must be configured to the register.
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
XGE_CPSW_P0_RX_PRI_MAP_REG_PRI0, XGE_CPSW_P0_RX_PRI_MAP_REG_PRI1, XGE_CPSW_P0_RX_PRI_MAP_REG_PRI2, XGE_CPSW_P0_RX_PRI_MAP_REG_PRI3, XGE_CPSW_P0_RX_PRI_MAP_REG_PRI4, XGE_CPSW_P0_RX_PRI_MAP_REG_PRI5, XGE_CPSW_P0_RX_PRI_MAP_REG_PRI6, XGE_CPSW_P0_RX_PRI_MAP_REG_PRI7
Example
* Uint32 i, port0RxPriMap [8];
for (i = 0; i < 8; i ++)
port0RxPriMap [i] = i;
CSL_CPSW_setPort0RxPriMapReg (port0RxPriMap);| Uint32 CSL_CPSW_getPort0FlowIdOffset | ( | CSL_Xge_cpswRegs * | hCpswRegs | ) |
============================================================================
CSL_CPSW_getPort0FlowIdOffset
Description
This function retrieves the contents of the Port 0 Flow ID Offset Register, which is added to the thread/Flow_ID in CPPI transmit PSI Info Word 0.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Reads
XGE_CPSW_P0_FLOW_ID_OFFSET_REG_VALUE
Example
* Uint32 flowIdOffset;
flowIdOffset = CSL_CPSW_getPort0FlowIdOffset ();| void CSL_CPSW_setPort0FlowIdOffset | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | flowIdOffset | ||
| ) |
============================================================================
CSL_CPSW_setPort0FlowIdOffset
Description
This function sets up the Port0 Flow ID Offset register. which is added to the thread/Flow_ID in CPPI transmit PSI Info Word 0.
Arguments
flowIdOffset CPPI Flow ID offset to configure. *
Return Value
None
Pre Condition
None
Post Condition
None
Writes
XGE_CPSW_P0_FLOW_ID_OFFSET_REG_VALUE
Example
* Uint32 flowIdOffset;
flowIdOffset = 0;
CSL_CPSW_setPort0FlowIdOffset (flowIdOffset);| Uint32 CSL_CPSW_getPort0RxMaxLen | ( | CSL_Xge_cpswRegs * | hCpswRegs | ) |
============================================================================
CSL_CPSW_getPort0RxMaxLen
Description
This function retrieves the contents of the Port 0 Receive Maximum Length Register.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Reads
XGE_CPSW_P0_RX_MAXLEN_REG_RX_MAXLEN
Example
* Uint32 rxMaxLen;
rxMaxLen = CSL_CPSW_getPort0RxMaxLen ();| void CSL_CPSW_setPort0RxMaxLen | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | rxMaxLen | ||
| ) |
============================================================================
CSL_CPSW_setPort0RxMaxLen
Description
This function sets up the Port0 Receive Maximum length register.
Arguments
rxMaxLen Maximum receive frame length to configure. *
Return Value
None
Pre Condition
None
Post Condition
None
Writes
XGE_CPSW_P0_RX_MAXLEN_REG_RX_MAXLEN
Example
* Uint32 rxMaxLen;
rxMaxLen = 1518;
CSL_CPSW_setPort0RxMaxLen (rxMaxLen);| void CSL_CPSW_getPortBlockCountReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| Uint32 * | pRxBlkCnt_e, | ||
| Uint32 * | pRxBlkCnt_p, | ||
| Uint32 * | pTxBlkCnt | ||
| ) |
============================================================================
CSL_CPSW_getPortBlockCountReg
Description
This function retrieves the contents of the Port Block Count register corresponding to the CPSW port specified.
Arguments
portNum CPSW port number for which the block count
must be retrieved.
pRxBlkCnt_e Receive block count usage read for express MAC for this port.
pRxBlkCnt_p Receive block count usage read for preempt MAC for this port.
pTxBlkCnt Transmit block count usage read for this port.
* Return Value
None
Pre Condition
None
Post Condition
None
Reads
XGE_CPSW_PN_BLK_CNT_REG_RX_BLK_CNT_E, XGE_CPSW_PN_BLK_CNT_REG_RX_BLK_CNT_P, XGE_CPSW_PN_BLK_CNT_REG_TX_BLK_CNT, XGE_CPSW_P0_BLK_CNT_REG_RX_BLK_CNT, XGE_CPSW_P0_BLK_CNT_REG_TX_BLK_CNT,
Example
* Uint32 rxBlkCnt_e, rxBlkCnt_p, txBlkCnt, portNum;
portNum = 1;
CSL_CPSW_getPortBlockCountReg (portNum, &rxBlkCnt, &rxBlkCnt_p,
&txBlkCnt);| Uint32 CSL_CPSW_getPortRxMaxLen | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum | ||
| ) |
============================================================================
CSL_CPSW_getPortRxMaxLen
Description
This function retrieves the contents of the CPSW Port Receive Maximum Length Register.
Arguments portNum CPSW port number for which the Receive Maximum Length must be retrieved.
Return Value
None
Pre Condition
None
Post Condition
None
Reads
XGE_CPSW_P0_RX_MAXLEN_REG_RX_MAXLEN XGE_CPSW_PN_RX_MAXLEN_REG_RX_MAXLEN
Example
* Uint32 portNum, rxMaxLen;
portNum = 1;
rxMaxLen = CSL_CPSW_getPortRxMaxLen (portNum);| void CSL_CPSW_setPortRxMaxLen | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| Uint32 | rxMaxLen | ||
| ) |
============================================================================
CSL_CPSW_setPortRxMaxLen
Description
This function sets up the Port Receive Maximum length register.
Arguments
portNum CPSW port number for which the Receive Maximum Length
must be retrieved.
rxMaxLen Maximum receive frame length to configure.
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
XGE_CPSW_P0_RX_MAXLEN_REG_RX_MAXLEN XGE_CPSW_PN_RX_MAXLEN_REG_RX_MAXLEN
Example
* Uint32 portNum, rxMaxLen;
portNum = 1;
rxMaxLen = 1518;
CSL_CPSW_setPortRxMaxLen (portNum, rxMaxLen);| void CSL_CPSW_getPortTxPriMapReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| Uint32 * | pPortTxPriMap | ||
| ) |
============================================================================
CSL_CPSW_getPortTxPriMapReg
Description
This function retrieves the contents of the Port Transmit Packet Priority to Header Priority Mapping Register.
Arguments
portNum CPSW port number for which the block count
must be retrieved.
pPortRxPriMap Array of Port Rx priority map priority values
read from the register.
* Return Value
None
Pre Condition
The input parameter 'pPortRxPriMap' must be large enough to hold all the 8 priority values read from the register.
Post Condition
None
Reads
XGE_CPSW_P0_TX_PRI_MAP_REG_PRI0, XGE_CPSW_P0_TX_PRI_MAP_REG_PRI1, XGE_CPSW_P0_TX_PRI_MAP_REG_PRI2, XGE_CPSW_P0_TX_PRI_MAP_REG_PRI3, XGE_CPSW_P0_TX_PRI_MAP_REG_PRI4, XGE_CPSW_P0_TX_PRI_MAP_REG_PRI5, XGE_CPSW_P0_TX_PRI_MAP_REG_PRI6, XGE_CPSW_P0_TX_PRI_MAP_REG_PRI7,
XGE_CPSW_PN_TX_PRI_MAP_REG_PRI0, XGE_CPSW_PN_TX_PRI_MAP_REG_PRI1, XGE_CPSW_PN_TX_PRI_MAP_REG_PRI2, XGE_CPSW_PN_TX_PRI_MAP_REG_PRI3, XGE_CPSW_PN_TX_PRI_MAP_REG_PRI4, XGE_CPSW_PN_TX_PRI_MAP_REG_PRI5, XGE_CPSW_PN_TX_PRI_MAP_REG_PRI6, XGE_CPSW_PN_TX_PRI_MAP_REG_PRI7
Example
* Uint32 portNum = 1;
* Uint32 portRxPriMap [8];
CSL_CPSW_getPortTxPriMapReg (portNum, portRxPriMap);| void CSL_CPSW_setPortTxPriMapReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| Uint32 * | pPortTxPriMap | ||
| ) |
============================================================================
CSL_CPSW_setPortTxPriMapReg
Description
This function sets up the contents of the Port Transmit Packet Priority to Header Priority Mapping Register.
Arguments
portNum CPSW port number for which the priority mapping
registers must be configured.
pPortRxPriMap Array of Port Rx priority map priority values
that must be configured to the register.
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
XGE_CPSW_P0_TX_PRI_MAP_REG_PRI0, XGE_CPSW_P0_TX_PRI_MAP_REG_PRI1, XGE_CPSW_P0_TX_PRI_MAP_REG_PRI2, XGE_CPSW_P0_TX_PRI_MAP_REG_PRI3, XGE_CPSW_P0_TX_PRI_MAP_REG_PRI4, XGE_CPSW_P0_TX_PRI_MAP_REG_PRI5, XGE_CPSW_P0_TX_PRI_MAP_REG_PRI6, XGE_CPSW_P0_TX_PRI_MAP_REG_PRI7,
XGE_CPSW_PN_TX_PRI_MAP_REG_PRI0, XGE_CPSW_PN_TX_PRI_MAP_REG_PRI1, XGE_CPSW_PN_TX_PRI_MAP_REG_PRI2, XGE_CPSW_PN_TX_PRI_MAP_REG_PRI3, XGE_CPSW_PN_TX_PRI_MAP_REG_PRI4, XGE_CPSW_PN_TX_PRI_MAP_REG_PRI5, XGE_CPSW_PN_TX_PRI_MAP_REG_PRI6, XGE_CPSW_PN_TX_PRI_MAP_REG_PRI7
Example
* Uint32 portNum = 1;
* Uint32 i, port0RxPriMap [8];
for (i = 0; i < 8; i ++)
port0TxPriMap [i] = i;
CSL_CPSW_setPortTxPriMapReg (port0TxPriMap);| void CSL_CPSW_getPortRxPriMapReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| Uint32 * | pPortRxPriMap | ||
| ) |
============================================================================
CSL_CPSW_getPortRxPriMapReg
Description
This function retrieves the contents of the Port Receive Packet Priority to Header Priority Mapping Register.
Arguments
portNum CPSW port number for which the block count
must be retrieved.
pPortRxPriMap Array of Port Rx priority map priority values
read from the register.
* Return Value
None
Pre Condition
The input parameter 'pPortRxPriMap' must be large enough to hold all the 8 priority values read from the register.
Post Condition
None
Reads
XGE_CPSW_P0_RX_PRI_MAP_REG_PRI0, XGE_CPSW_P0_RX_PRI_MAP_REG_PRI1, XGE_CPSW_P0_RX_PRI_MAP_REG_PRI2, XGE_CPSW_P0_RX_PRI_MAP_REG_PRI3, XGE_CPSW_P0_RX_PRI_MAP_REG_PRI4, XGE_CPSW_P0_RX_PRI_MAP_REG_PRI5, XGE_CPSW_P0_RX_PRI_MAP_REG_PRI6, XGE_CPSW_P0_RX_PRI_MAP_REG_PRI7,
XGE_CPSW_PN_RX_PRI_MAP_REG_PRI0, XGE_CPSW_PN_RX_PRI_MAP_REG_PRI1, XGE_CPSW_PN_RX_PRI_MAP_REG_PRI2, XGE_CPSW_PN_RX_PRI_MAP_REG_PRI3, XGE_CPSW_PN_RX_PRI_MAP_REG_PRI4, XGE_CPSW_PN_RX_PRI_MAP_REG_PRI5, XGE_CPSW_PN_RX_PRI_MAP_REG_PRI6, XGE_CPSW_PN_RX_PRI_MAP_REG_PRI7
Example
* Uint32 portNum = 1;
* Uint32 portRxPriMap [8];
CSL_CPSW_getPortRxPriMapReg (portNum, portRxPriMap);| void CSL_CPSW_setPortRxPriMapReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| Uint32 * | pPortRxPriMap | ||
| ) |
============================================================================
CSL_CPSW_setPortRxPriMapReg
Description
This function sets up the contents of the Port Receive Packet Priority to Header Priority Mapping Register.
Arguments
portNum CPSW port number for which the priority mapping
registers must be configured.
pPortRxPriMap Array of Port Rx priority map priority values
that must be configured to the register.
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
XGE_CPSW_P0_RX_PRI_MAP_REG_PRI0, XGE_CPSW_P0_RX_PRI_MAP_REG_PRI1, XGE_CPSW_P0_RX_PRI_MAP_REG_PRI2, XGE_CPSW_P0_RX_PRI_MAP_REG_PRI3, XGE_CPSW_P0_RX_PRI_MAP_REG_PRI4, XGE_CPSW_P0_RX_PRI_MAP_REG_PRI5, XGE_CPSW_P0_RX_PRI_MAP_REG_PRI6, XGE_CPSW_P0_RX_PRI_MAP_REG_PRI7,
XGE_CPSW_PN_RX_PRI_MAP_REG_PRI0, XGE_CPSW_PN_RX_PRI_MAP_REG_PRI1, XGE_CPSW_PN_RX_PRI_MAP_REG_PRI2, XGE_CPSW_PN_RX_PRI_MAP_REG_PRI3, XGE_CPSW_PN_RX_PRI_MAP_REG_PRI4, XGE_CPSW_PN_RX_PRI_MAP_REG_PRI5, XGE_CPSW_PN_RX_PRI_MAP_REG_PRI6, XGE_CPSW_PN_RX_PRI_MAP_REG_PRI7
Example
* Uint32 portNum = 1;
* Uint32 i, port0RxPriMap [8];
for (i = 0; i < 8; i ++)
port0RxPriMap [i] = i;
CSL_CPSW_setPortRxPriMapReg (port0RxPriMap);| void CSL_CPSW_getPortRxDscpMap | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| Uint32 * | pRxDscpPriMap | ||
| ) |
============================================================================
CSL_CPSW_getPortRxDscpMap
Description
This function retrieves the contents of the Port DSCP to Priority Mapping Registers corresponding to the CPSW port specified.
Arguments
portNum CPSW port number for which the DSCP mapping
registers must be retrieved.
pRxDscpPriMap Array of Port Rx DSCP to priority mapping values
read from the registers.
* Return Value
None
Pre Condition
The input parameter 'pRxDscpPriMap' must be large enough to hold all the 64 priority values read from the register.
Post Condition
None
Reads
XGE_CPSW_P0_RX_DSCP_MAP_REG_PRI0, XGE_CPSW_P0_RX_DSCP_MAP_REG_PRI1, XGE_CPSW_P0_RX_DSCP_MAP_REG_PRI2, XGE_CPSW_P0_RX_DSCP_MAP_REG_PRI3, XGE_CPSW_P0_RX_DSCP_MAP_REG_PRI4, XGE_CPSW_P0_RX_DSCP_MAP_REG_PRI5, XGE_CPSW_P0_RX_DSCP_MAP_REG_PRI6, XGE_CPSW_P0_RX_DSCP_MAP_REG_PRI7,
XGE_CPSW_PN_RX_DSCP_MAP_REG_PRI0, XGE_CPSW_PN_RX_DSCP_MAP_REG_PRI1, XGE_CPSW_PN_RX_DSCP_MAP_REG_PRI2, XGE_CPSW_PN_RX_DSCP_MAP_REG_PRI3, XGE_CPSW_PN_RX_DSCP_MAP_REG_PRI4, XGE_CPSW_PN_RX_DSCP_MAP_REG_PRI5, XGE_CPSW_PN_RX_DSCP_MAP_REG_PRI6, XGE_CPSW_PN_RX_DSCP_MAP_REG_PRI7
@b Example
* Uint32 rxDscpPriMap [64], portNum;
portNum = 1;
CSL_CPSW_getPortRxDscpMap (portNum, rxDscpPriMap);| void CSL_CPSW_setPortRxDscpMap | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| Uint32 * | pRxDscpPriMap | ||
| ) |
============================================================================
CSL_CPSW_setPortRxDscpMap
Description
This function sets up the contents of the Port DSCP to Priority Mapping Registers corresponding to the CPSW port specified.
Arguments
portNum CPSW port number for which the DSCP mapping
registers must be configured.
pRxDscpPriMap Array of Port Rx DSCP to priority mapping values
that must be configured to the registers.
* Return Value
None
Pre Condition
The input parameter 'pRxDscpPriMap' must be large enough to hold all the 64 priority values read from the register.
Post Condition
None
Writes
XGE_CPSW_P0_RX_DSCP_MAP_REG_PRI0, XGE_CPSW_P0_RX_DSCP_MAP_REG_PRI1, XGE_CPSW_P0_RX_DSCP_MAP_REG_PRI2, XGE_CPSW_P0_RX_DSCP_MAP_REG_PRI3, XGE_CPSW_P0_RX_DSCP_MAP_REG_PRI4, XGE_CPSW_P0_RX_DSCP_MAP_REG_PRI5, XGE_CPSW_P0_RX_DSCP_MAP_REG_PRI6, XGE_CPSW_P0_RX_DSCP_MAP_REG_PRI7,
XGE_CPSW_PN_RX_DSCP_MAP_REG_PRI0, XGE_CPSW_PN_RX_DSCP_MAP_REG_PRI1, XGE_CPSW_PN_RX_DSCP_MAP_REG_PRI2, XGE_CPSW_PN_RX_DSCP_MAP_REG_PRI3, XGE_CPSW_PN_RX_DSCP_MAP_REG_PRI4, XGE_CPSW_PN_RX_DSCP_MAP_REG_PRI5, XGE_CPSW_PN_RX_DSCP_MAP_REG_PRI6, XGE_CPSW_PN_RX_DSCP_MAP_REG_PRI7
@b Example
* Uint32 rxDscpPriMap [64], portNum;
portNum = 1;
for (i = 0; i < 64; i ++)
port0RxPriMap [i] = i/8;
CSL_CPSW_setPortRxDscpMap (portNum, rxDscpPriMap);| void CSL_CPSW_getEEEGlobConfig | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| CSL_CPSW_EEE_GLOB_CONFIG * | pGlobConfig | ||
| ) |
============================================================================
CSL_CPSW_getEEEGlobConfig
Description
This function retrieves the contents of the CPSW EEE Global Configuration.
Arguments
pGlobConfig CSL_CPSW_EEE_GLOB_CONFIG structure that needs to be populated
with the contents of the corresponging EEE global control
registers.
* Return Value
None
Pre Condition
None
Post Condition
None
Reads
XGE_CPSW_EEE_PRESCALE_REG_EEE_PRESCALE XGE_CPSW_CONTROL_REG_EEE_ENABLE
@b Example
CSL_CPSW_EEE_GLOB_CONFIG globConfig;
CSL_CPSW_getEEEGlobConfig (&globConfig);| void CSL_CPSW_setEEEGlobConfig | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| CSL_CPSW_EEE_GLOB_CONFIG * | pGlobConfig | ||
| ) |
============================================================================
CSL_CPSW_setEEEGlobConfig
Description
This function sets up the contents of the CPSW EEE related global registers per user-specified EEE Global Configuration.
Arguments
pGlobConfig CSL_CPSW_EEE_GLOB_CONFIG structure that holds the values
that need to be configured to the EEE global control
registers.
* Return Value
None
Pre Condition
None
Post Condition
CPSW EEE Global control register modified with values provided.
Writes
XGE_CPSW_EEE_PRESCALE_REG_EEE_PRESCALE XGE_CPSW_CONTROL_REG_EEE_ENABLE
Example
CSL_CPSW_EEE_GLOB_CONFIG globConfig;
globConfig.enable = 1;
globalConfig.prescale = 100;
...
CSL_CPSW_setEEEGlobConfig (&globConfig);| void CSL_CPSW_getEEEPortConfig | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| CSL_CPSW_EEE_PORT_CONFIG * | pPortConfig | ||
| ) |
============================================================================
CSL_CPSW_getEEEPortConfig
Description
This function retrieves the contents of the CPSW EEE Port Configuration.
Arguments
portNum CPSW port number for which the EEE Port Control
registers must be retrieved.
pPortConfig CSL_CPSW_EEE_PORT_CONFIG structure that needs to be populated
with the contents of the corresponging EEE port-specific control
registers.
* Return Value
None
Pre Condition
None
Post Condition
None
Reads
XGE_CPSW_P0_IDLE2LPI_REG_COUNT XGE_CPSW_P0_LPI2WAKE_REG_COUNT
XGE_CPSW_PN_IDLE2LPI_REG_COUNT XGE_CPSW_PN_LPI2WAKE_REG_COUNT XGE_CPSW_PN_CONTROL_REG_TX_LPI_CLKSTOP_EN
Example
Uint32 portNum;
CSL_CPSW_EEE_PORT_CONFIG portConfig;
portNum = 1;
CSL_CPSW_getEEEPortConfig (portNum, &portConfig);| void CSL_CPSW_setEEEPortConfig | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| CSL_CPSW_EEE_PORT_CONFIG * | pPortConfig | ||
| ) |
============================================================================
CSL_CPSW_setEEEPortConfig
Description
This function sets up the contents of the CPSW EEE port-specific control registers per user-specified EEE Port Configuration.
Arguments
portNum CPSW port number for which the EEE Port Control
registers must be configured.
pPortConfig CSL_CPSW_EEE_PORT_CONFIG structure holds the value
that needs to be configured to the EEE port-specific
control registers.
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
XGE_CPSW_P0_IDLE2LPI_REG_COUNT XGE_CPSW_P0_LPI2WAKE_REG_COUNT
XGE_CPSW_PN_IDLE2LPI_REG_COUNT XGE_CPSW_PN_LPI2WAKE_REG_COUNT XGE_CPSW_PN_CONTROL_REG_TX_LPI_CLKSTOP_EN
Example
Uint32 portNum;
CSL_CPSW_EEE_PORT_CONFIG portConfig;
portNum = 1;
portConfig.idle2lpi = 10;
portConfig.lpi2wake = 10;
portConfig.txLpiClkstopEnable = 1;
CSL_CPSW_setEEEPortConfig (portNum, &portConfig);| void CSL_CPSW_EEEPortStatus | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| CSL_CPSW_EEE_PORT_STATUS * | pPortStatus | ||
| ) |
============================================================================
CSL_CPSW_getEEEPortStatus
Description
This function retrieves the contents of the EEE port-specific Status register corresponding to the CPSW port specified.
Arguments
portNum CPSW port number for which the EEE status
must be retrieved.
pPortStatus CSL_CPSW_EEE_PORT_STATUS structure holds the EEE Port Status.
* Return Value
None
Pre Condition
None
Post Condition
None
Reads
XGE_CPSW_P0_EEE_STATUS_REG_WAIT_IDLE2LPI, XGE_CPSW_P0_EEE_STATUS_REG_RX_LPI, XGE_CPSW_P0_EEE_STATUS_REG_TX_LPI, XGE_CPSW_P0_EEE_STATUS_REG_TX_WAKE, XGE_CPSW_P0_EEE_STATUS_REG_TX_FIFO_HOLD, XGE_CPSW_P0_EEE_STATUS_REG_TX_FIFO_EMPTY, XGE_CPSW_P0_EEE_STATUS_REG_RX_FIFO_EMPTY,
XGE_CPSW_PN_EEE_STATUS_REG_WAIT_IDLE2LPI, XGE_CPSW_PN_EEE_STATUS_REG_RX_LPI, XGE_CPSW_PN_EEE_STATUS_REG_TX_LPI, XGE_CPSW_PN_EEE_STATUS_REG_TX_WAKE, XGE_CPSW_PN_EEE_STATUS_REG_TX_FIFO_HOLD, XGE_CPSW_PN_EEE_STATUS_REG_TX_FIFO_EMPTY, XGE_CPSW_PN_EEE_STATUS_REG_RX_FIFO_EMPTY
@b Example
* Uint32 portNum;
CSL_CPSW_EEE_PORT_STATUS portStatus;
portNum = 1;
CSL_CPSW_getEEEPortStatus (portNum, &portStatus);| void CSL_CPSW_getPortVlanReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| Uint32 * | pPortVID, | ||
| Uint32 * | pPortCFI, | ||
| Uint32 * | pPortPRI | ||
| ) |
============================================================================
CSL_CPSW_getPortVlanReg
Description
This function retrieves the contents of the VLAN Register corresponding to the CPSW port number specified.
Arguments
portNum CPSW port number for which the VLAN register
contents must be read
pPortVID Port VLAN Id
pPortCFI Port CFI bit
pPortPRI Port VLAN priority (0-7, 7 is highest priority)
* Return Value
None
Pre Condition
None
Post Condition
None
Reads
XGE_CPSW_P0_PORT_VLAN_REG_PORT_VID, XGE_CPSW_P0_PORT_VLAN_REG_PORT_CFI, XGE_CPSW_P0_PORT_VLAN_REG_PORT_PRI,
XGE_CPSW_PN_PORT_VLAN_REG_PORT_VID, XGE_CPSW_PN_PORT_VLAN_REG_PORT_CFI, XGE_CPSW_PN_PORT_VLAN_REG_PORT_PRI,
Example
* Uint32 portVID, portCFI, portPRI, portNum;
portNum = 1;
CSL_CPSW_getPortVlanReg (portNum, &portVID, &portCFI, &portPRI);| void CSL_CPSW_setPortVlanReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| Uint32 | portVID, | ||
| Uint32 | portCFI, | ||
| Uint32 | portPRI | ||
| ) |
============================================================================
CSL_CPSW_setPortVlanReg
Description
This function sets up the contents of the VLAN Register corresponding to the CPSW port number specified.
Arguments
portNum CPSW port number for which the VLAN register
must be configured.
portVID Port VLAN Id to be configured
portCFI Port CFI bit to be configured
portPRI Port VLAN priority to be configured
(0-7, 7 is highest priority)
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
XGE_CPSW_P0_PORT_VLAN_REG_PORT_VID, XGE_CPSW_P0_PORT_VLAN_REG_PORT_CFI, XGE_CPSW_P0_PORT_VLAN_REG_PORT_PRI,
XGE_CPSW_PN_PORT_VLAN_REG_PORT_VID, XGE_CPSW_PN_PORT_VLAN_REG_PORT_CFI, XGE_CPSW_PN_PORT_VLAN_REG_PORT_PRI,
Example
* Uint32 portVID, portCFI, portPRI, portNum;
portNum = 1;
portVID = 1;
portCFI = 0;
portPRI = 7;
CSL_CPSW_setPortVlanReg (portNum, portVID, portCFI, portPRI);| void CSL_CPSW_getPortMaxBlksReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| Uint32 * | pRxMaxBlks, | ||
| Uint32 * | pTxMaxBlks | ||
| ) |
============================================================================
CSL_CPSW_getPortMaxBlksReg
Description
This function retrieves the contents of the Port Maxmium Block register corresponding to the CPSW port specified.
Arguments
portNum CPSW port number for which the max block value
must be retrieved.
pRxMaxBlks Receive FIFO Maximum Blocks - This value is the
maximum number of 1k memory blocks that may be
allocated to the FIFO's logical receive queue.
This value must be greater than or equal to 0x3.
The recommended value of rx_max_blks is 0x9
pTxMaxBlks Transmit FIFO Maximum Blocks - This value is the
maximum number of 1k memory blocks that may be
allocated to the FIFO's logical transmit
priority queues. The recommended value of
tx_max_blks is 0x3.
* Return Value
None
Pre Condition
None
Post Condition
None
Reads
XGE_CPSW_PN_MAX_BLKS_REG_RX_MAX_BLKS, XGE_CPSW_PN_MAX_BLKS_REG_TX_MAX_BLKS,
Example
* Uint32 rxMaxBlks, txMaxBlks, portNum;
portNum = 1;
CSL_CPSW_getPortMaxBlksReg (portNum, &rxMaxBlks, &txMaxBlks);| void CSL_CPSW_setPortMaxBlksReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| Uint32 | rxMaxBlks, | ||
| Uint32 | txMaxBlks | ||
| ) |
============================================================================
CSL_CPSW_setPortMaxBlksReg
Description
This function sets up the contents of the Port Maxmium Block register corresponding to the CPSW port specified.
Arguments
portNum CPSW port number for which the max block value
must be retrieved.
rxMaxBlks Receive FIFO Maximum Blocks - This value is the
maximum number of 1k memory blocks that may be
allocated to the FIFO's logical receive queue.
This value must be greater than or equal to 0x3.
The recommended value of rx_max_blks is 0x9
txMaxBlks Transmit FIFO Maximum Blocks - This value is the
maximum number of 1k memory blocks that may be
allocated to the FIFO's logical transmit
priority queues. The recommended value of
tx_max_blks is 0x3.
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
XGE_CPSW_PN_MAX_BLKS_REG_RX_MAX_BLKS, XGE_CPSW_PN_MAX_BLKS_REG_TX_MAX_BLKS,
Example
* Uint32 rxMaxBlks, txMaxBlks, portNum;
portNum = 1;
CSL_CPSW_setPortMaxBlksReg (portNum, rxMaxBlks, txMaxBlks);| void CSL_CPSW_getPortMACAddress | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| Uint8 * | pMacAddress | ||
| ) |
============================================================================
CSL_CPSW_getPortMACAddress
Description
This function retreives the source MAC address of the Tx Pause Frame corresponding to the CPSW port number specified.
Arguments
portNum CPSW port number for which the source MAC address
must be read and returned. (1-8)
pMacAddress 6 byte Source MAC address read.
* Return Value
None
Pre Condition
The input parameter 'pMacAddres' must be large enough the 6 byte MAC address returned by this API.
Post Condition
None
Reads
XGE_CPSW_PN_SA_L_REG_MACSRCADDR_7_0, XGE_CPSW_PN_SA_L_REG_MACSRCADDR_15_8, XGE_CPSW_PN_SA_H_REG_MACSRCADDR_23_16, XGE_CPSW_PN_SA_H_REG_MACSRCADDR_31_24, XGE_CPSW_PN_SA_H_REG_MACSRCADDR_39_32, XGE_CPSW_PN_SA_H_REG_MACSRCADDR_47_40
Example
* Uint8 macAddress [6], portNum;
portNum = 1;
CSL_CPSW_getPortMACAddress (portNum, macAddress);| void CSL_CPSW_setPortMACAddress | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| Uint8 * | pMacAddress | ||
| ) |
============================================================================
CSL_CPSW_setPortMACAddress
Description
This function sets up the source MAC address the Tx Pause Frame corresponding to the CPSW port number specified.
Arguments
portNum CPSW port number for which the source MAC address
must be setup. (1-8)
pMacAddress 6 byte Source MAC address to configure.
* Return Value
None
Pre Condition
The input parameter 'pMacAddres' is expected to be 6 bytes long.
Post Condition
None
Writes
XGE_CPSW_PN_SA_L_REG_MACSRCADDR_7_0, XGE_CPSW_PN_SA_L_REG_MACSRCADDR_15_8, XGE_CPSW_PN_SA_H_REG_MACSRCADDR_23_16, XGE_CPSW_PN_SA_H_REG_MACSRCADDR_31_24, XGE_CPSW_PN_SA_H_REG_MACSRCADDR_39_32, XGE_CPSW_PN_SA_H_REG_MACSRCADDR_47_40
Example
* Uint8 macAddress [6], portNum;
portNum = 1;
macAddress [0] = 0x01;
macAddress [1] = 0x02;
macAddress [2] = 0x03;
macAddress [3] = 0x04;
macAddress [4] = 0x05;
macAddress [5] = 0x06;
CSL_CPSW_setPortMACAddress (portNum, macAddress);| void CSL_CPSW_getPortTimeSyncCntlReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| CSL_CPSW_TSCNTL * | pTimeSyncCntlCfg | ||
| ) |
============================================================================
CSL_CPSW_getPortTimeSyncCntlReg
Description
This function retreives the contents of Time sync control register corresponding to the CPSW port number specified.
Arguments
portNum CPSW port number for which the register must be read. (1-8)
pTimeSyncCntlCfg CSL_CPSW_TSCNTL that needs to be populated with
contents of time sync control register.
* Return Value
None
Pre Condition
None
Post Condition
None
Reads
XGE_CPSW_PN_TS_CTL_REG_TS_RX_ANNEX_F_EN, XGE_CPSW_PN_TS_CTL_REG_TS_RX_VLAN_LTYPE1_EN, XGE_CPSW_PN_TS_CTL_REG_TS_RX_VLAN_LTYPE2_EN, XGE_CPSW_PN_TS_CTL_REG_TS_RX_ANNEX_D_EN, XGE_CPSW_PN_TS_CTL_REG_TS_TX_ANNEX_F_EN, XGE_CPSW_PN_TS_CTL_REG_TS_TX_VLAN_LTYPE1_EN, XGE_CPSW_PN_TS_CTL_REG_TS_TX_VLAN_LTYPE2_EN, XGE_CPSW_PN_TS_CTL_REG_TS_TX_ANNEX_D_EN, XGE_CPSW_PN_TS_CTL_REG_TS_LTYPE2_EN, XGE_CPSW_PN_TS_CTL_REG_TS_RX_ANNEX_E_EN, XGE_CPSW_PN_TS_CTL_REG_TS_TX_ANNEX_E_EN, XGE_CPSW_PN_TS_CTL_REG_TS_TX_HOST_TS_EN, XGE_CPSW_PN_TS_CTL_REG_TS_MSG_TYPE_EN
Example
* Uint32 portNum;
CSL_CPSW_TSCNTL tsCtlCfg;
portNum = 1;
CSL_CPSW_getPortTimeSyncCntlReg (portNum, &tsCtlCfg);| void CSL_CPSW_setPortTimeSyncCntlReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| CSL_CPSW_TSCNTL * | pTimeSyncCntlCfg | ||
| ) |
============================================================================
CSL_CPSW_setPortTimeSyncCntlReg
Description
This function sets up the contents of Time sync control register corresponding to the CPSW port number specified.
Arguments
portNum CPSW port number for which the register must be
configured.
pTimeSyncCntlCfg CSL_CPSW_TSCNTL containing settings for time
sync control register.
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
XGE_CPSW_PN_TS_CTL_REG_TS_RX_ANNEX_F_EN, XGE_CPSW_PN_TS_CTL_REG_TS_RX_VLAN_LTYPE1_EN, XGE_CPSW_PN_TS_CTL_REG_TS_RX_VLAN_LTYPE2_EN, XGE_CPSW_PN_TS_CTL_REG_TS_RX_ANNEX_D_EN, XGE_CPSW_PN_TS_CTL_REG_TS_TX_ANNEX_F_EN, XGE_CPSW_PN_TS_CTL_REG_TS_TX_VLAN_LTYPE1_EN, XGE_CPSW_PN_TS_CTL_REG_TS_TX_VLAN_LTYPE2_EN, XGE_CPSW_PN_TS_CTL_REG_TS_TX_ANNEX_D_EN, XGE_CPSW_PN_TS_CTL_REG_TS_LTYPE2_EN, XGE_CPSW_PN_TS_CTL_REG_TS_RX_ANNEX_E_EN, XGE_CPSW_PN_TS_CTL_REG_TS_TX_ANNEX_E_EN, XGE_CPSW_PN_TS_CTL_REG_TS_TX_HOST_TS_EN, XGE_CPSW_PN_TS_CTL_REG_TS_MSG_TYPE_EN
Example
* Uint32 portNum;
CSL_CPSW_TSCNTL tsCtlCfg;
portNum = 1;
tsCtlCfg.tsRxVlanLType1Enable = 0;
tsCtlCfg.tsRxVlanLType2Enable = 0;
...
CSL_CPSW_setPortTimeSyncCntlReg (portNum, &tsCtlCfg);| void CSL_CPSW_getPortTimeSyncSeqIdReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| Uint32 * | pTsLtype, | ||
| Uint32 * | pTsSeqIdOffset | ||
| ) |
============================================================================
CSL_CPSW_getPortTimeSyncSeqIdReg
Description
This function retreives the contents of Time Sync Sequence Id and LTYPE register corresponding to the CPSW port number specified.
Arguments
portNum CPSW port number for which the register must be read. (1-8)
pTsLtype Time sync LTYPE read.
pTsSeqIdOffset Time sync sequence Id offset read.
* Return Value
None
Pre Condition
None
Post Condition
None
Reads
XGE_CPSW_PN_TS_SEQ_LTYPE_REG_TS_LTYPE1, XGE_CPSW_PN_TS_SEQ_LTYPE_REG_TS_SEQ_ID_OFFSET
Example
* Uint32 portNum, tsLtype, tsSeqIdOffset;
portNum = 1;
CSL_CPSW_getPortTimeSyncSeqIdReg (portNum, &tsLtype, &tsSeqIdOffset);| void CSL_CPSW_getVlanLTypeReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 * | pVlanLtypeInner, | ||
| Uint32 * | pVlanLtypeOuter | ||
| ) |
| void CSL_CPSW_setVlanLTypeReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | pVlanLtypeInner, | ||
| Uint32 | pVlanLtypeOuter | ||
| ) |
============================================================================
CSL_CPSW_setVlanLTypeReg
Description
This function retreives the contents of VLAN_LTYPE_REG register.
Arguments
pVlanLtype1 VLAN LTYPE1 value read.
pVlanLtype2 VLAN LTYPE2 value read.
* Return Value
None
Pre Condition
None
Post Condition
None
Reads
XGE_CPSW_VLAN_LTYPE_REG_VLAN_LTYPE_INNER, XGE_CPSW_VLAN_LTYPE_REG_VLAN_LTYPE_OUTER
Example
* Uint32 portNum, tsLtype1, tsLtype2;
portNum = 1;
CSL_CPSW_setVlanLTypeReg (portNum, &tsLtype1, &tsLtype2);| void CSL_CPSW_setPortTimeSyncSeqIdReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| Uint32 | tsLtype, | ||
| Uint32 | tsSeqIdOffset | ||
| ) |
============================================================================
CSL_CPSW_setPortTimeSyncSeqIdReg
Description
This function sets up the contents of Time Sync Sequence Id and LTYPE register corresponding to the CPSW port number specified.
Arguments
portNum CPSW port number for which the register must be
configured. (1-8)
tsLtype Time sync LTYPE to be configured.
tsSeqIdOffset Time sync sequence Id offset to be configured.
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
XGE_CPSW_PN_TS_SEQ_LTYPE_REG_TS_LTYPE1, XGE_CPSW_PN_TS_SEQ_LTYPE_REG_TS_SEQ_ID_OFFSET
Example
* Uint32 portNum, tsLtype, tsSeqIdOffset;
portNum = 1;
tsLtype = 0;
tsSeqIdOffset = 30;
CSL_CPSW_getPortTimeSyncSeqIdReg (portNum, tsLtype, tsSeqIdOffset);| void CSL_CPSW_getPortTimeSyncVlanLTypeReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| Uint32 * | pTsVlanLtype1, | ||
| Uint32 * | pTsVlanLtype2 | ||
| ) |
============================================================================
CSL_CPSW_getPortTimeSyncVlanLTypeReg
Description
This function retreives the contents of Time Sync VLAN LTYPE register corresponding to the CPSW port number specified.
Arguments
portNum CPSW port number for which the register must be read. (1-8)
pTsVlanLtype1 Time sync VLAN LTYPE1 value read.
pTsVlanLtype2 Time sync VLAN LTYPE2 value read.
* Return Value
None
Pre Condition
None
Post Condition
None
Reads
XGE_CPSW_PN_TS_VLAN_LTYPE_REG_TS_VLAN_LTYPE1, XGE_CPSW_PN_TS_VLAN_LTYPE_REG_TS_VLAN_LTYPE2
Example
* Uint32 portNum, tsLtype1, tsLtype2;
portNum = 1;
CSL_CPSW_getPortTimeSyncVlanLTypeReg (portNum, &tsLtype1, &tsLtype2);| void CSL_CPSW_setPortTimeSyncVlanLTypeReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| Uint32 | tsVlanLtype1, | ||
| Uint32 | tsVlanLtype2 | ||
| ) |
============================================================================
CSL_CPSW_setPortTimeSyncVlanLTypeReg
Description
This function sets up the contents of Time Sync VLAN LTYPE register corresponding to the CPSW port number specified.
Arguments
portNum CPSW port number for which the register must be read. (1-8)
tsVlanLtype1 Time sync VLAN LTYPE1 value to be configured.
tsVlanLtype2 Time sync VLAN LTYPE2 value to be configured.
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
XGE_CPSW_PN_TS_VLAN_LTYPE_REG_TS_VLAN_LTYPE1, XGE_CPSW_PN_TS_VLAN_LTYPE_REG_TS_VLAN_LTYPE2
Example
* Uint32 portNum, tsLtype1, tsLtype2;
portNum = 1;
tsLtype1 = 0x8100;
tsLtype2 = 0x8100;
CSL_CPSW_setPortTimeSyncVlanLTypeReg (portNum, &tsLtype1, &tsLtype2);| void CSL_CPSW_getPortTimeSyncConfig | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| CSL_CPSW_TSCONFIG * | pTimeSyncConfig | ||
| ) |
============================================================================
CSL_CPSW_getPortTimeSyncCntlReg
Description
This function retreives the contents of Time sync configuration from time sync control registers corresponding to the CPSW port number specified.
Arguments
portNum CPSW port number for which the registers must be read. (1-8)
pTimeSyncConfig CSL_CPSW_TSCONFIG that needs to be populated with
contents of time sync control registers.
* Return Value
None
Pre Condition
None
Post Condition
None
Reads
XGE_CPSW_PN_TS_CTL_REG_TS_RX_ANNEX_F_EN, XGE_CPSW_PN_TS_CTL_REG_TS_RX_VLAN_LTYPE1_EN, XGE_CPSW_PN_TS_CTL_REG_TS_RX_VLAN_LTYPE2_EN, XGE_CPSW_PN_TS_CTL_REG_TS_RX_ANNEX_D_EN, XGE_CPSW_PN_TS_CTL_REG_TS_TX_ANNEX_F_EN, XGE_CPSW_PN_TS_CTL_REG_TS_TX_VLAN_LTYPE1_EN, XGE_CPSW_PN_TS_CTL_REG_TS_TX_VLAN_LTYPE2_EN, XGE_CPSW_PN_TS_CTL_REG_TS_TX_ANNEX_D_EN, XGE_CPSW_PN_TS_CTL_REG_TS_LTYPE2_EN, XGE_CPSW_PN_TS_CTL_REG_TS_RX_ANNEX_E_EN, XGE_CPSW_PN_TS_CTL_REG_TS_TX_ANNEX_E_EN, XGE_CPSW_PN_TS_CTL_REG_TS_TX_HOST_TS_EN, XGE_CPSW_PN_TS_CTL_REG_TS_MSG_TYPE_EN,
XGE_CPSW_PN_TS_SEQ_LTYPE_REG_TS_LTYPE1, XGE_CPSW_PN_TS_SEQ_LTYPE_REG_TS_SEQ_ID_OFFSET,
XGE_CPSW_PN_TS_VLAN_LTYPE_REG_TS_VLAN_LTYPE1, XGE_CPSW_PN_TS_VLAN_LTYPE_REG_TS_VLAN_LTYPE2,
XGE_CPSW_PN_TS_CTL_LTYPE2_REG_TS_LTYPE2, XGE_CPSW_PN_TS_CTL_LTYPE2_REG_TS_107, XGE_CPSW_PN_TS_CTL_LTYPE2_REG_TS_129, XGE_CPSW_PN_TS_CTL_LTYPE2_REG_TS_130, XGE_CPSW_PN_TS_CTL_LTYPE2_REG_TS_131, XGE_CPSW_PN_TS_CTL_LTYPE2_REG_TS_132, XGE_CPSW_PN_TS_CTL_LTYPE2_REG_TS_319, XGE_CPSW_PN_TS_CTL_LTYPE2_REG_TS_330, XGE_CPSW_PN_TS_CTL_LTYPE2_REG_TS_TTL_NONZERO, XGE_CPSW_PN_TS_CTL_LTYPE2_REG_TS_UNI_EN,
XGE_CPSW_PN_TS_CTL2_REG_TS_MCAST_TYPE_EN, XGE_CPSW_PN_TS_CTL2_REG_TS_DOMAIN_OFFSET
Example
* Uint32 portNum;
CSL_CPSW_TSCONFIG tsConfig;
portNum = 1;
CSL_CPSW_getPortTimeSyncCntlReg (portNum, &tsConfig);| void CSL_CPSW_setPortTimeSyncConfig | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| CSL_CPSW_TSCONFIG * | pTimeSyncConfig | ||
| ) |
============================================================================
CSL_CPSW_setPortTimeSyncConfig
Description
This function sets up the contents of Time sync control registers corresponding to the CPSW port number specified per user configuration.
Arguments
portNum CPSW port number for which the registers must be
configured.
pTimeSyncConfig CSL_CPSW_TSCONFIG containing settings for time
sync control registers.
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
XGE_CPSW_PN_TS_CTL_REG_TS_RX_ANNEX_F_EN, XGE_CPSW_PN_TS_CTL_REG_TS_RX_VLAN_LTYPE1_EN, XGE_CPSW_PN_TS_CTL_REG_TS_RX_VLAN_LTYPE2_EN, XGE_CPSW_PN_TS_CTL_REG_TS_RX_ANNEX_D_EN, XGE_CPSW_PN_TS_CTL_REG_TS_TX_ANNEX_F_EN, XGE_CPSW_PN_TS_CTL_REG_TS_TX_VLAN_LTYPE1_EN, XGE_CPSW_PN_TS_CTL_REG_TS_TX_VLAN_LTYPE2_EN, XGE_CPSW_PN_TS_CTL_REG_TS_TX_ANNEX_D_EN, XGE_CPSW_PN_TS_CTL_REG_TS_LTYPE2_EN, XGE_CPSW_PN_TS_CTL_REG_TS_RX_ANNEX_E_EN, XGE_CPSW_PN_TS_CTL_REG_TS_TX_ANNEX_E_EN, XGE_CPSW_PN_TS_CTL_REG_TS_TX_HOST_TS_EN, XGE_CPSW_PN_TS_CTL_REG_TS_MSG_TYPE_EN
XGE_CPSW_PN_TS_SEQ_LTYPE_REG_TS_LTYPE1, XGE_CPSW_PN_TS_SEQ_LTYPE_REG_TS_SEQ_ID_OFFSET,
XGE_CPSW_PN_TS_VLAN_LTYPE_REG_TS_VLAN_LTYPE1, XGE_CPSW_PN_TS_VLAN_LTYPE_REG_TS_VLAN_LTYPE2,
XGE_CPSW_PN_TS_CTL_LTYPE2_REG_TS_LTYPE2, XGE_CPSW_PN_TS_CTL_LTYPE2_REG_TS_107, XGE_CPSW_PN_TS_CTL_LTYPE2_REG_TS_129, XGE_CPSW_PN_TS_CTL_LTYPE2_REG_TS_130, XGE_CPSW_PN_TS_CTL_LTYPE2_REG_TS_131, XGE_CPSW_PN_TS_CTL_LTYPE2_REG_TS_132, XGE_CPSW_PN_TS_CTL_LTYPE2_REG_TS_319, XGE_CPSW_PN_TS_CTL_LTYPE2_REG_TS_330, XGE_CPSW_PN_TS_CTL_LTYPE2_REG_TS_TTL_NONZERO, XGE_CPSW_PN_TS_CTL_LTYPE2_REG_TS_UNI_EN,
XGE_CPSW_PN_TS_CTL2_REG_TS_MCAST_TYPE_EN, XGE_CPSW_PN_TS_CTL2_REG_TS_DOMAIN_OFFSET
Example
* Uint32 portNum;
CSL_CPSW_TSCONFIG tsConfig;
portNum = 1;
tsConfig.tsRxVlanLType1Enable = 0;
tsConfig.tsRxVlanLType2Enable = 0;
...
CSL_CPSW_setPortTimeSyncConfig (portNum, &tsConfig);| void CSL_CPSW_getStats | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| CSL_CPSW_STATS * | pCpswStats | ||
| ) |
============================================================================
CSL_CPSW_getStats
Description
The CPSW stats are divided into 9 blocks, i.e., Stats for Host port (switch Port 0) and Stats for CPSW ports (Port 1-8 ). This function
@b Arguments
pCpswStats Array of CSL_CPSW_STATS structure that needs to be filled
with the stats read from the hardware. This function expects
that the array passed to it is big enough to hold the stats
for all stat blocks, i.e., size of array passed to this
function must be 5 or 9 for 5/9 port switch respectively.
* Return Value
None
Pre Condition
None
Post Condition
None
Reads
CPSW_RXGOODFRAMES, CPSW_RXBROADCASTFRAMES, CPSW_RXMULTICASTFRAMES, CPSW_RXPAUSEFRAMES, CPSW_RXCRCERRORS, CPSW_RXALIGNCODEERRORS, CPSW_RXOVERSIZEDFRAMES, CPSW_RXJABBERFRAMES, CPSW_RXUNDERSIZEDFRAMES, CPSW_RXFRAGMENTS, CPSW_ALE_DROP, CPSW_ALE_OVERRUN_DROP, CPSW_RXOCTETS, CPSW_TXGOODFRAMES, CPSW_TXBROADCASTFRAMES, CPSW_TXMULTICASTFRAMES, CPSW_TXPAUSEFRAMES, CPSW_TXDEFERREDFRAMES, CPSW_TXCOLLISIONFRAMES, CPSW_TXSINGLECOLLFRAMES, CPSW_TXMULTCOLLFRAMES, CPSW_TXEXCESSIVECOLLISIONS, CPSW_TXLATECOLLISIONS, CPSW_TXUNDERRUN, CPSW_TXCARRIERSENSEERRORS, CPSW_TXOCTETS, CPSW_OCTETFRAMES64, CPSW_OCTETFRAMES65T127, CPSW_OCTETFRAMES128T255, CPSW_OCTETFRAMES256T511, CPSW_OCTETFRAMES512T1023, CPSW_OCTETFRAMES1024TUP, CPSW_NETOCTETS, CPSW_RX_BOTTOM_OF_FIFO_DROP, CPSW_PORTMASK_DROP, CPSW_RX_TOP_OF_FIFO_DROP, CPSW_ALE_ALE_RATE_LIMIT_DROP, CPSW_ALE_VID_INGRESS_DROP, CPSW_ALE_DA_EQ_SA_DROP, CPSW_ALE_UNKN_UNI, CPSW_ALE_UNKN_UNI_BCNT, CPSW_ALE_UNKN_MLT, CPSW_ALE_UNKN_MLT_BCNT, CPSW_ALE_UNKN_BRD, CPSW_ALE_UNKN_BRD_BCNT, CPSW_ALE_POLL_MATCH, CPSW_TX_MEMORY_PROTECT_ERROR
Affects
CPSW_RXGOODFRAMES=0, CPSW_RXBROADCASTFRAMES=0, CPSW_RXMULTICASTFRAMES=0, CPSW_RXPAUSEFRAMES=0, CPSW_RXCRCERRORS=0, CPSW_RXALIGNCODEERRORS=0, CPSW_RXOVERSIZEDFRAMES=0, CPSW_RXJABBERFRAMES=0, CPSW_RXUNDERSIZEDFRAMES=0, CPSW_RXFRAGMENTS=0, CPSW_ALE_DROP=0, CPSW_ALE_OVERRUN_DROP=0, CPSW_RXOCTETS=0, CPSW_TXGOODFRAMES=0, CPSW_TXBROADCASTFRAMES=0, CPSW_TXMULTICASTFRAMES=0, CPSW_TXPAUSEFRAMES=0, CPSW_TXDEFERREDFRAMES=0, CPSW_TXCOLLISIONFRAMES=0, CPSW_TXSINGLECOLLFRAMES=0, CPSW_TXMULTCOLLFRAMES=0, CPSW_TXEXCESSIVECOLLISIONS=0, CPSW_TXLATECOLLISIONS=0, CPSW_TXUNDERRUN=0, CPSW_TXCARRIERSENSEERRORS=0, CPSW_TXOCTETS=0, CPSW_OCTETFRAMES64=0, CPSW_OCTETFRAMES65T127=0, CPSW_OCTETFRAMES128T255=0, CPSW_OCTETFRAMES256T511=0, CPSW_OCTETFRAMES512T1023=0, CPSW_OCTETFRAMES1024TUP=0, CPSW_NETOCTETS=0, CPSW_RX_BOTTOM_OF_FIFO_DROP=0, CPSW_PORTMASK_DROP=0, CPSW_RX_TOP_OF_FIFO_DROP=0, CPSW_ALE_ALE_RATE_LIMIT_DROP=0, CPSW_ALE_VID_INGRESS_DROP=0, CPSW_ALE_DA_EQ_SA_DROP=0, CPSW_ALE_UNKN_UNI=0, CPSW_ALE_UNKN_UNI_BCNT=0, CPSW_ALE_UNKN_MLT=0, CPSW_ALE_UNKN_MLT_BCNT=0, CPSW_ALE_UNKN_BRD=0, CPSW_ALE_UNKN_BRD_BCNT=0, CPSW_ALE_POLL_MATCH=0, CPSW_TX_MEMORY_PROTECT_ERROR=0
Example
* CSL_CPSW_STATS stats [9];
CSL_CPSW_getStats (stats);| void CSL_CPSW_getPortStats | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| CSL_CPSW_STATS * | pCpswStats | ||
| ) |
| void CSL_CPSW_getRawStats | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| CSL_CPSW_STATS * | pCpswStats | ||
| ) |
============================================================================
CSL_CPSW_getRawStats
Description
The CPSW stats are divided into 9 blocks, i.e., Stats for Host port (switch Port 0) and Stats for MAC ports (Port 1-8). This function retreives snapshot of hardware statistics for all the stat blocks. In the case of Linux ARM master use case all CPSW stats is recommended to be accessed from Linux.
Since this function does not clear the stats, its possible to have non-exclusive ownership of the switch and use this function without corrupting other caller's view of the stats.
Additional Note: In order to avoid stats loss due to rollovers, application would need to poll the stats by determining the correct interval. The stat CPSW_NETOCTETS would be first one to roll over The software must poll and accumulate the stats faster than this rate. On a 1 gigabit network, it takes approximately (0x100000000/(1000000000/8)/2)=17 seconds to roll over (the /2 is because this stat contains both tx and rx, both of which run at gigabit). A good rule of thumb is to poll at twice this rate (8-9 seconds).
If it is really necessary for application to have multiple nonexclusive owners of the switch, it is possible for all callers to have a view of the accumulated statistics if they (including Linux) follows the differential accumulation of the stats defiened below: uint64_t accum_CPSW_NETOCTETS; uint32_t old_CPSW_NETOCTETS, new_CPSW_NETOCTETS, diff_CPSW_NETOCTETS;
diff_CPSW_NETOCTETS = new_CPSW_NETOCTETS - old_CPSW_NETOCTETS; // let rollover occur, no "if" required old_CPSW_NETOCTETS = new_CPSW_NETOCTETS; accum_CPSW_NETOCTETS += diff_CPSW_NETOCTETS
Arguments
pCpswStats Array of CSL_CPSW_STATS structure that needs to be filled
with the stats read from the hardware. This function expects
that the array passed to it is big enough to hold the stats
for both stat blocks, i.e., size of array passed to this
function must be 5 or 9 for 5-port/9-port switch respectively.
* Return Value
None
Pre Condition
None
Post Condition
None
Reads
CPSW_RXGOODFRAMES, CPSW_RXBROADCASTFRAMES, CPSW_RXMULTICASTFRAMES, CPSW_RXPAUSEFRAMES, CPSW_RXCRCERRORS, CPSW_RXALIGNCODEERRORS, CPSW_RXOVERSIZEDFRAMES, CPSW_RXJABBERFRAMES, CPSW_RXUNDERSIZEDFRAMES, CPSW_RXFRAGMENTS, CPSW_ALE_DROP, CPSW_ALE_OVERRUN_DROP, CPSW_RXOCTETS, CPSW_TXGOODFRAMES, CPSW_TXBROADCASTFRAMES, CPSW_TXMULTICASTFRAMES, CPSW_TXPAUSEFRAMES, CPSW_TXDEFERREDFRAMES, CPSW_TXCOLLISIONFRAMES, CPSW_TXSINGLECOLLFRAMES, CPSW_TXMULTCOLLFRAMES, CPSW_TXEXCESSIVECOLLISIONS, CPSW_TXLATECOLLISIONS, CPSW_TXUNDERRUN, CPSW_TXCARRIERSENSEERRORS, CPSW_TXOCTETS, CPSW_OCTETFRAMES64, CPSW_OCTETFRAMES65T127, CPSW_OCTETFRAMES128T255, CPSW_OCTETFRAMES256T511, CPSW_OCTETFRAMES512T1023, CPSW_OCTETFRAMES1024TUP, CPSW_NETOCTETS, CPSW_RX_BOTTOM_OF_FIFO_DROP, CPSW_PORTMASK_DROP, CPSW_RX_TOP_OF_FIFO_DROP, CPSW_ALE_ALE_RATE_LIMIT_DROP, CPSW_ALE_VID_INGRESS_DROP, CPSW_ALE_DA_EQ_SA_DROP, CPSW_ALE_UNKN_UNI, CPSW_ALE_UNKN_UNI_BCNT, CPSW_ALE_UNKN_MLT, CPSW_ALE_UNKN_MLT_BCNT, CPSW_ALE_UNKN_BRD, CPSW_ALE_UNKN_BRD_BCNT, CPSW_ALE_POLL_MATCH, CPSW_TX_MEMORY_PROTECT_ERROR
Example
* CSL_CPSW_STATS stats [9];
CSL_CPSW_getRawStats (stats);| void CSL_CPSW_getPortRawStats | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNum, | ||
| CSL_CPSW_STATS * | pCpswStats | ||
| ) |
| void CSL_CPSW_getAleVersionInfo | ( | CSL_AleRegs * | hCpswAleRegs, |
| CSL_CPSW_ALE_VERSION * | pVersionInfo | ||
| ) |
============================================================================
CSL_CPSW_getAleVersionInfo
Description
This function retrieves the ALE submodule identification and version information.
Arguments
pVersionInfo CSL_CPSW_ALE_VERSION structure that needs to be populated
with the ALE version info read from the hardware.
* Return Value
None
Pre Condition
None
Post Condition
None
Reads
ALE_MOD_VER_MINOR_REVISION, ALE_MOD_VER_MAJOR_REVISION, ALE_MOD_VER_RTL_VERSION, ALE_MOD_VER_MODULE_ID
Example
CSL_CPSW_ALE_VERSION versionInfo;
CSL_CPSW_getAleVersionInfo (&versionInfo);| Uint32 CSL_CPSW_isAleRateLimitEnabled | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_isAleRateLimitEnabled
Description
This function indicates if ALE Broadcast and Multicast Rate Limit is enabled.
Arguments
None
Return Value
TRUE ALE Broadcast and multicast rate limit enabled. Broadcast/multicast packet reception limited to port control register rate limit fields.
FALSE ALE Broadcast and multicast rate limit disabled. Broadcast/multicast rates not limited.
Pre Condition
None
Post Condition
None
Reads
ALE_ALE_CONTROL_ENABLE_RATE_LIMIT
Example
if (CSL_CPSW_isAleRateLimitEnabled () == TRUE)
{
// ALE Broadcast/Multicast rate limit enabled
}
else
{
// ALE Broadcast/Multicast rate limit disabled
}| void CSL_CPSW_enableAleRateLimit | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_enableAleRateLimit
Description
This function configures the ALE control register to enable multicast, broadcast rate limiting.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_CONTROL_ENABLE_RATE_LIMIT=1
Example
CSL_CPSW_enableAleRateLimit ();
| void CSL_CPSW_disableAleRateLimit | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_disableAleRateLimit
Description
This function configures the ALE control register to disable multicast, broadcast rate limiting.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_CONTROL_ENABLE_RATE_LIMIT=0
Example
CSL_CPSW_disableAleRateLimit ();
| Uint32 CSL_CPSW_isAleMacAuthModeEnabled | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_isAleMacAuthModeEnabled
Description
This function indicates if ALE MAC Authorization mode is enabled.
Arguments
None
Return Value
TRUE ALE is in MAC authorization mode.
FALSE ALE not in MAC authorization mode.
Pre Condition
None
Post Condition
None
Reads
ALE_ALE_CONTROL_ENABLE_AUTH_MODE
Example
if (CSL_CPSW_isAleMacAuthModeEnabled () == TRUE);
{
// ALE is in MAC authorization mode
}
else
{
// ALE not in MAC authorization mode
}| void CSL_CPSW_enableAleMacAuthMode | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_enableAleMacAuthMode
Description
This function configures the ALE control register to enable MAC authorization mode.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_CONTROL_ENABLE_AUTH_MODE=1
Example
CSL_CPSW_enableAleMacAuthMode ();
| void CSL_CPSW_disableAleMacAuthMode | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_disableAleMacAuthMode
Description
This function configures the ALE control register to disable MAC authorization mode.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_CONTROL_ENABLE_AUTH_MODE=0
Example
CSL_CPSW_disableAleMacAuthMode ();
| Uint32 CSL_CPSW_isAleVlanAwareEnabled | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_isAleVlanAwareEnabled
Description
This function indicates if ALE is programmed to be VLAN aware.
Arguments
None
Return Value
TRUE ALE VLAN aware. ALE drops packets if VLAN not found.
FALSE ALE not VLAN aware. Floods if VLAN not found.
Pre Condition
None
Post Condition
None
Reads
ALE_ALE_CONTROL_ALE_VLAN_AWARE
Example
if (CSL_CPSW_isAleVlanAwareEnabled () == TRUE)
{
// ALE VLAN aware
}
else
{
// ALE not VLAN aware
}| void CSL_CPSW_enableAleVlanAware | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_enableAleVlanAware
Description
This function configures the ALE control register to enable VLAN aware mode.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_CONTROL_ALE_VLAN_AWARE=1
Example
CSL_CPSW_enableAleVlanAware ();
| void CSL_CPSW_disableAleVlanAware | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_disableAleVlanAware
Description
This function configures the ALE control register to disable VLAN aware mode.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_CONTROL_ALE_VLAN_AWARE=0
Example
CSL_CPSW_disableAleVlanAware ();
| Uint32 CSL_CPSW_isAleTxRateLimitEnabled | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_isAleTxRateLimitEnabled
Description
This function indicates if ALE is programmed to be Tx-port based multicast, broadcast rate limited.
Arguments
None
Return Value
TRUE ALE Tx rate limit enabled. Broadcast, multicast rate limit counters are transmit port based.
FALSE ALE Tx rate limit disabled. Broadcast, multicast rate limit counters are receive port based.
Pre Condition
ALE_ALE_CONTROL_ENABLE_RATE_LIMIT=1
Post Condition
None
Reads
ALE_ALE_CONTROL_BCAST_MCAST_CTL
Example
if (CSL_CPSW_isAleTxRateLimitEnabled () == TRUE)
{
// ALE Tx rate limit on
}
else
{
// ALE Tx rate limit off
}| void CSL_CPSW_enableAleTxRateLimit | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_enableAleTxRateLimit
Description
This function configures the ALE control register to select Tx-port based multicast, broadcast rate limiting
Arguments
None
Return Value
None
Pre Condition
ALE_ALE_CONTROL_ENABLE_RATE_LIMIT=1
Post Condition
None
Writes
ALE_ALE_CONTROL_BCAST_MCAST_CTL=1
Example
CSL_CPSW_enableAleTxRateLimit ();
| void CSL_CPSW_disableAleTxRateLimit | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_disableAleTxRateLimit
Description
This function configures the ALE control register to select Rx-port based multicast, broadcast rate limiting
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_CONTROL_BCAST_MCAST_CTL=0
Example
CSL_CPSW_disableAleTxRateLimit ();
| Uint32 CSL_CPSW_isAleBypassEnabled | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_isAleBypassEnabled
Description
This function indicates if ALE is programmed to be in Bypass mode.
Arguments
None
Return Value
TRUE ALE Bypass mode enabled.
FALSE ALE Bypass mode disabled.
Pre Condition
None
Post Condition
None
Reads
ALE_ALE_CONTROL_ENABLE_BYPASS
Example
if (CSL_CPSW_isAleBypassEnabled () == TRUE)
{
// ALE Bypass mode on
}
else
{
// ALE Bypass mode off
}| void CSL_CPSW_enableAleBypass | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_enableAleBypass
Description
This function configures the ALE control register to enable Bypass mode.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_CONTROL_ENABLE_BYPASS=1
Example
CSL_CPSW_enableAleBypass ();
| void CSL_CPSW_disableAleBypass | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_disableAleBypass
Description
This function configures the ALE control register to disable Bypass mode.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_CONTROL_ENABLE_BYPASS=0
Example
CSL_CPSW_disableAleBypass ();
| Uint32 CSL_CPSW_isAleOUIDenyModeEnabled | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_isAleOUIDenyModeEnabled
Description
This function indicates if ALE is programmed to be in OUI deny mode.
Arguments
None
Return Value
TRUE ALE OUI deny mode enabled.
FALSE ALE OUI deny mode disabled.
Pre Condition
None
Post Condition
None
Reads
ALE_ALE_CONTROL_ENABLE_OUI_DENY
Example
if (CSL_CPSW_isAleOUIDenyModeEnabled () == TRUE)
{
// ALE OUI deny mode on
}
else
{
// ALE OUI deny mode off
}| void CSL_CPSW_enableAleOUIDenyMode | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_enableAleOUIDenyMode
Description
This function configures the ALE control register to enable OUI deny mode.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_CONTROL_ENABLE_OUI_DENY=1
Example
CSL_CPSW_enableAleOUIDenyMode ();
| void CSL_CPSW_disableAleOUIDenyMode | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_disableAleOUIDenyMode
Description
This function configures the ALE control register to disable OUI deny mode.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_CONTROL_ENABLE_OUI_DENY=0
Example
CSL_CPSW_disableAleOUIDenyMode ();
| Uint32 CSL_CPSW_isAleVID0ModeEnabled | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_isAleVID0ModeEnabled
Description
This function indicates if ALE is programmed to be in VID0 (VLAN ID=0) mode.
Arguments
None
Return Value
TRUE ALE VID0 mode enabled. Process the packet with VLAN Id = 0
FALSE ALE VID0 mode disabled. Process the packet with VLAN Id =PORT_VLAN[11-0]
Pre Condition
None
Post Condition
None
Reads
ALE_ALE_CONTROL_ENABLE_VID0_MODE
Example
if (CSL_CPSW_isAleVID0ModeEnabled () == TRUE)
{
// ALE VID0 mode on
}
else
{
// ALE VID0 mode off
}| void CSL_CPSW_enableAleVID0Mode | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_enableAleVID0Mode
Description
This function configures the ALE control register to enable VID0 mode.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_CONTROL_ENABLE_VID0_MODE=1
Example
CSL_CPSW_enableAleVID0Mode ();
| void CSL_CPSW_disableAleVID0Mode | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_disableAleVID0Mode
Description
This function configures the ALE control register to disable VID0 mode.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_CONTROL_ENABLE_VID0_MODE=0
Example
CSL_CPSW_disableAleVID0Mode ();
| Uint32 CSL_CPSW_isAleLearnNoVIDEnabled | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_isAleLearnNoVIDEnabled
Description
This function indicates if ALE is programmed to not learn VLAN Ids.
Arguments
None
Return Value
TRUE ALE Learn no VID enabled. VLAN Id is not learned with source address (source address is not tied to VID)
FALSE ALE VID learning mode enabled.
Pre Condition
None
Post Condition
None
Reads
ALE_ALE_CONTROL_LEARN_NO_VLANID
Example
if (CSL_CPSW_isAleLearnNoVIDEnabled () == TRUE)
{
// ALE VID learning disabled
}
else
{
// ALE VID learning enabled
}| void CSL_CPSW_enableAleLearnNoVID | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_enableAleLearnNoVID
Description
This function configures the ALE control register to enable VLAN Id No Learn, i.e., disable VLAN Id learning.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_CONTROL_LEARN_NO_VLANID=1
Example
CSL_CPSW_enableAleLearnNoVID ();
| void CSL_CPSW_disableAleLearnNoVID | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_disableAleLearnNoVID
Description
This function configures the ALE control register to enable VLAN Id learning.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_CONTROL_LEARN_NO_VLANID=0
Example
CSL_CPSW_disableAleLearnNoVID ();
| Uint32 CSL_CPSW_isAleUUNIToHostEnabled | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_isAleUUNIToHostEnabled
Description
This function indicates if ALE is programmed to forward unkown unicast packets to host.
Arguments
None
Return Value
TRUE Unknown unicast packets flood to host also.
FALSE Unknown unicast packets are dropped to the host.
Pre Condition
None
Post Condition
None
Reads
ALE_ALE_CONTROL_EN_HOST_UNI_FLOOD
Example
if (CSL_CPSW_isAleUUNIToHostEnabled () == TRUE)
{
// ALE Unknown UNI packets forwarded to host
}
else
{
// ALE Unknown UNI packets dropped to host
}| void CSL_CPSW_enableAleUUNIToHost | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_enableAleUUNIToHost
Description
This function configures the ALE control register to enable forwarding unkown unicast packets to host.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_CONTROL_EN_HOST_UNI_FLOOD=1
Example
CSL_CPSW_enableAleUUNIToHost ();
| void CSL_CPSW_disableAleUUNIToHost | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_disableAleUUNIToHost
Description
This function configures the ALE control register to disable forwarding unkown unicast packets to host.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_CONTROL_EN_HOST_UNI_FLOOD=0
Example
CSL_CPSW_disableAleUUNIToHost ();
| Uint32 CSL_CPSW_isAleUVLANNoLearnEnabled | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_isAleUVLANNoLearnEnabled
Description
This function indicates if ALE is programmed to disable learning of the packets with unknown VLAN.
Arguments
None
Return Value
TRUE Unknown VLAN No Learn enabled. Source addresses of unknown VLANIDs are not added into the look up table even if learning is enabled.
FALSE Unknown VLAN No Learn disabled. Source addresses of unknown VLANIDs are added into the look up table if learning is enabled.
Pre Condition
ALE_ALE_CONTROL_ENABLE_ALE = 1
Post Condition
None
Reads
ALE_ALE_CONTROL_UVLAN_NO_LEARN
Example
if (CSL_CPSW_isAleUVLANNoLearnEnabled () == TRUE)
{
// Unknown VLAN No Learn disabled
}
else
{
// Unknown VLAN No Learn enabled
}| void CSL_CPSW_enableAleUVLANNoLearn | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_enableAleUVLANNoLearn
Description
This function configures the ALE control register to enable Unknown VLAN No Learn mode.
Arguments
None
Return Value
None
Pre Condition
ALE_ALE_CONTROL_ENABLE_ALE = 1
Post Condition
None
Writes
ALE_ALE_CONTROL_UVLAN_NO_LEARN=1
Example
CSL_CPSW_enableAleUVLANNoLearn ();
| void CSL_CPSW_disableAleUVLANNoLearn | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_disableAleUVLANNoLearn
Description
This function configures the ALE control register to disable unknown VLAN No Learn mode.
Arguments
None
Return Value
None
Pre Condition
ALE_ALE_CONTROL_ENABLE_ALE = 1
Post Condition
None
Writes
ALE_ALE_CONTROL_UVLAN_NO_LEARN=0
Example
CSL_CPSW_disableAleUVLANNoLearn ();
| Uint32 CSL_CPSW_getAleUpdateBW | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_getAleUpdateBW
Description
This function extracts the ALE Update Bandwidth of the ALE control register
Arguments
None
Return Value
aleUpdBW ALE Update Bandwidth
Pre Condition
None
Post Condition
None
Reads
ALE_ALE_CONTROL_UPD_BW_CTRL
Example
Uint32 aleUpdBW;
aleUpdBW = CSL_CPSW_getAleUpdateBW();| void CSL_CPSW_setAleUpdateBW | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | aleUpdBW | ||
| ) |
============================================================================
CSL_CPSW_setAleUpdateBW
Description
This function configures the ALE Update Bandwidth of the ALE control register.
Arguments
aleUpdBW ALE Update Bandwidth
Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_CONTROL_UPD_BW_CTRL
Example
CSL_CPSW_setAleUpdateBW ((Uint32)ALE_UPD_BW_350MHZ_5M);
| void CSL_CPSW_startAleAgeOutNow | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_startAleAgeOutNow
Description
This function configures the ALE control register to initiate an ALE ageable entry cleanup. This enables the ALE hardware to remove any ageable table entry that does not have a set touch bit.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_CONTROL_AGE_OUT_NOW=1
Example
CSL_CPSW_startAleAgeOutNow ();
| Uint32 CSL_CPSW_isAleAgeOutDone | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_isAleAgeOutDone
Description
This function reads the ALE control register's AGE_OUT_NOW bit to check if the ALE ageable entry cleanup process is done.
Arguments
None
Return Value
TRUE ALE age out process done.
FALSE ALE age out process not yet completed.
Pre Condition
None
Post Condition
None
Reads
ALE_ALE_CONTROL_AGE_OUT_NOW
Example
if (CSL_CPSW_isAleAgeOutDone ();
| void CSL_CPSW_clearAleTable | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_clearAleTable
Description
This function initiates a full ALE table cleanup. The ALE hardware clears all table entries.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_CONTROL_CLEAR_TABLE=1
Example
CSL_CPSW_clearAleTable ();
| Uint32 CSL_CPSW_isAleEnabled | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_isAleEnabled
Description
This function indicates if ALE processing is enabled.
Arguments
None
Return Value
TRUE ALE enabled. ALE packet processing will be done.
FALSE ALE disabled. All packets are dropped by ALE.
Pre Condition
None
Post Condition
None
Reads
ALE_ALE_CONTROL_ENABLE_ALE
Example
if (CSL_CPSW_isAleEnabled () == TRUE)
{
// ALE enabled
}
else
{
// ALE disabled
}| void CSL_CPSW_enableAle | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_enableAle
Description
This function configures the ALE control register to enable ALE processing.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_CONTROL_ENABLE_ALE=1
Example
CSL_CPSW_enableAle ();
| void CSL_CPSW_disableAle | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_disableAle
Description
This function configures the ALE control register to disable ALE processing.
Arguments
None
Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_CONTROL_ENABLE_ALE=0
Example
CSL_CPSW_disableAle ();
| Uint32 CSL_CPSW_getAleControlReg | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_getAleControlReg
Description
This function retrieves the contents of the ALE control register.
Arguments
None
Return Value
>=0 ALE control register contents.
Pre Condition
None
Post Condition
None
Reads
ALE_CONTROL_REG
Example
Uint32 aleCtrlVal;
aleCtrlVal = CSL_CPSW_getAleControlReg ();| void CSL_CPSW_setAleControlReg | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | aleCtrlVal | ||
| ) |
============================================================================
CSL_CPSW_setAleControlReg
Description
This function sets up the contents of the ALE control register.
Arguments
aleCtrlVal Value to be configured to the ALE control register. *
Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_CONTROL_REG
Example
* Uint32 aleCtrlVal = 0;
aleCtrlVal = CSL_CPSW_getAleControlReg ();
aleCtrlVal |= CSL_XGE_CPSW_ALECONTROL_CLRTABLE_EN;
CSL_CPSW_setAleControlReg (&aleCtrlRegInfo);| void CSL_CPSW_getAleStatusReg | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 * | pNumPolicers, | ||
| Uint32 * | pNumEntries | ||
| ) |
============================================================================
CSL_CPSW_getAleStatusReg
Description
This function retrieves the contents of the ALE Status register.
Arguments
pNumPolicers Number of policers the ALE implements (multiple of 8)
pNumEntries Number of total table entries supported (multiple of 1024).
* Return Value
None
Pre Condition
None
Post Condition
None
Reads
ALE_ALE_STATUS_KLUENTRIES ALE_ALE_STATUS_POLCNTDIV8
Example
Uint32 numPolicers, numEntries;
CSL_CPSW_getAleStatusReg (&numPolicers,
&numEntries);| void CSL_CPSW_getAleStatusNumAleEntries | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 * | pNumEntries | ||
| ) |
| CSL_CPSW_ALE_RAMDEPTH_E CSL_CPSW_getAleStatusRamDepth | ( | CSL_AleRegs * | hCpswAleRegs | ) |
| void CSL_CPSW_getAleStatusVlanMask | ( | CSL_AleRegs * | hCpswAleRegs, |
| bool * | vlanMsk08, | ||
| bool * | vlanMsk12 | ||
| ) |
| Uint32 CSL_CPSW_getAlePrescaleReg | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_getAlePrescaleReg
Description
This function retrieves the contents of the ALE Prescale register.
Arguments
None
Return Value
>=0 ALE prescale register contents.
Pre Condition
None
Post Condition
None
Reads
ALE_ALE_PRESCALE_ALE_PRESCALE
Example
Uint32 alePrescaleVal;
alePrescaleVal = CSL_CPSW_getAlePrescaleReg ();| void CSL_CPSW_setAlePrescaleReg | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | alePrescaleVal | ||
| ) |
============================================================================
CSL_CPSW_setAlePrescaleReg
Description
This function sets up the contents of the ALE prescale register.
Arguments
alePrescaleVal Value to be configured to the ALE Prescale register. *
Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_PRESCALE_ALE_PRESCALE
Example
* Uint32 alePrescaleVal = 0;
alePrescaleVal = 10;
CSL_CPSW_setAlePrescaleReg (&aleCtrlRegInfo);| void CSL_CPSW_getAleAgingTimerReg | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 * | pAgingPrescale, | ||
| Uint32 * | pAgingPeriod | ||
| ) |
============================================================================
CSL_CPSW_getAleAgingTimerReg
Description
This function retrieves the contents of the ALE Aging Timer register.
Arguments
pAgingPrescale Aging Timer prescale (1, 1000, 1000000)
pAgingPeriod Aging period in units of prescale.
When non-zero, auto-aging is enabled.
This value (minus 1) times prescale is the number
of clock cycles after which auto-aging will automatically
be initiated.
* Return Value
None
Pre Condition
None
Post Condition
None
Reads
ALE_ALE_AGING_CTRL_ALE_AGING_TIMER ALE_ALE_AGING_CTRL_PRESCALE_1_DISABLE ALE_ALE_AGING_CTRL_PRESCALE_2_DISABLE
Example
Uint32 aleAgingPrescale;
Uint32 aleAgingPeriod
CSL_CPSW_getAleAgingTimerReg (&aleAgingPrescale,
&aleAgingPeriod);| void CSL_CPSW_setAleAgingTimerReg | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | agingPrescale, | ||
| Uint32 | agingPeriod | ||
| ) |
============================================================================
CSL_CPSW_setAleAgingTimerReg
Description
This function sets up the contents of the ALE Aging Timer register.
Arguments
agingPrescale Aging Timer prescale (1, 1000, 1000000)
agingPeriod Aging period in units of prescale.
When non-zero, auto-aging is enabled.
This value (minus 1) times prescale is the number
of clock cycles after which auto-aging will automatically
be initiated.
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_AGING_CTRL_ALE_AGING_TIMER ALE_ALE_AGING_CTRL_PRESCALE_1_DISABLE ALE_ALE_AGING_CTRL_PRESCALE_2_DISABLE
Example
Uint32 aleAgingPrescale;
Uint32 aleAgingPeriod;
aleAgingPrescale = (Uint32)ALE_AGT_PRESACLE_1M;
aleAgingPeriod = 1000;
CSL_CPSW_setAleAgingTimerReg (aleAgingPrescale,
aleAgingPeriod);| void CSL_CPSW_getAleUnkownVlanReg | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 * | pUnVlanMemList, | ||
| Uint32 * | pUnMcastFloodMask, | ||
| Uint32 * | pUnRegMcastFloodMask, | ||
| Uint32 * | pUnForceUntagEgress | ||
| ) |
============================================================================
CSL_CPSW_getAleUnkownVlanReg
Description
This function retrieves the contents of the ALE Unknown VLAN and etc registers.
Arguments
pUnVlanMemList Unknown VLAN member list.
pUnMcastFloodMask Unknown VLAN Multicast flood mask.
pUnRegMcastFloodMask Unknown VLAN Registered Multicast Flood mask.
pUnForceUntagEgress Unknown VLAN Force Untagged Egress.
* Return Value
None
Pre Condition
None
Post Condition
None
Reads
ALE_UNKNOWN_VLAN_REG_UNKNOWN_LIST, ALE_UNKNOWN_MCAST_FLOOD_REG_MASK, ALE_UNKNOWN_REG_MCAST_FLOOD_REG_MASK, ALE_ALE_UVLAN_UNTAG_UVLAN_FORCE_UNTAGGED_EGRESS
Example
Uint32 unVlanMemList, unMcastFloodMask, unRegMcastFloodMask, unForceUntagEgress;
CSL_CPSW_getAleUnkownVlanReg (&unVlanMemList,
&unMcastFloodMask,
&unRegMcastFloodMask,
&unForceUntagEgress);| void CSL_CPSW_setAleUnkownVlanReg | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | unVlanMemList, | ||
| Uint32 | unMcastFloodMask, | ||
| Uint32 | unRegMcastFloodMask, | ||
| Uint32 | unForceUntagEgress | ||
| ) |
============================================================================
CSL_CPSW_setAleUnkownVlanReg
Description
This function sets up the contents of the ALE Unknown VLAN and etc. register.
Arguments
unVlanMemList Unknown VLAN member list.
unMcastFloodMask Unknown VLAN Multicast flood mask.
unRegMcastFloodMask Unknown VLAN Registered Multicast Flood mask.
unForceUntagEgress Unknown VLAN Force Untagged Egress.
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_UNKNOWN_VLAN_REG_UNKNOWN_LIST, ALE_UNKNOWN_MCAST_FLOOD_REG_MASK, ALE_UNKNOWN_REG_MCAST_FLOOD_REG_MASK, ALE_ALE_UVLAN_UNTAG_UVLAN_FORCE_UNTAGGED_EGRESS
Example
Uint32 unVlanMemList, unMcastFloodMask, unRegMcastFloodMask, unForceUntagEgress;
unVlanMemList = 0;
unMcastFloodMask = 3;
unRegMcastFloodMask = 0;
unForceUntagEgress = 0;
CSL_CPSW_setAleUnkownVlanReg (unVlanMemList,
unMcastFloodMask,
unRegMcastFloodMask,
unForceUntagEgress);| void CSL_CPSW_getAleVlanMaskMuxReg | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 * | vlanMaskMux | ||
| ) |
============================================================================
CSL_CPSW_getAleVlanMaskMuxReg
Description
This function retrieves the contents of the ALE VLAN Mask Mux registers.
Arguments
vlanMaskMux Array of VLAN Mask Mux which is indexed by
the unreg_mcast_flood_index and reg_mcast_flood_
index values from the VLAN table entry to determine
the registered and unregistered multicast flood masks Return Value
None
Pre Condition
None
Post Condition
None
Reads
ALE_VLAN_MASK_MUX_REG_MASK
Example
Uint32 vlanMaskMux[4];
CSL_CPSW_getAleVlanMaskMuxReg (vlanMaskMux);Note
The value of VLAN_Mask_MUX_0 is read only and all ones (all ports are one).
| void CSL_CPSW_setAleVlanMaskMuxReg | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 * | vlanMaskMux | ||
| ) |
============================================================================
CSL_CPSW_setAleVlanMaskMuxReg
Description
This function sets up the contents of the ALE VLAN Mask Mux registers.
Arguments
vlanMaskMux Array of VLAN Mask Mux which is indexed by
the unreg_mcast_flood_index and reg_mcast_flood_
index values from the VLAN table entry to determine
the registered and unregistered multicast flood masks
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_VLAN_MASK_MUX_REG_MASK
Example
Uint32 vlanMaskMux[4];
vlanMaskMux[0] = 0x3;
vlanMaskMux[1] = 0;
...
CSL_CPSW_setAleVlanMaskMuxReg (vlanMaskMux); Note
The value of VLAN_Mask_MUX_0 is read only and all ones (all ports are one).
| void CSL_CPSW_getAleVlanMaskMuxEntryReg | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | maskMuxIndex, | ||
| Uint32 * | vlanMaskMuxPtr | ||
| ) |
============================================================================
CSL_CPSW_getAleVlanMaskMuxEntryReg
Description
This function retrieves the contents of the ALE VLAN Mask Mux registers.
Arguments
vlanMaskMux Array of VLAN Mask Mux which is indexed by
the unreg_mcast_flood_index and reg_mcast_flood_
index values from the VLAN table entry to determine
the registered and unregistered multicast flood masks
* Return Value
None
Pre Condition
None
Post Condition
None
Reads
ALE_VLAN_MASK_MUX_REG_MASK
Example
Uint32 vlanMaskMux[4];
CSL_CPSW_getAleVlanMaskMuxReg (vlanMaskMux); Note
The value of VLAN_Mask_MUX_0 is read only and all ones (all ports are one).
| void CSL_CPSW_setAleVlanMaskMuxEntryReg | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | maskMuxIndex, | ||
| Uint32 | vlanMaskMuxVal | ||
| ) |
============================================================================
CSL_CPSW_setAleVlanMaskMuxEntryReg
Description
This function sets up the contents of the ALE VLAN Mask Mux registers.
Arguments
vlanMaskMux Array of VLAN Mask Mux which is indexed by
the unreg_mcast_flood_index and reg_mcast_flood_
index values from the VLAN table entry to determine
the registered and unregistered multicast flood masks
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_VLAN_MASK_MUX_REG_MASK
Example
Uint32 vlanMaskMux[4];
vlanMaskMux[0] = 0x3;
vlanMaskMux[1] = 0;
...
CSL_CPSW_setAleVlanMaskMuxReg (vlanMaskMux); Note
The value of VLAN_Mask_MUX_0 is read only and all ones (all ports are one).
| void CSL_CPSW_getAleTableEntry | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index, | ||
| Uint32 * | pAleInfoWd0, | ||
| Uint32 * | pAleInfoWd1, | ||
| Uint32 * | pAleInfoWd2 | ||
| ) |
============================================================================
CSL_CPSW_getAleTableEntry
Description
This function retrieves an ALE table entry corresponding to the ALE entry index specified in 'index' input parameter. The ALE entry values corresponding to the ALE_TBLW0, ALE_TBLW1 and ALE_TBLW2 registers are returned in 'pAleInfoWd0', 'pAleInfoWd1', 'pAleInfoWd2' output parameters.
Arguments
index ALE table index to be read.
pAleInfoWd0 Contents of ALE Table Word 0 Register (ALE_TBLW0).
pAleInfoWd1 Contents of ALE Table Word 1 Register (ALE_TBLW1).
pAleInfoWd2 Contents of ALE Table Word 2 Register (ALE_TBLW2).
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_TBLCTL_TABLEIDX, ALE_ALE_TBLCTL_TABLEWR=0
Reads
ALE_ALE_TBLW0_TABLEWRD0, ALE_ALE_TBLW1_TABLEWRD1, ALE_ALE_TBLW2_TABLEWRD2
Example
Uint32 index, info0, info1, info2;
index = 0;
CSL_CPSW_getAleTableEntry (index,
&info0,
&info1,
&info2);| void CSL_CPSW_setAleTableEntry | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index, | ||
| Uint32 | aleInfoWd0, | ||
| Uint32 | aleInfoWd1, | ||
| Uint32 | aleInfoWd2 | ||
| ) |
============================================================================
CSL_CPSW_setAleTableEntry
Description
This function sets up an ALE table entry corresponding to the ALE entry index specified in 'index' input parameter. The ALE entry values corresponding to the ALE_TBLW0, ALE_TBLW1 and ALE_TBLW2 registers msut be specified in 'aleInfoWd0', 'aleInfoWd1', 'aleInfoWd2' input parameters.
Arguments
index ALE table index to be written.
aleInfoWd0 Value to write to ALE Table Word 0 Register (ALE_TBLW0).
aleInfoWd1 Value to write to ALE Table Word 1 Register (ALE_TBLW1).
aleInfoWd2 Value to write to ALE Table Word 2 Register (ALE_TBLW2).
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_TBLW0_TABLEWRD0, ALE_ALE_TBLW1_TABLEWRD1, ALE_ALE_TBLW2_TABLEWRD2, ALE_ALE_TBLCTL_TABLEIDX, ALE_ALE_TBLCTL_TABLEWR=1
@b Example
Uint32 index, info0, info1, info2;
index = 0;
info0 = ...;
info1 = ...;
info2 = ...;
CSL_CPSW_setAleTableEntry (index,
info0,
info1,
info2);| CSL_CPSW_ALE_ENTRYTYPE CSL_CPSW_getALEEntryType | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index, | ||
| CSL_CPSW_ALETABLE_TYPE | aleType | ||
| ) |
============================================================================
CSL_CPSW_getALEEntryType
Description
This function returns the ALE entry type for any given ALE table entry index.
Arguments
hCpswAleRegs ALE register overlay
index ALE table index to be read.
aleType ALE type(4-Port/9-Port)
* Return Value CSL_CPSW_ALE_ENTRYTYPE
ALE_ENTRYTYPE_FREE ALE entry is free.
ALE_ENTRYTYPE_ADDRESS ALE entry contains a unicast/multicast address.
ALE_ENTRYTYPE_VLAN ALE entry contains a VLAN.
ALE_ENTRYTYPE_VLANADDRESS ALE entry contains a VLAN and a unicast/multicast address.
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_TBLCTL_TABLEIDX, ALE_ALE_TBLCTL_TABLEWR=0
Reads
ALE_TABLE_WORD1_REG
Example
* Uint32 index = 0;
if (CSL_CPSW_getALEEntryType () == ALE_ENTRYTYPE_FREE)
{
// ALE entry free
}| CSL_CPSW_ALE_ADDRTYPE CSL_CPSW_getALEAddressType | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index, | ||
| CSL_CPSW_ALETABLE_TYPE | aleType | ||
| ) |
============================================================================
CSL_CPSW_getALEAddressType
Description
This function returns the address type of an ALE entry.
Arguments
hCpswAleRegs ALE register overlay
index ALE table index to be read.
aleType ALE type(4-Port/9-Port)
* Return Value CSL_CPSW_ALE_ADDRTYPE
ALE_ADDRTYPE_UCAST Address at this entry is unicast
ALE_ADDRTYPE_MCAST Address at this entry is multicast
ALE_ADDRTYPE_OUI Address at this entry is OUI address
Pre Condition
This function must be called only for an ALE address entry, i.e., if CSL_XGE_CPSW_getALEEntryType () returns ALE_ENTRYTYPE_ADDRESS or ALE_ENTRYTYPE_VLANADDRESS only.
Post Condition
None
Writes
ALE_ALE_TBLCTL_TABLEIDX, ALE_ALE_TBLCTL_TABLEWR=0
Reads
ALE_TABLE_WORD0_REG, ALE_TABLE_WORD1_REG
Example
* Uint32 index = 0;
if (CSL_CPSW_getALEEntryType (index) == ALE_ENTRYTYPE_ADDRESS)
{
// ALE entry has an address
if (CSL_CPSW_getALEAddressType (index) == ALE_ADDRTYPE_UCAST)
{
// Unicast address
}
}
else
{
// Do nothing
}
...| CSL_CPSW_ALE_POLICER_ENTRYTYPE CSL_CPSW_getALEPolicerEntryType | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index, | ||
| CSL_CPSW_ALETABLE_TYPE | aleType | ||
| ) |
============================================================================
CSL_CPSW_getALEPolicerEntryType
Description
This function returns the entry type of an ALE Policer entry.
Arguments
hCpswAleRegs ALE register overlay
index ALE table index to be read.
aleType ALE type(4-Port/9-Port)
* Return Value CSL_CPSW_ALE_POLICER_ENTRYTYPE
ALE_POLICER_ENTRYTYPE_VLAN (Inner) VLAN Entry
ALE_POLICER_ENTRYTYPE_OVLAN Outer VLAN entry
ALE_POLICER_ENTRYTYPE_ETHERTYPEI Ether Type entry
ALE_POLICER_ENTRYTYPE_IPV4 IPv4 Address entry
ALE_POLICER_ENTRYTYPE_IPV6 IPv6 Address entry
Pre Condition
This function must be called only for an ALE address entry, i.e., if CSL_XGE_CPSW_getALEEntryType () returns ALE_ENTRYTYPE_POLICER.
Post Condition
None
Writes
ALE_ALE_TBLCTL_TABLEIDX, ALE_ALE_TBLCTL_TABLEWR=0
Reads
ALE_TABLE_WORD1_REG, ALE_TABLE_WORD2_REG
Example
* Uint32 index = 0;
if (CSL_CPSW_getALEEntryType (index) == ALE_ENTRYTYPE_POLICER)
{
// ALE entry has an address
if (CSL_CPSW_getALEPolicerEntryType (index) == ALE_POLICER_ENTRYTYPE_IPV4)
{
// IPv4 address
}
}
else
{
// Do nothing
}
...| void CSL_CPSW_getAleMcastAddrEntry | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index, | ||
| CSL_CPSW_ALE_MCASTADDR_ENTRY * | pMcastAddrCfg, | ||
| CSL_CPSW_ALETABLE_TYPE | aleType | ||
| ) |
============================================================================
CSL_CPSW_getAleMcastAddrEntry
Description
This function reads the ALE table entry for the index specified and fills the output parameter structure with Multicast address configuration read from the hardware.
Arguments
hCpswAleRegs ALE register overlay
index ALE table index to be read.
pMcastAddrCfg ALE entry contents read.
aleType ALE type(4-Port/9-Port)
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_TBLCTL_TABLEIDX, ALE_ALE_TBLCTL_TABLEWR=0
Reads
ALE_TABLE_WORD0, ALE_TABLE_WORD1, ALE_TABLE_WORD2
Example
Uint32 index;
CSL_ALE_MCASTADDR_ENTRY mcastAddrCfg;
index = 0;
if (CSL_CPSW_getALEEntryType (index) == ALE_ENTRYTYPE_ADDRESS)
{
// ALE entry has an address
if (CSL_CPSW_getALEAddressType (index) == ALE_ADDRTYPE_MCAST)
{
// Read Multicast address config from hardware
CSL_CPSW_getAleMcastAddrEntry (index, &mcastAddrCfg);
}
}| void CSL_CPSW_setAleMcastAddrEntry | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index, | ||
| CSL_CPSW_ALE_MCASTADDR_ENTRY * | pMcastAddrCfg, | ||
| CSL_CPSW_ALETABLE_TYPE | aleType | ||
| ) |
============================================================================
CSL_CPSW_setAleMcastAddrEntry
Description
This function sets up the ALE table entry for the index specified with Multicast address configuration specified here.
Arguments
hCpswAleRegs ALE register overlay
index ALE table index.
pMcastAddrCfg ALE entry contents to be configured.
aleType ALE type(4-Port/9-Port)
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_TBLCTL_TABLEIDX, ALE_ALE_TBLCTL_TABLEWR=1 ALE_TABLE_WORD0, ALE_TABLE_WORD1, ALE_TABLE_WORD2
Example
Uint32 index;
CSL_CPSW_ALE_MCASTADDR_ENTRY mcastAddrCfg;
index = 0;
mcastAddrCfg.macAddress [0] = 0x00;
mcastAddrCfg.macAddress [1] = 0x01;
...
if (CSL_CPSW_getALEEntryType (index) == ALE_ENTRYTYPE_FREE)
{
// ALE entry is free
// Add Multicast address entry
CSL_CPSW_setAleMcastAddrEntry (index, &mcastAddrCfg);
}| void CSL_CPSW_getAleVlanMcastAddrEntry | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index, | ||
| CSL_CPSW_ALE_VLANMCASTADDR_ENTRY * | pVlanMcastAddrCfg, | ||
| CSL_CPSW_ALETABLE_TYPE | aleType | ||
| ) |
============================================================================
CSL_CPSW_getAleVlanMcastAddrEntry
Description
This function reads the ALE table entry for the index specified and fills the output parameter structure with VLAN Multicast address configuration read from the hardware.
Arguments
hCpswAleRegs ALE register overlay
index ALE table index to be read.
pVlanMcastAddrCfg ALE entry contents read.
aleType ALE type(4-Port/9-Port)
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_TBLCTL_TABLEIDX, ALE_ALE_TBLCTL_TABLEWR=0
Reads
ALE_TABLE_WORD0, ALE_TABLE_WORD1, ALE_TABLE_WORD2
Example
Uint32 index;
CSL_CPSW_ALE_VLANMCASTADDR_ENTRY vlanMcastAddrCfg;
index = 0;
if (CSL_CPSW_getALEEntryType (index) == ALE_ENTRYTYPE_VLANADDRESS)
{
// ALE entry has a VLAN address
if (CSL_CPSW_getALEAddressType (index) == ALE_ADDRTYPE_MCAST)
{
// Read VLAN Multicast address config from hardware
CSL_CPSW_getAleVlanMcastAddrEntry (index, &vlanMcastAddrCfg);
}
}| void CSL_CPSW_setAleVlanMcastAddrEntry | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index, | ||
| CSL_CPSW_ALE_VLANMCASTADDR_ENTRY * | pVlanMcastAddrCfg, | ||
| CSL_CPSW_ALETABLE_TYPE | aleType | ||
| ) |
============================================================================
CSL_CPSW_setAleVlanMcastAddrEntry
Description
This function sets up the ALE table entry for the index specified with VLAN Multicast address configuration specified here.
Arguments
hCpswAleRegs ALE register overlay
index ALE table index.
pVlanMcastAddrCfg ALE entry contents to be configured.
aleType ALE type(4-Port/9-Port)
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_TBLCTL_TABLEIDX, ALE_ALE_TBLCTL_TABLEWR=1 ALE_TABLE_WORD0, ALE_TABLE_WORD1, ALE_TABLE_WORD2
Example
Uint32 index;
CSL_CPSW_ALE_VLANMCASTADDR_ENTRY vlanMcastAddrCfg;
index = 0;
vlanMcastAddrCfg.macAddress [0] = 0x00;
vlanMcastAddrCfg.macAddress [1] = 0x01;
...
if (CSL_CPSW_getALEEntryType (index) == ALE_ENTRYTYPE_FREE)
{
// ALE entry is free
// Add VLAN Multicast address entry
CSL_CPSW_setAleVlanMcastAddrEntry (index, &vlanMcastAddrCfg);
}| void CSL_CPSW_getAleUnicastAddrEntry | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index, | ||
| CSL_CPSW_ALE_UNICASTADDR_ENTRY * | pUcastAddrCfg, | ||
| CSL_CPSW_ALETABLE_TYPE | aleType | ||
| ) |
============================================================================
CSL_CPSW_getAleUnicastAddrEntry
Description
This function reads the ALE table entry for the index specified and fills the output parameter structure with Unicast address configuration read from the hardware.
Arguments
hCpswAleRegs ALE register overlay
index ALE table index to be read.
pUcastAddrCfg ALE entry contents read.
aleType ALE type(4-Port/9-Port)
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_TBLCTL_TABLEIDX, ALE_ALE_TBLCTL_TABLEWR=0
Reads
ALE_TABLE_WORD0, ALE_TABLE_WORD1, ALE_TABLE_WORD2
Example
Uint32 index;
CSL_CPSW_ALE_UNICASTADDR_ENTRY ucastAddrCfg;
index = 0;
if (CSL_CPSW_getALEEntryType (index) == ALE_ENTRYTYPE_ADDRESS)
{
// ALE entry has an address
if (CSL_CPSW_getALEAddressType (index) == ALE_ADDRTYPE_UCAST)
{
// Read Unicast address config from hardware
CSL_CPSW_getAleUnicastAddrEntry (index, &ucastAddrCfg);
}
}| void CSL_CPSW_setAleUnicastAddrEntry | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index, | ||
| CSL_CPSW_ALE_UNICASTADDR_ENTRY * | pUcastAddrCfg, | ||
| CSL_CPSW_ALETABLE_TYPE | aleType | ||
| ) |
============================================================================
CSL_CPSW_setAleUnicastAddrEntry
Description
This function sets up the ALE table entry for the index specified with unicast address configuration specified here.
Arguments
hCpswAleRegs ALE register overlay
index ALE table index.
pUcastAddrCfg ALE entry contents to be configured.
aleType ALE type(4-Port/9-Port)
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_TBLCTL_TABLEIDX, ALE_ALE_TBLCTL_TABLEWR=1 ALE_TABLE_WORD0, ALE_TABLE_WORD1, ALE_TABLE_WORD2
Example
Uint32 index;
CSL_CPSW_ALE_UNICASTADDR_ENTRY ucastAddrCfg;
index = 0;
ucastAddrCfg.macAddress [0] = 0x00;
ucastAddrCfg.macAddress [1] = 0x01;
...
if (CSL_CPSW_getALEEntryType (index) == ALE_ENTRYTYPE_FREE)
{
// ALE entry is free
// Add Unicast address entry
CSL_CPSW_setAleUnicastAddrEntry (index, &ucastAddrCfg);
}| void CSL_CPSW_getAleOUIAddrEntry | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index, | ||
| CSL_CPSW_ALE_OUIADDR_ENTRY * | pOUIAddrCfg, | ||
| CSL_CPSW_ALETABLE_TYPE | aleType | ||
| ) |
============================================================================
CSL_CPSW_getAleOUIAddrEntry
Description
This function reads the ALE table entry for the index specified and fills the output parameter structure with OUI address configuration read from the hardware.
Arguments
hCpswAleRegs ALE register overlay
index ALE table index to be read.
pOUIAddrCfg ALE entry contents read.
aleType ALE type(4-Port/9-Port)
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_TBLCTL_TABLEIDX, ALE_ALE_TBLCTL_TABLEWR=0
Reads
ALE_TABLE_WORD0, ALE_TABLE_WORD1, ALE_TABLE_WORD2
Example
Uint32 index;
CSL_CPSW_ALE_OUIADDR_ENTRY ouiAddrCfg;
index = 0;
if (CSL_CPSW_getALEEntryType (index) == ALE_ENTRYTYPE_ADDRESS)
{
// ALE entry has an address
if (CSL_CPSW_getALEAddressType (index) == ALE_ADDRTYPE_OUI)
{
// Read Unicast address config from hardware
CSL_CPSW_getAleOUIAddrEntry (index, &ouiAddrCfg);
}
}| void CSL_CPSW_setAleOUIAddrEntry | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index, | ||
| CSL_CPSW_ALE_OUIADDR_ENTRY * | pOUIAddrCfg, | ||
| CSL_CPSW_ALETABLE_TYPE | aleType | ||
| ) |
============================================================================
CSL_CPSW_setAleOUIAddrEntry
Description
This function sets up the ALE table entry for the index specified with OUI address configuration specified here.
Arguments
hCpswAleRegs ALE register overlay
index ALE table index.
pOUIAddrCfg ALE entry contents to be configured.
aleType ALE type(4-Port/9-Port)
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_TBLCTL_TABLEIDX, ALE_ALE_TBLCTL_TABLEWR=1 ALE_TABLE_WORD0, ALE_TABLE_WORD1, ALE_TABLE_WORD2
Example
Uint32 index;
CSL_CPSW_ALE_OUIADDR_ENTRY ouiAddrCfg;
index = 0;
ouiAddrCfg.ouiAddress [0] = 0x00;
ouiAddrCfg.ouiAddress [1] = 0x01;
...
if (CSL_CPSW_getALEEntryType (index) == ALE_ENTRYTYPE_FREE)
{
// ALE entry is free
// Add OUI address entry
CSL_CPSW_setAleOUIAddrEntry (index, &ouiAddrCfg);
}| void CSL_CPSW_getAleVlanUnicastAddrEntry | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index, | ||
| CSL_CPSW_ALE_VLANUNICASTADDR_ENTRY * | pVlanUcastAddrCfg, | ||
| CSL_CPSW_ALETABLE_TYPE | aleType | ||
| ) |
============================================================================
CSL_CPSW_getAleVlanUnicastAddrEntry
Description
This function reads the ALE table entry for the index specified and fills the output parameter structure with VLAN Unicast address configuration read from the hardware.
Arguments
hCpswAleRegs ALE register overlay
index ALE table index to be read.
pVlanUcastAddrCfg ALE entry contents read.
aleType ALE type(4-Port/9-Port)
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_TBLCTL_TABLEIDX, ALE_ALE_TBLCTL_TABLEWR=0
Reads
ALE_TABLE_WORD0, ALE_TABLE_WORD1, ALE_TABLE_WORD2
Example
Uint32 index;
CSL_CPSW_ALE_VLANUNICASTADDR_ENTRY vlanUcastAddrCfg;
index = 0;
if (CSL_CPSW_getALEEntryType (index) == ALE_ENTRYTYPE_VLANADDRESS)
{
// ALE entry has a VLAN address
if (CSL_CPSW_getALEAddressType (index) == ALE_ADDRTYPE_UCAST)
{
// Read VLAN Unicast address config from hardware
CSL_CPSW_getAleVlanUnicastAddrEntry (index, &ucvlanUcastAddrCfgastAddrCfg);
}
}| void CSL_CPSW_setAleVlanUnicastAddrEntry | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index, | ||
| CSL_CPSW_ALE_VLANUNICASTADDR_ENTRY * | pVlanUcastAddrCfg, | ||
| CSL_CPSW_ALETABLE_TYPE | aleType | ||
| ) |
============================================================================
CSL_CPSW_setAleVlanUnicastAddrEntry
Description
This function sets up the ALE table entry for the index specified with VLAN unicast address configuration specified here.
Arguments
hCpswAleRegs ALE register overlay
index ALE table index.
pVlanUcastAddrCfg ALE entry contents to be configured.
aleType ALE type(4-Port/9-Port)
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_TBLCTL_TABLEIDX, ALE_ALE_TBLCTL_TABLEWR=1 ALE_TABLE_WORD0, ALE_TABLE_WORD1, ALE_TABLE_WORD2
Example
Uint32 index;
CSL_CPSW_ALE_VLANUNICASTADDR_ENTRY vlanUcastAddrCfg;
index = 0;
vlanUcastAddrCfg.macAddress [0] = 0x00;
vlanUcastAddrCfg.macAddress [1] = 0x01;
...
if (CSL_CPSW_getALEEntryType (index) == ALE_ENTRYTYPE_FREE)
{
// ALE entry is free
// Add VLAN Unicast address entry
CSL_CPSW_setAleVlanUnicastAddrEntry (index, &vlanUcastAddrCfg);
}| void CSL_CPSW_getAleVlanEntry | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index, | ||
| CSL_CPSW_ALE_VLAN_ENTRY * | pVlanCfg, | ||
| CSL_CPSW_ALETABLE_TYPE | aleType | ||
| ) |
============================================================================
CSL_CPSW_getAleVlanEntry
Description
This function reads the ALE entry info for inner vlan entry
Arguments
hCpswAleRegs ALE register overlay
index ALE table index.
pVlanCfg ALE entry info for VLAN populated by this function
aleType ALE type(4-Port/9-Port)
* Return Value
None
| void CSL_CPSW_setAleVlanEntry | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index, | ||
| CSL_CPSW_ALE_VLAN_ENTRY * | pVlanCfg, | ||
| CSL_CPSW_ALETABLE_TYPE | aleType | ||
| ) |
============================================================================
CSL_CPSW_setAleVlanEntry
Description
This function sets up the ALE table entry for the index specified with VLAN configuration specified here.
Arguments
hCpswAleRegs ALE register overlay
index ALE table index.
pVlanCfg ALE entry contents to be configured.
aleType ALE type(4-Port/9-Port)
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_TBLCTL_TABLEIDX, ALE_ALE_TBLCTL_TABLEWR=1 ALE_TABLE_WORD0, ALE_TABLE_WORD1, ALE_TABLE_WORD2
Example
Uint32 index;
CSL_CPSW_ALE_VLAN_ENTRY vlanCfg;
index = 0;
vlanCfg.vlanId = 0x10;
...
if (CSL_CPSW_getALEEntryType (index) == ALE_ENTRYTYPE_FREE)
{
// ALE entry is free
// Add VLAN entry
CSL_CPSW_setAleVlanEntry (index, &vlanCfg);
}| void CSL_CPSW_getAleOutVlanEntry | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index, | ||
| CSL_CPSW_ALE_OUTER_VLAN_ENTRY * | pOutVlanCfg, | ||
| CSL_CPSW_ALETABLE_TYPE | aleType | ||
| ) |
============================================================================
CSL_CPSW_getAleOutVlanEntry
Description
This function reads the ALE table entry for the index specified and fills the output parameter structure with Outer VLAN configuration read from the hardware.
Arguments
hCpswAleRegs ALE register overlay
index ALE table index to be read.
pOutValnCfg ALE entry contents read.
aleType ALE type(4-Port/9-Port)
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_TBLCTL_TABLEIDX, ALE_ALE_TBLCTL_TABLEWR=0
Reads
ALE_TABLE_WORD1
Example
Uint32 index;
CSL_CPSW_ALE_OUTER_VLAN_ENTRY outVlanCfg;
index = 0;
if (CSL_CPSW_getALEEntryType (index) == ALE_ENTRYTYPE_POLICER)
{
// ALE entry has a plicer entry
if (CSL_CPSW_getALEPolicerEntryType (index) == ALE_POLICER_ENTRYTYPE_OVLAN)
{
// Read outer VALN config from hardware
CSL_CPSW_getAleOutVlanEntry (index, &outVlanCfg);
}
}| void CSL_CPSW_setAleOutVlanEntry | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index, | ||
| CSL_CPSW_ALE_OUTER_VLAN_ENTRY * | pOutVlanCfg, | ||
| CSL_CPSW_ALETABLE_TYPE | aleType | ||
| ) |
============================================================================
CSL_CPSW_setAleOutVlanEntry
Description
This function sets up the ALE table entry for the index specified with Outer VLAN configuration specified here.
Arguments
hCpswAleRegs ALE register overlay
index ALE table index.
pOutValnCfg ALE entry contents to be configured.
aleType ALE type(4-Port/9-Port)
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_TBLCTL_TABLEIDX, ALE_ALE_TBLCTL_TABLEWR=1 ALE_TABLE_WORD0, ALE_TABLE_WORD1, ALE_TABLE_WORD2
Example
Uint32 index;
CSL_CPSW_ALE_OUTER_VLAN_ENTRY outVlanCfg;
index = 0;
outVlanCfg.vlanId = 0x0123;
...
if (CSL_CPSW_getALEEntryType (index) == ALE_ENTRYTYPE_FREE)
{
// ALE entry is free
// Add Outer VLAN entry
CSL_CPSW_setAleOutValnEntry (index, &outVlanCfg);
}| void CSL_CPSW_getAleEthertypeEntry | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index, | ||
| CSL_CPSW_ALE_ETHERTYPE_ENTRY * | pEthertypeCfg, | ||
| CSL_CPSW_ALETABLE_TYPE | aleType | ||
| ) |
============================================================================
CSL_CPSW_getAleEthertypeEntry
Description
This function reads the ALE table entry for the index specified and fills the output parameter structure with Ethertype configuration read from the hardware.
Arguments
hCpswAleRegs ALE register overlay
index ALE table index to be read.
pEthertypeCfg ALE entry contents read.
aleType ALE type(4-Port/9-Port)
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_TBLCTL_TABLEIDX, ALE_ALE_TBLCTL_TABLEWR=0
Reads
ALE_TABLE_WORD0
Example
Uint32 index;
CSL_CPSW_ALE_ETHERTYPE_ENTRY ethertypeCfg;
index = 0;
if (CSL_CPSW_getALEEntryType (index) == ALE_ENTRYTYPE_POLICER)
{
// ALE entry has a plicer entry
if (CSL_CPSW_getALEPolicerEntryType (index) == ALE_POLICER_ENTRYTYPE_ETHERTYPE)
{
// Read Ethertype config from hardware
CSL_CPSW_getAleEthertypeEntry (index, ðertypeCfg);
}
}| void CSL_CPSW_setAleEthertypeEntry | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index, | ||
| CSL_CPSW_ALE_ETHERTYPE_ENTRY * | pEthertypeCfg, | ||
| CSL_CPSW_ALETABLE_TYPE | aleType | ||
| ) |
============================================================================
CSL_CPSW_setAleEthertypeEntry
Description
This function sets up the ALE table entry for the index specified with Ethertype configuration specified here.
Arguments
hCpswAleRegs ALE register overlay
index ALE table index.
pEthertypeCfg ALE entry contents to be configured.
aleType ALE type(4-Port/9-Port)
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_TBLCTL_TABLEIDX, ALE_ALE_TBLCTL_TABLEWR=1 ALE_TABLE_WORD0, ALE_TABLE_WORD1, ALE_TABLE_WORD2
Example
Uint32 index;
CSL_CPSW_ALE_ETHERTYPE_ENTRY ethertypeCfg;
index = 0;
ethertypeCfg.ethertype = 0x0800;
...
if (CSL_CPSW_getALEEntryType (index) == ALE_ENTRYTYPE_FREE)
{
// ALE entry is free
// Add Ethertype entry
CSL_CPSW_setAleEthertypeEntry (index, ðertypeCfg);
}| void CSL_CPSW_getAleIPv4Entry | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index, | ||
| CSL_CPSW_ALE_IPv4_ENTRY * | pIPv4Cfg, | ||
| CSL_CPSW_ALETABLE_TYPE | aleType | ||
| ) |
============================================================================
CSL_CPSW_getAleIPv4Entry
Description
This function reads the ALE table entry for the index specified and fills the output parameter structure with IPv4 configuration read from the hardware.
Arguments
hCpswAleRegs ALE register overlay
index ALE table index to be read.
pIPv4Cfg ALE entry contents read.
aleType ALE type(4-Port/9-Port)
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_TBLCTL_TABLEIDX, ALE_ALE_TBLCTL_TABLEWR=0
Reads
ALE_TABLE_WORD0
Example
Uint32 index;
CSL_CPSW_ALE_IPv4_ENTRY ipv4Cfg;
index = 0;
if (CSL_CPSW_getALEEntryType (index) == ALE_ENTRYTYPE_POLICER)
{
// ALE entry has a plicer entry
if (CSL_CPSW_getALEPolicerEntryType (index) == ALE_POLICER_ENTRYTYPE_IPV4)
{
// Read IPv4 config from hardware
CSL_CPSW_getAleIPv4Entry (index, &ipv4Cfg);
}
}| void CSL_CPSW_setAleIPv4Entry | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index, | ||
| CSL_CPSW_ALE_IPv4_ENTRY * | pIPv4Cfg, | ||
| CSL_CPSW_ALETABLE_TYPE | aleType | ||
| ) |
============================================================================
CSL_CPSW_setAleIPv4Entry
Description
This function sets up the ALE table entry for the index specified with IPv4 configuration specified here.
Arguments
hCpswAleRegs ALE register overlay
index ALE table index.
pIPv4Cfg ALE entry contents to be configured.
aleType ALE type(4-Port/9-Port)
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_TBLCTL_TABLEIDX, ALE_ALE_TBLCTL_TABLEWR=1 ALE_TABLE_WORD0, ALE_TABLE_WORD1, ALE_TABLE_WORD2
Example
Uint32 index;
CSL_CPSW_ALE_IPv4_ENTRY ipv4Cfg;
index = 0;
ipv4Cfg.ethertype = 0x0800;
...
if (CSL_CPSW_getALEEntryType (index) == ALE_ENTRYTYPE_FREE)
{
// ALE entry is free
// Add IPv4 entry
CSL_CPSW_setAleIPv4Entry (index, &ipv4Cfg);
}| Uint32 CSL_CPSW_getAleIPv6HighEntryOffset | ( | CSL_AleRegs * | hCpswAleRegs | ) |
============================================================================
CSL_CPSW_getAleIPv6HighEntryOffset
Description
This function returns the offset of the higher 64bit offset of IPv6 entry for the specific ALE type
Arguments
hCpswAleRegs ALE register overlay *
Return Value
None
| Uint32 CSL_CPSW_getAleIPv6HighEntryIndex | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | entryIndex | ||
| ) |
============================================================================
CSL_CPSW_getAleIPv6HighEntryIndex
Description
This function returns the higher 64bit offset of IPv6 entry given the lower 64bit ALE table entry index
Arguments
hCpswAleRegs ALE register overlay *
Return Value
None
| Uint32 CSL_CPSW_getAleIPv6LowEntryIndex | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | entryIndex | ||
| ) |
============================================================================
CSL_CPSW_getAleIPv6LowEntryIndex
Description
This function returns the lower 64bit ALE entry index of IPv6 entry given the higher 64bit ALE table entry index
Arguments
hCpswAleRegs ALE register overlay *
Return Value
None
| void CSL_CPSW_getAleIPv6Entry | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index, | ||
| CSL_CPSW_ALE_IPv6_ENTRY * | pIPv6Cfg, | ||
| CSL_CPSW_ALETABLE_TYPE | aleType | ||
| ) |
============================================================================
CSL_CPSW_getAleIPv6Entry
Description
This function reads the ALE table entry for the index specified and fills the output parameter structure with Ipv6 configuration read from the hardware.
Arguments
hCpswAleRegs ALE register overlay
index ALE table index to be read.
pIPv6Cfg ALE entry contents read.
aleType ALE type(4-Port/9-Port)
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_TBLCTL_TABLEIDX, ALE_ALE_TBLCTL_TABLEWR=0
Reads
ALE_TABLE_WORD0
Example
Uint32 index;
CSL_CPSW_ALE_IPv6_ENTRY ipv6Cfg;
index = 0;
if (CSL_CPSW_getALEEntryType (index) == ALE_ENTRYTYPE_POLICER)
{
// ALE entry has a plicer entry
if (CSL_CPSW_getALEPolicerEntryType (index) == ALE_POLICER_ENTRYTYPE_IPV6)
{
// Read Ipv6 config from hardware
CSL_CPSW_getAleIPv6Entry (index, &ipv6Cfg);
}
}| void CSL_CPSW_setAleIPv6Entry | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index, | ||
| CSL_CPSW_ALE_IPv6_ENTRY * | pIPv6Cfg, | ||
| CSL_CPSW_ALETABLE_TYPE | aleType | ||
| ) |
============================================================================
CSL_CPSW_setAleIPv6Entry
Description
This function sets up the ALE table entry for the index specified with IPv6 configuration specified here.
Arguments
hCpswAleRegs ALE register overlay
index ALE table index.
pIPv6Cfg ALE entry contents to be configured.
aleType ALE type(4-Port/9-Port)
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_TBLCTL_TABLEIDX, ALE_ALE_TBLCTL_TABLEWR=1 ALE_TABLE_WORD0, ALE_TABLE_WORD1, ALE_TABLE_WORD2
Example
Uint32 index;
CSL_CPSW_ALE_IPv6_ENTRY ipv4Cfg;
index = 0;
ipv4Cfg.ethertype = 0x0800;
...
if ((CSL_CPSW_getALEEntryType (index) == ALE_ENTRYTYPE_FREE &&
(CSL_CPSW_getALEEntryType (index+1) == ALE_ENTRYTYPE_FREE))
{
// ALE entry is free
// Add IPv6 entry
CSL_CPSW_setAleIPv6Entry (index, &ipv4Cfg);
}| void CSL_CPSW_mapTableWord2MacAddr | ( | uint32_t | word0, |
| uint32_t | word1, | ||
| uint8_t * | macAddr, | ||
| CSL_CPSW_ALETABLE_TYPE | aleType | ||
| ) |
============================================================================
CSL_CPSW_mapTableWord2MacAddr
Description
This function extracts the mac address from the ALE table word0 and word 1 Arguments
word0 ALE table word 0 value
word1 ALE table word 0 value
macAddr mac address which will be populated
aleType ALE type(4-Port/9-Port)
* | void CSL_CPSW_mapMacAddr2TableWord | ( | uint32_t * | word0, |
| uint32_t * | word1, | ||
| uint8_t * | macAddr, | ||
| CSL_CPSW_ALETABLE_TYPE | aleType | ||
| ) |
============================================================================
CSL_CPSW_mapMacAddr2TableWord
Description
This function populates the ALE table word 0 and word 1 with the mac address passed Arguments
word0 Pointer to ALE table word 0 to be populated
word1 Pointer to ALE table word 1 to be populated
macAddr input mac address
aleType ALE type(4-Port/9-Port)
* | Uint32 CSL_CPSW_extractVid | ( | Uint32 | word1, |
| CSL_CPSW_ALETABLE_TYPE | aleType | ||
| ) |
============================================================================
CSL_CPSW_extractVid
Description
This function extracts the vlan id field from the ALE table word 1 Arguments
word1 ALE table word 1 value for a VLAN entry
aleType ALE type(4-Port/9-Port)
* Return Value
vid Extracted vlan id
| Uint32 CSL_CPSW_getEthertypeMax | ( | CSL_CPSW_ALETABLE_TYPE | aleType | ) |
============================================================================
CSL_CPSW_getEthertypeMax
Description
This function returns the max value of EtherType field in ALE table Arguments
aleType ALE type(4-Port/9-Port) *
Return Value
Maximum value of Ethertype field in ALE table
| Uint32 CSL_CPSW_getIpv4IgnBitsMax | ( | CSL_CPSW_ALETABLE_TYPE | aleType | ) |
============================================================================
CSL_CPSW_getIpv4IgnBitsMax
Description
This function returns the max value of IPv4 ignore bits field in ALE table Arguments
aleType ALE type(4-Port/9-Port) *
Return Value
Maximum value of max value of IPv4 ignore bits field in ALE table
| Uint32 CSL_CPSW_getIpv6IgnBitsMax | ( | CSL_CPSW_ALETABLE_TYPE | aleType | ) |
============================================================================
CSL_CPSW_getIpv6IgnBitsMax
Description
This function returns the max value of IPv6 ignore bits field in ALE table Arguments
aleType ALE type(4-Port/9-Port) *
Return Value
Maximum value of max value of IPv4 ignore bits field in ALE table
| void CSL_CPSW_clearAleEntry | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index | ||
| ) |
============================================================================
CSL_CPSW_clearAleEntry
Description
This function clears the ALE entry corresponding to the index specified
Arguments
index ALE table index. *
Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_ALE_TBLCTL_TABLEIDX, ALE_ALE_TBLCTL_TABLEWR=1 ALE_TABLE_WORD0=0, ALE_TABLE_WORD1=0, ALE_TABLE_WORD2=0
Example
Uint32 index;
index = 0;
CSL_CPSW_clearAleEntry (index);| void CSL_CPSW_getAlePortControlReg | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | portNo, | ||
| CSL_CPSW_ALE_PORTCONTROL * | pPortControlInfo | ||
| ) |
============================================================================
CSL_CPSW_getAlePortControlReg
Description
This function retrieves the contents of ALE Port control register corresponding to the port number specified.
Arguments
portNo Port number for which the ALE port control register
must be read.
pPortControlInfo CSL_CPSW_ALE_PORTCONTROL structure that needs to be
filled with Port control register info read from
the hardware.
* Return Value
None
Pre Condition
None
Post Condition
None
Reads
ALE_I0_ALE_PORTCTL0_I0_REG_P0_PORTSTATE, ALE_I0_ALE_PORTCTL0_I0_REG_P0_DROP_UN_TAGGED, ALE_I0_ALE_PORTCTL0_I0_REG_P0_VID_INGRESS_CHECK, ALE_I0_ALE_PORTCTL0_I0_REG_P0_NO_LEARN, ALE_I0_ALE_PORTCTL0_I0_REG_P0_NO_SA_UPDATE, ALE_I0_ALE_PORTCTL0_I0_REG_P0_MACONLY, ALE_I0_ALE_PORTCTL0_I0_REG_P0_DIS_PAUTHMOD, ALE_I0_ALE_PORTCTL0_I0_REG_P0_MACONLY_CAF, ALE_I0_ALE_PORTCTL0_I0_REG_P0_MCAST_LIMIT, ALE_I0_ALE_PORTCTL0_I0_REG_P0_BCAST_LIMIT
Example
Uint32 index;
CSL_CPSW_ALE_PORTCONTROL portControlInfo;
index = 0;
CSL_CPSW_getAlePortControlReg (index, &portControlInfo);| void CSL_CPSW_setAlePortControlReg | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | portNo, | ||
| CSL_CPSW_ALE_PORTCONTROL * | pPortControlInfo | ||
| ) |
============================================================================
CSL_CPSW_setAlePortControlReg
Description
This function sets up the contents of ALE Port control register corresponding to the port number specified.
Arguments
portNo Port number for which the ALE port control register
must be configured.
pPortControlInfo CSL_CPSW_ALE_PORTCONTROL structure that contains
port control register settings to be written.
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_I0_ALE_PORTCTL0_I0_REG_P0_PORTSTATE, ALE_I0_ALE_PORTCTL0_I0_REG_P0_DROP_UN_TAGGED, ALE_I0_ALE_PORTCTL0_I0_REG_P0_VID_INGRESS_CHECK, ALE_I0_ALE_PORTCTL0_I0_REG_P0_NO_LEARN, ALE_I0_ALE_PORTCTL0_I0_REG_P0_NO_SA_UPDATE, ALE_I0_ALE_PORTCTL0_I0_REG_P0_MACONLY, ALE_I0_ALE_PORTCTL0_I0_REG_P0_DIS_PAUTHMOD, ALE_I0_ALE_PORTCTL0_I0_REG_P0_MACONLY_CAF, ALE_I0_ALE_PORTCTL0_I0_REG_P0_MCAST_LIMIT, ALE_I0_ALE_PORTCTL0_I0_REG_P0_BCAST_LIMIT
Example
Uint32 index;
CSL_CPSW_ALE_PORTCONTROL portControlInfo;
index = 0;
portControlInfo.portState = ALE_PORTSTATE_FORWARD |
ALE_PORTSTATE_LEARN;
CSL_CPSW_setAlePortControlReg (index, &portControlInfo);| void CSL_CPSW_setAlePortControlTrunk | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | portNo, | ||
| bool | trunkEnable, | ||
| Uint32 | trunkNum | ||
| ) |
| void CSL_CPSW_getAlePortState | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | portNo, | ||
| CSL_CPSW_ALE_PORTSTATE * | pPortState | ||
| ) |
============================================================================
CSL_CPSW_getAlePortControlReg
| void CSL_CPSW_setAlePortState | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | portNo, | ||
| CSL_CPSW_ALE_PORTSTATE | portState | ||
| ) |
============================================================================
CSL_CPSW_setAlePortControlReg
| void CSL_CPSW_setAlePortMirrorSouce | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | portNo, | ||
| bool | enableMirror | ||
| ) |
============================================================================
CSL_CPSW_setAlePortControlReg
| void CSL_CPSW_setAleCtrl2MirrorMatchIndex | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | mirrorMatchIndex | ||
| ) |
============================================================================
CSL_CPSW_setAleCtrl2MirrorMatchIndex
| void CSL_CPSW_setAleCtrl2TrunkParams | ( | CSL_AleRegs * | hCpswAleRegs, |
| CSL_CPSW_ALE_CTRL2_TRUNK_CONFIG * | trunkCfg | ||
| ) |
============================================================================
CSL_CPSW_setAleCtrl2MirrorMatchIndex
| void CSL_CPSW_setAleCtrl2IPPktFilterConfig | ( | CSL_AleRegs * | hCpswAleRegs, |
| CSL_CPSW_ALE_CTRL2_IPPKTFLT_CONFIG * | ipPktFltCfg | ||
| ) |
============================================================================
CSL_CPSW_setAleCtrl2IPPktFilterConfig
| void CSL_CPSW_setAleCtrl2MalformedFrameConfig | ( | CSL_AleRegs * | hCpswAleRegs, |
| CSL_CPSW_ALE_CTRL2_MALFORMEDFRAME_CONFIG * | badFrmCfg | ||
| ) |
============================================================================
CSL_CPSW_setAleCtrl2MalformedPktConfig
| void CSL_CPSW_setAleIPNxtHdrWhitelist | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint8 | ipNxtHdr0, | ||
| Uint8 | ipNxtHdr1, | ||
| Uint8 | ipNxtHdr2, | ||
| Uint8 | ipNxtHdr3 | ||
| ) |
============================================================================
CSL_CPSW_setIPNxtHdrList
| void CSL_CPSW_getAlePolicerGlobConfig | ( | CSL_AleRegs * | hCpswAleRegs, |
| CSL_CPSW_ALE_POLICER_GLOB_CONFIG * | pGlobConfig | ||
| ) |
============================================================================
CSL_CPSW_getAlePolicerGlobConfig
Description
This function retrieves the contents of the CPSW ALE Policer/Classifier Global Configuration.
Arguments
pGlobConfig CSL_CPSW_ALE_POLICER_GLOB_CONFIG structure that needs to
be populated with the contents of the corresponging ALE Policer
global control registers.
* Return Value
None
Pre Condition
None
Post Condition
None
Reads
ALE_THREADMAPDEF_DEFTHREAD_EN, ALE_THREADMAPDEF_DEFTHREADVAL
@b Example
CSL_CPSW_ALE_POLICER_GLOB_CONFIG globConfig;
CSL_CPSW_getAlePolicerGlobConfig (&globConfig);| void CSL_CPSW_setAlePolicerGlobConfig | ( | CSL_AleRegs * | hCpswAleRegs, |
| CSL_CPSW_ALE_POLICER_GLOB_CONFIG * | pGlobConfig | ||
| ) |
============================================================================
CSL_CPSW_setAlePolicerGlobConfig
Description
This function sets up the contents of the CPSW ALE Policer/Classifier global registers per user-specified ALE Policer Global Configuration.
Arguments
pGlobConfig CSL_CPSW_ALE_POLICER_GLOB_CONFIG structure that holds the values
that need to be configured to the ALE Policer global control
registers.
* Return Value
None
Pre Condition
None
Post Condition
CPSW ALE Policer Global control register modified with values provided.
Writes
ALE_THREADMAPDEF_DEFTHREAD_EN, ALE_THREADMAPDEF_DEFTHREADVAL
Example
CSL_CPSW_ALE_POLICER_GLOB_CONFIG globConfig;
globConfig.defThreadEnable = 1;
...
CSL_CPSW_setAlePolicerGlobConfig (&globConfig);| void CSL_CPSW_getAlePolicerEntry | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index, | ||
| CSL_CPSW_ALE_POLICER_ENTRY * | pPolCfg | ||
| ) |
============================================================================
CSL_CPSW_getAlePolicerEntry
Description
This function reads the ALE Policer table entry for the index specified and fills the output parameter structure with Policer configuration read from the hardware.
Arguments
index ALE Policer table index to be read.
pPolCfg ALE Policer entry contents read.
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_POLICETBLCTL_POL_TBL_IDX ALE_POLICETBLCTL_WRITE_ENABLE=0 ALE_THREADMAPCTL_CLASSINDEX
Reads
ALE_POLICECFG0_PORT_MEN, ALE_POLICECFG0_PORT_NUM, ALE_POLICECFG0_PRI_MEN, ALE_POLICECFG0_PRI_VAL, ALE_POLICECFG0_ONU_MEN, ALE_POLICECFG0_ONU_INDEX, ALE_POLICECFG1_DST_MEN, ALE_POLICECFG1_DST_INDEX, ALE_POLICECFG1_SRC_MEN, ALE_POLICECFG1_SRC_INDEX, ALE_POLICECFG2_OVLAN_MEN, ALE_POLICECFG2_OVLAN_INDEX, ALE_POLICECFG2_IVLAN_MEN, ALE_POLICECFG2_IVLAN_INDEX, ALE_POLICECFG3_ETHERTYPE_MEN, ALE_POLICECFG3_ETHERTYPE_INDEX, ALE_POLICECFG3_IPSRC_MEN, ALE_POLICECFG3_IPSRC_INDEX, ALE_POLICECFG4_IPDST_MEN, ALE_POLICECFG4_IPDST_INDEX, ALE_THREADMAPVAL_THREAD_EN, ALE_THREADMAPVAL_THREADVAL
Example
Uint32 index;
CSL_CPSW_ALE_POLICER_ENTRY polCfg;
index = 0;
// Read Policer Entry config from hardware
CSL_CPSW_getAlePolicerEntry (index, &polCfg);| void CSL_CPSW_setAlePolicerEntry | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index, | ||
| CSL_CPSW_ALE_POLICER_ENTRY * | pPolCfg | ||
| ) |
============================================================================
CSL_CPSW_setAlePolicerEntry
Description
This function sets up the ALE table entry for the index specified with VLAN configuration specified here.
Arguments
index ALE table index.
pPolCfg ALE entry contents to be configured.
* Return Value
None
Pre Condition
None
Post Condition
None
Writes
ALE_POLICETBLCTL_POL_TBL_IDX ALE_POLICETBLCTL_WRITE_ENABLE=1 ALE_THREADMAPCTL_CLASSINDEX ALE_POLICECFG0_PORT_MEN, ALE_POLICECFG0_PORT_NUM, ALE_POLICECFG0_PRI_MEN, ALE_POLICECFG0_PRI_VAL, ALE_POLICECFG0_ONU_MEN, ALE_POLICECFG0_ONU_INDEX, ALE_POLICECFG1_DST_MEN, ALE_POLICECFG1_DST_INDEX, ALE_POLICECFG1_SRC_MEN, ALE_POLICECFG1_SRC_INDEX, ALE_POLICECFG2_OVLAN_MEN, ALE_POLICECFG2_OVLAN_INDEX, ALE_POLICECFG2_IVLAN_MEN, ALE_POLICECFG2_IVLAN_INDEX, ALE_POLICECFG3_ETHERTYPE_MEN, ALE_POLICECFG3_ETHERTYPE_INDEX, ALE_POLICECFG3_IPSRC_MEN, ALE_POLICECFG3_IPSRC_INDEX, ALE_POLICECFG4_IPDST_MEN, ALE_POLICECFG4_IPDST_INDEX, ALE_THREADMAPVAL_THREAD_EN, ALE_THREADMAPVAL_THREADVAL
Example
Uint32 index;
CSL_CPSW_ALE_POLICER_ENTRY polCfg;
index = 0;
polCfg.vlanId = 0x10;
...
// Add ALE Policer entry
CSL_CPSW_setAlePolicerEntry (index, &polCfg);| void CSL_CPSW_disableAlePolicerThread | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | index | ||
| ) |
| void CSL_CPSW_setAleUnknwnVlanMemberReg | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | aleUnknwnVlanMemberVal | ||
| ) |
============================================================================
CSL_CPSW_setAleUnknwnVlanMemberReg
Description
This function sets up the contents of the ALE unknown vlan register.
Arguments
aleUnknwnVlanVal Value to be configured to the ALE unknown vlan reg *
Return Value
None
Pre Condition
None
Post Condition
None
Writes
UNKNOWN_VLAN_REG
Example
* Uint32 aleUnknwnVlanVal = 0;
CSL_CPSW_getAleUnknwnVlanReg (&aleUnknwnVlanVal);
aleUnknwnVlanVal |= CSL_XGE_CPSW_ALECONTROL_CLRTABLE_EN;
CSL_CPSW_setAleUnknwnVlanReg (aleUnknwnVlanVal);| void CSL_CPSW_setAleUnknwnVlanUntagReg | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | aleUnknwnVlanUntagVal | ||
| ) |
============================================================================
CSL_CPSW_setAleUnknwnVlanUntagReg
Description
This function sets up the contents of the ALE unknown vlan register.
Arguments
aleUnknwnVlanVal Value to be configured to the ALE unknown vlan reg *
Return Value
None
Pre Condition
None
Post Condition
None
Writes
UNKNOWN_VLAN_REG
Example
* Uint32 aleUnknwnVlanVal = 0;
CSL_CPSW_getAleUnknwnVlanReg (&aleUnknwnVlanVal);
aleUnknwnVlanVal |= CSL_XGE_CPSW_ALECONTROL_CLRTABLE_EN;
CSL_CPSW_setAleUnknwnVlanReg (aleUnknwnVlanVal);| void CSL_CPSW_setCppiP0Control | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| CSL_CPSW_CPPI_P0_CONTROL * | pCppiP0ControlCfg | ||
| ) |
============================================================================
CSL_CPSW_setCppiP0Control
Description
This function sets the P0_CONTROL_REG register contents.
Arguments
* pCppiP0ControlCfg P0_CONTROL_REG configuration structure *
Return Value
none
| void CSL_CPSW_setAleUnknwnVlanUnregMcastReg | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | aleUnknwnVlanUnregMcastVal | ||
| ) |
| void CSL_CPSW_setAleUnknwnVlanRegMcastReg | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | aleUnknwnVlanRegMcastVal | ||
| ) |
| void CSL_CPSW_setAlePolicerControlReg | ( | CSL_AleRegs * | hCpswAleRegs, |
| CSL_CPSW_ALE_POLICER_CONTROL * | policerCntrlCfg | ||
| ) |
| void CSL_CPSW_getAlePolicerControlReg | ( | CSL_AleRegs * | hCpswAleRegs, |
| CSL_CPSW_ALE_POLICER_CONTROL * | policerCntrlCfg | ||
| ) |
| void CSL_CPSW_setAlePolicerTestControlReg | ( | CSL_AleRegs * | hCpswAleRegs, |
| CSL_CPSW_ALE_POLICER_TEST_CONTROL * | policerTestCntrlCfg | ||
| ) |
| void CSL_CPSW_getAlePolicerHstatReg | ( | CSL_AleRegs * | hCpswAleRegs, |
| CSL_CPSW_ALE_POLICER_HSTAT * | policerHStatCfg | ||
| ) |
| void CSL_CPSW_setAleOAMLpbkControl | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 | lpbkEnablePortMask | ||
| ) |
============================================================================
CSL_CPSW_setAleOAMLpbkControl
| void CSL_CPSW_getAleStatusNumPolicers | ( | CSL_AleRegs * | hCpswAleRegs, |
| Uint32 * | pNumPolicers | ||
| ) |
| void CSL_CPSW_setCppiPriCirEir | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | pri, | ||
| Uint32 | cir, | ||
| Uint32 | eir | ||
| ) |
| void CSL_CPSW_getCppiPriCirEir | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | pri, | ||
| Uint32 * | cir, | ||
| Uint32 * | eir | ||
| ) |
| void CSL_CPSW_setPriCirEir | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNo, | ||
| Uint32 | pri, | ||
| Uint32 | cir, | ||
| Uint32 | eir | ||
| ) |
| void CSL_CPSW_getPriCirEir | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNo, | ||
| Uint32 | pri, | ||
| Uint32 * | cir, | ||
| Uint32 * | eir | ||
| ) |
| void CSL_CPSW_setCppiRxPriFlowControl | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint8 | pri | ||
| ) |
| Uint8 CSL_CPSW_getCppiRxPriFlowControl | ( | CSL_Xge_cpswRegs * | hCpswRegs | ) |
| void CSL_CPSW_setCppiTxDstThresholdSetX | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | pri, | ||
| Uint32 | setVal | ||
| ) |
| Uint32 CSL_CPSW_getCppiTxDstThresholdSetX | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | pri | ||
| ) |
| void CSL_CPSW_setCppiTxDstThresholdClrX | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | pri, | ||
| Uint32 | setVal | ||
| ) |
| Uint32 CSL_CPSW_getCppiDstTxThresholdClrX | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | pri | ||
| ) |
| void CSL_CPSW_setCppiTxGlobalBufThresholdSetX | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | pri, | ||
| Uint32 | setVal | ||
| ) |
| Uint32 CSL_CPSW_getCppiTxGlobalBufThresholdSetX | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | pri | ||
| ) |
| void CSL_CPSW_setCppiTxGlobalBufThresholdClrX | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | pri, | ||
| Uint32 | setVal | ||
| ) |
| Uint32 CSL_CPSW_getCppiTxGlobalBufThresholdClrX | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | pri | ||
| ) |
| void CSL_CPSW_setcppiTxBlksPri | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint8 | pri, | ||
| Uint32 | blks | ||
| ) |
| Uint32 CSL_CPSW_getCppiTxBlksPri | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint8 | pri | ||
| ) |
| void CSL_CPSW_setTxBlksPri | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNo, | ||
| Uint8 | pri, | ||
| Uint32 | blks | ||
| ) |
| Uint32 CSL_CPSW_getTxBlksPri | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNo, | ||
| Uint8 | pri | ||
| ) |
| void CSL_CPSW_setTxPriFlowControl | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNo, | ||
| Uint8 | pri | ||
| ) |
| Uint8 CSL_CPSW_getTxPriFlowControl | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNo | ||
| ) |
| void CSL_CPSW_setRxPriFlowControl | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNo, | ||
| Uint8 | pri | ||
| ) |
| Uint8 CSL_CPSW_getRxPriFlowControl | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNo | ||
| ) |
| Uint32 CSL_CPSW_getTxHostBlksRem | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNo | ||
| ) |
| void CSL_CPSW_setTxHostBlksRem | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNo, | ||
| Uint32 | txBlksRem | ||
| ) |
| void CSL_CPSW_setTxDstThresholdSetX | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNo, | ||
| Uint32 | pri, | ||
| Uint32 | setVal | ||
| ) |
| Uint32 CSL_CPSW_getTxDstThresholdSetX | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNo, | ||
| Uint32 | pri | ||
| ) |
| void CSL_CPSW_setTxDstThresholdClrX | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNo, | ||
| Uint32 | pri, | ||
| Uint32 | setVal | ||
| ) |
| Uint32 CSL_CPSW_getTxDstThresholdClrX | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNo, | ||
| Uint32 | pri | ||
| ) |
| void CSL_CPSW_setTxGlobalBufThresholdSetX | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNo, | ||
| Uint32 | pri, | ||
| Uint32 | setVal | ||
| ) |
| Uint32 CSL_CPSW_getTxGlobalBufThresholdSetX | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNo, | ||
| Uint32 | pri | ||
| ) |
| void CSL_CPSW_setTxGlobalBufThresholdClrX | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNo, | ||
| Uint32 | pri, | ||
| Uint32 | setVal | ||
| ) |
| Uint32 CSL_CPSW_getTxGlobalBufThresholdClrX | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNo, | ||
| Uint32 | pri | ||
| ) |
| void CSL_CPSW_setTxDstBasedOutFlowAddValX | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNo, | ||
| Uint32 | pri, | ||
| Uint32 | addVal | ||
| ) |
| Uint32 CSL_CPSW_getTxDstBasedOutFlowAddValX | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | portNo, | ||
| Uint32 | pri | ||
| ) |
| void CSL_CPSW_setTxGlobalOutFlowThresholdSetX | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | pri, | ||
| Uint32 | setVal | ||
| ) |
| Uint32 CSL_CPSW_getTxGlobalOutFlowThresholdSetX | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | pri | ||
| ) |
| void CSL_CPSW_setTxGlobalOutFlowThresholdClrX | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | pri, | ||
| Uint32 | setVal | ||
| ) |
| Uint32 CSL_CPSW_getTxGlobalOutFlowThresholdClrX | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | pri | ||
| ) |
| void CSL_CPSW_setCpswTxGlobalBufThresholdSetX | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | pri, | ||
| Uint32 | setVal | ||
| ) |
| Uint32 CSL_CPSW_getCpswTxGlobalBufThresholdSetX | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | pri | ||
| ) |
| void CSL_CPSW_setCpswTxGlobalBufThresholdClrX | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | pri, | ||
| Uint32 | setVal | ||
| ) |
| Uint32 CSL_CPSW_getCpswTxGlobalBufThresholdClrX | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | pri | ||
| ) |
| Uint32 CSL_CPSW_isP0TxCastagnoliCRCEnabled | ( | CSL_Xge_cpswRegs * | hCpswRegs | ) |
============================================================================
CSL_CPSW_isP0TxCastagnoliCRCEnabled
Description
This function indicates if Castagnoli CRC is enabled in the CPSW control register for host port.
Return Value
TRUE Castagnoli CRC enabled
FALSE Castagnoli CRC disabled.
| void CSL_CPSW_enableP0TxCastagnoliCRC | ( | CSL_Xge_cpswRegs * | hCpswRegs | ) |
============================================================================
CSL_CPSW_enableP0TxCastagnoliCRC
Description
This function configures the CPSW control register to enable Castagnoli CRC for host port specified.
Return Value
None
| void CSL_CPSW_disableP0TxCastagnoliCRC | ( | CSL_Xge_cpswRegs * | hCpswRegs | ) |
============================================================================
CSL_CPSW_disableP0TxCastagnoliCRC
Description
This function configures the CPSW control register to disable Castagnoli CRC for host port.
Return Value
None
| void CSL_CPSW_getPTypeReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| CSL_CPSW_PTYPE * | pPtypeCfg | ||
| ) |
============================================================================
CSL_CPSW_getPTypeReg
Description
This function retrieves the contents of the CPSW PTYPE register.
Arguments
pPtypeCfg CSL_CPSW_PTYPE structure that needs to be populated
with the CPSW PTYPE register contents.
* Return Value
None
| void CSL_CPSW_setPTypeReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| CSL_CPSW_PTYPE * | pPtypeCfg | ||
| ) |
============================================================================
CSL_CPSW_setPTypeReg
Description
This function retrieves the contents of the CPSW PTYPE register.
Arguments
pPtypeCfg CSL_CPSW_PTYPE structure that has the
CPSW PTYPE register configuration.
* Return Value
None
| void CSL_CPSW_getThruRateReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| CSL_CPSW_THRURATE * | pThruRateCfg | ||
| ) |
============================================================================
CSL_CPSW_getThruRateReg
Description
This function retrieves the contents of the CPSW_THRU_RATE register.
Arguments
pThruRateCfg CSL_CPSW_THRURATE structure that needs to be populated
with the CPSW_THRU_RATE register contents.
* Return Value
None
| Uint32 CSL_CPSW_getGapThreshold | ( | CSL_Xge_cpswRegs * | hCpswRegs | ) |
============================================================================
CSL_CPSW_getGapThreshold
Description
This function retrieves the contents of the GAP_THRESH_REG register.
The Ethernet port transmit inter-packet gap (IPG) may be shortened by eight bit times when short gap is enabled and triggered. Setting the pn_tx_short_gap_en bit each Enet_Pn_Mac_Control register enables the gap to be shortened when triggered. The condition is triggered when the ports associated transmit packet FIFO has a user defined number of FIFO blocks used. The associated transmit FIFO blocks used value determines if the gap is shortened, and so on. The Gap_Thresh register value determines the short gap threshold. If the FIFO blocks used is greater than or equal to the Gap_Thresh value then short gap is triggered Arguments
* none *
Return Value
Gap threshold configured
| void CSL_CPSW_setGapThreshold | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | gapThreshold | ||
| ) |
============================================================================
CSL_CPSW_setGapThreshold
Description
This function retrieves the contents of the GAP_THRESH_REG register.
The Ethernet port transmit inter-packet gap (IPG) may be shortened by eight bit times when short gap is enabled and triggered. Setting the pn_tx_short_gap_en bit each Enet_Pn_Mac_Control register enables the gap to be shortened when triggered. The condition is triggered when the ports associated transmit packet FIFO has a user defined number of FIFO blocks used. The associated transmit FIFO blocks used value determines if the gap is shortened, and so on. The Gap_Thresh register value determines the short gap threshold. If the FIFO blocks used is greater than or equal to the Gap_Thresh value then short gap is triggered Arguments
* gapThreshold Ethernet Port Short Gap Threshold - * This is the Ethernet port associated FIFO transmit * block usage value for triggering transmit short gap * (when short gap is enabled) *
Return Value
Gap threshold configured
| Uint32 CSL_CPSW_getTxStartWords | ( | CSL_Xge_cpswRegs * | hCpswRegs | ) |
============================================================================
CSL_CPSW_getTxStartWdsReg
Description
This function retrieves the contents of the TX_START_WDS_REG register.
FIFO Packet Transmit (egress) Start Words. This value is the number of required 32-byte packet words in an Ethernet transmit FIFO before the packet egress will begin. This value is non-zero to preclude Ethernet transmit underrun. Decimal 8 is the recommended value. It should not be increased unnecessarily to prevent adding to the switch latency
Arguments
* none *
Return Value
Gap threshold configured
| Uint32 CSL_CPSW_getTxMaxLenPerPriority | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | priority | ||
| ) |
============================================================================
CSL_CPSW_getTxMaxLenPerPriority
Description
This function retrieves the max tx packet length per switch priority.
Arguments
* priority Priority for which tx max packet length is queried (0 -7) *
Return Value
Max tx packet length for given priority
| void CSL_CPSW_setTxMaxLenPerPriority | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | priority, | ||
| Uint32 | maxLen | ||
| ) |
============================================================================
CSL_CPSW_setTxMaxLenPerPriority
Description
This function sets the max tx packet length per switch priority.
Arguments
* priority Priority for which tx max packet length is set (0 -7) * maxLen Tx max packet length to be set *
Return Value
Max tx packet length for given priority
| void CSL_CPSW_getCppiP0Control | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| CSL_CPSW_CPPI_P0_CONTROL * | pCppiP0ControlCfg | ||
| ) |
============================================================================
CSL_CPSW_getCppiP0Control
Description
This function gets the P0_CONTROL_REG register contents.
Arguments
* pCppiP0ControlCfg P0_CONTROL_REG configuration structure *
Return Value
none
| void CSL_CPSW_setCppiRxPType | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | p0RxPtype | ||
| ) |
============================================================================
CSL_CPSW_setCppiRxPType
Description
This function sets the P0 Receive priority type
Arguments
* p0RxPtype Receive Priority Type * 0 - Fixed priority * 1 - Round Robin priority *
Return Value
none
| Uint32 CSL_CPSW_getCppiRxPType | ( | CSL_Xge_cpswRegs * | hCpswRegs | ) |
============================================================================
CSL_CPSW_getCppiRxPType
Description
This function gets the P0 Receive priority type
Arguments
* none *
Return Value
p0RxPtype Receive Priority Type 0 - Fixed priority 1 - Round Robin priority
| Uint32 CSL_CPSW_getCppiRxPacketsPriority | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | priority | ||
| ) |
============================================================================
CSL_CPSW_getCppiRxPacketsPriority
Description
This function gets Port 0 Receive (same as Port 1 Transmit) Packets Per Priority This function is applicable for 2 port switch
Arguments
* priority Priority for which number of rx packets is queried *
Return Value
rxPackets Number of rx packets for queried priority
| void CSL_CPSW_setCppiRxPacketsPriority | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| Uint32 | priority, | ||
| Uint32 | rxPackets | ||
| ) |
============================================================================
CSL_CPSW_setCppiRxPacketsPriority
Description
This function gets Port 0 Receive (same as Port 1 Transmit) Packets Per Priority This function is applicable for 2 port switch
Arguments
* priority Priority for which number of rx packets is to be set * rxPackets Number of rx packets to be set *
Return Value
none
| void CSL_CPSW_getCppiRxGapReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| CSL_CPSW_CPPI_P0_RXGAP * | pCppiRxGap | ||
| ) |
============================================================================
CSL_CPSW_getCppiRxGapReg
Description
This function gets CPPI_P0_Rx_Gap This function is applicable for 2 port switch
Arguments
* pCppiRxGap CPPI_P0_Rx_Gap register configuration *
Return Value
none
| void CSL_CPSW_setCppiRxGapReg | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| CSL_CPSW_CPPI_P0_RXGAP * | pCppiRxGap | ||
| ) |
============================================================================
CSL_CPSW_setCppiRxGapReg
Description
This function sets CPPI_P0_Rx_Gap This function is applicable for 2 port switch
Arguments
* pCppiRxGap CPPI_P0_Rx_Gap register configuration *
Return Value
none
| void CSL_CPSW_getP0FifoStatus | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| CSL_CPSW_CPPI_P0_FIFOSTATUS * | pCppiFifoStats | ||
| ) |
============================================================================
CSL_CPSW_getP0FifoStatus
Description
This function gets CPPI_P0_FIFO_Status register This function is will return 0 for 2 port switch as there is no Tx FIFO
Arguments
* pCppiFifoStats CPPI_P0_FIFO_Status register configuration *
Return Value
none
| void CSL_CPSW_getP0HostBlksPri | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| CSL_CPSW_CPPI_P0_HOSTBLKSPRI * | pCppiHostBlksPri | ||
| ) |
============================================================================
CSL_CPSW_getP0HostBlksPri
Description
This function gets CPPI_P0_Host_Blks_Pri register This function is not applicable to two port switch
Arguments
* pCppiHostBlksPri CPPI_P0_Host_Blks_Pri register configuration *
Return Value
none
| void CSL_CPSW_setP0HostBlksPri | ( | CSL_Xge_cpswRegs * | hCpswRegs, |
| CSL_CPSW_CPPI_P0_HOSTBLKSPRI * | pCppiHostBlksPri | ||
| ) |
============================================================================
CSL_CPSW_setP0HostBlksPri
Description
This function sets CPPI_P0_Host_Blks_Pri register This function is not applicable to two port switch
Arguments
* pCppiHostBlksPri CPPI_P0_Host_Blks_Pri register configuration *
Return Value
none
1.8.11