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PDK API Guide for J721E
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Data Structures | |
| struct | CSL_CPSW_VERSION |
| Holds the Time sync submodule's version info. More... | |
| struct | CSL_CPSW_CONTROL |
| Holds CPSW control register contents. More... | |
| struct | CSL_CPSW_THRURATE |
| CPSW_THRU_RATE register. More... | |
| struct | CSL_CPSW_CPPI_P0_CONTROL |
| Holds CPPI P0 Control register contents. More... | |
| struct | CSL_CPSW_CPPI_P0_RXGAP |
| Holds CPPI_P0_Rx_Gap register contents. This is applicable only for 2 port switch. More... | |
| struct | CSL_CPSW_CPPI_P0_FIFOSTATUS |
| Holds CPPI_P0_FIFO_Status register contents. This is not applicable for 2 port switch. More... | |
| struct | CSL_CPSW_CPPI_P0_HOSTBLKSPRI |
| Holds CSL_CPSW_CPPI_P0_HOSTBLKSPRI register contents. This is not used for 2 port switch. More... | |
| struct | CSL_CPSW_FLOWCNTL |
| Holds flow control register contents. More... | |
| struct | CSL_CPSW_ALE_VERSION |
| Holds the ALE submodule's version info. More... | |
| struct | CSL_CPSW_ALE_PORTCONTROL |
| Holds the ALE Port control register info. More... | |
| struct | CSL_CPSW_ALE_MCASTADDR_ENTRY |
| Holds the ALE Multicast Address Table entry configuration. More... | |
| struct | CSL_CPSW_ALE_VLANMCASTADDR_ENTRY |
| Holds the ALE VLAN/Multicast Address Table entry configuration. More... | |
| struct | CSL_CPSW_ALE_UNICASTADDR_ENTRY |
| Holds the ALE Unicast Address Table entry configuration. More... | |
| struct | CSL_CPSW_ALE_OUIADDR_ENTRY |
| Holds the ALE OUI Unicast Address Table entry configuration. More... | |
| struct | CSL_CPSW_ALE_VLANUNICASTADDR_ENTRY |
| Holds the ALE VLAN Unicast Address Table entry configuration. More... | |
| struct | CSL_CPSW_ALE_VLAN_ENTRY |
| Holds the ALE (Inner) VLAN Table entry configuration. More... | |
| struct | CSL_CPSW_ALE_ETHERTYPE_ENTRY |
| Holds the ALE Ethertype Table entry configuration. More... | |
| struct | CSL_CPSW_ALE_IPv4_ENTRY |
| Holds the ALE IPv4 Address Table entry configuration. More... | |
| struct | CSL_CPSW_ALE_IPv6_ENTRY |
| Holds the ALE IPv6 Address Table entry configuration. More... | |
| struct | CSL_CPSW_PORTSTAT |
| Holds Port Statistics Enable register contents. More... | |
| struct | CSL_CPSW_TSCNTL |
| Holds Port Time Sync Control register contents. More... | |
| struct | CSL_CPSW_TSCONFIG |
| Holds Port Time Sync Configuration contents. More... | |
| struct | CSL_CPSW_PORT_CONTROL |
| Holds CPSW Port Control contents. More... | |
| struct | CSL_CPSW_RX_RATE_LIMIT_CONFIG |
| Holds CPSW Port Rx Rate Limit Configuration for CPPI Port Ingress Rate Limitaion Operation. More... | |
| struct | CSL_CPSW_EEE_GLOB_CONFIG |
| Holds CPSW EEE (Energy Efficient Ethernet) Global Configuration. More... | |
| struct | CSL_CPSW_EEE_PORT_CONFIG |
| Holds CPSW EEE (Energy Efficient Ethernet) Per-Port Configuration. More... | |
| struct | CSL_CPSW_EEE_PORT_STATUS |
| Holds CPSW EEE (Energy Efficient Ethernet) Per-Port STATUS. More... | |
| struct | CSL_CPSW_ALE_POLICER_GLOB_CONFIG |
| Holds CPSW Policer Global Configuration. More... | |
| struct | CSL_CPSW_ALE_CTRL2_TRUNK_CONFIG |
| struct | CSL_CPSW_ALE_CTRL2_IPPKTFLT_CONFIG |
| struct | CSL_CPSW_ALE_CTRL2_MALFORMEDFRAME_CONFIG |
| struct | CSL_CPSW_ALE_POLICER_ENTRY |
| Holds the ALE Policer Table entry configuration. More... | |
| struct | CSL_CPSW_STATS |
| Holds the EMAC statistics. More... | |
| struct | CSL_CPSW_ALE_POLICER_CONTROL |
| struct | CSL_CPSW_ALE_POLICER_TEST_CONTROL |
| struct | CSL_CPSW_ALE_POLICER_HSTAT |
| struct | CSL_CPSW_PTYPE |
| Holds CPSW priority type register contents. More... | |
| struct | CSL_CPSW_INTERVLANCFG |
| Holds the Port intervlan configuration info. More... | |
| struct | CSL_CPGMAC_SL_FIFOSTATUS |
| Holds the Enet_Pn_FIFO_Status register contents. More... | |
Typedefs | |
| typedef CSL_CPSW_ALE_VLAN_ENTRY | CSL_CPSW_ALE_OUTER_VLAN_ENTRY |
| Holds the ALE Outer VLAN Table entry configuration. More... | |
| #define CSL_CPSW_ALECONTROL_RATELIMIT_EN (1 << 0u) |
ALE control register configuration definitions.
Enable Broadcast/Multicast rate limit
| #define CSL_CPSW_ALECONTROL_AUTHMODE_EN (1 << 1u) |
MAC auhorization mode enable
| #define CSL_CPSW_ALECONTROL_VLANAWARE_EN (1 << 2u) |
VLAN Aware Mode enable
| #define CSL_CPSW_ALECONTROL_RATELIMIT_TX_EN (1 << 3u) |
Tx rate limit enable
| #define CSL_CPSW_ALECONTROL_OUIDENY_EN (1 << 5u) |
OUI deny enable
| #define CSL_CPSW_ALECONTROL_VID0MODE_EN (1 << 6u) |
VID0 mode enable
| #define CSL_CPSW_ALECONTROL_LEARN_NO_VID_EN (1 << 7u) |
Learn no VID enable
| #define CSL_CPSW_ALECONTROL_AGEOUT_NOW_EN (1 << 29u) |
Age out now enable
| #define CSL_CPSW_ALECONTROL_CLRTABLE_EN (1 << 30u) |
Clear table enable
| #define CSL_CPSW_ALECONTROL_ALE_EN (1 << 31u) |
ALE enable
| #define CSL_CPSW_PORTMASK_PORT0_EN (1 << 0u) |
Port Mask definitions.
Port 0 Enable
| #define CSL_CPSW_PORTMASK_PORT1_EN (1 << 1u) |
Port 1 Enable
| #define CSL_CPSW_PORTMASK_PORT2_EN (1 << 2u) |
Port 2 Enable
| #define CSL_CPSW_PORTMASK_PORT3_EN (1 << 3u) |
Port 3 Enable
| #define CSL_CPSW_PORTMASK_PORT4_EN (1 << 4u) |
Port 4 Enable
| #define CSL_CPSW_PORTMASK_PORT5_EN (1 << 5u) |
Port 5 Enable
| #define CSL_CPSW_PORTMASK_PORT6_EN (1 << 6u) |
Port 6 Enable
| #define CSL_CPSW_PORTMASK_PORT7_EN (1 << 7u) |
Port 7 Enable
| #define CSL_CPSW_PORTMASK_PORT8_EN (1 << 8u) |
Port 8 Enable
| #define CSL_ALE_ENTRYTYPE_MAC_ADDR CSL_ALE_ENTRYTYPE_ADDRESS |
ALE Table entry type: MAC ADDRESS.
| #define CSL_ALE_ENTRYTYPE_POLICER CSL_ALE_ENTRYTYPE_VLAN |
ALE Table entry type: POLICER ENTRY.
| #define CSL_CPSW_NUMALE_ENTRIES_MIN (64) |
| #define CSL_CPSW_NUMSTATBLOCKS (9) |
| #define CSL_ALE_TABLE_POLICER_ENUM2REG | ( | policerType | ) | ((policerType) << 0x1) |
| #define CSL_CPSW_ALE_POLICER_PORT_VALID (1 << 0u) |
ALE Policer Entry configuration definitions.
Input EMAC port is used for classification
| #define CSL_CPSW_ALE_POLICER_PRI_VALID (1 << 1u) |
VLAN Priority is used for classification
| #define CSL_CPSW_ALE_POLICER_OUI_VALID (1 << 2u) |
OUI is used for classification
| #define CSL_CPSW_ALE_POLICER_DST_MAC_VALID (1 << 3u) |
Destination MAC is used for classification
| #define CSL_CPSW_ALE_POLICER_SRC_MAC_VALID (1 << 4u) |
Source MAC is used for classification
| #define CSL_CPSW_ALE_POLICER_OVLAN_VALID (1 << 5u) |
Outer VLAN ID is used for classification
| #define CSL_CPSW_ALE_POLICER_VLAN_VALID (1 << 6u) |
(Inner) VLAN ID is used for classification
| #define CSL_CPSW_ALE_POLICER_ETHERTYPE_VALID (1 << 7u) |
Ethertype is used for classification
| #define CSL_CPSW_ALE_POLICER_SRC_IP_VALID ( 1 << 8u) |
Source IP address is used for classification
| #define CSL_CPSW_ALE_POLICER_DST_IP_VALID (1 << 9u) |
Destination IP address is used for classification
| #define CSL_CPSW_ALE_POLICER_THREAD_VALID ( 1 << 10u) |
The specified thread value is used as the CPPI egress thread for any packet that matches the classifier
| #define CSL_CPSW_ALE_POLICER_PIR_VALID ( 1 << 11u) |
The specified pir_idl_inc value is used
| #define CSL_CPSW_ALE_POLICER_CIR_VALID ( 1 << 12u) |
The specified cir_idl_inc value is used
| #define CSL_CPSW_ALE_POLICER_PORT_TRUNK_VALID (1 << 13u) |
Input EMAC port is used for classification
| #define CSL_CPSW_ALE_POLICER_EGRESSOP_VALID (1 << 14u) |
The specified egress op is used
Holds the ALE Outer VLAN Table entry configuration.
Number of statistic blocks.
EMAC has multiple statistics blocks.
STATS0 holds statistics for Host/CPU port (Switch port 0). STATSn holds statistics for MAC ports (Switch ports n).
Defines ALE RAMDEPTH enums for storing IPv6 sliceIndex entry
| Enumerator | |
|---|---|
| CSL_ALE_RAMDEPTH_32 | |
| CSL_ALE_RAMDEPTH_64 |
RAMDEPTH is 32 |
| CSL_ALE_RAMDEPTH_128 |
RAMDEPTH is 32 |
| enum CSL_CPSW_ALE_UPD_BW |
Defines ALE Update Bandwidth Control Value: The upd_bw_ctrl field within ALE control register specifies the rate in which adds, updates, touches, writes, and aging updates can occur. At frequencies of 350Mhz, the table update rate should be at its lowest or 5 Million updates per second. When operating the switch core at frequencies or above, the upd_bw_ctrl can be programmed more aggressive. If the upd_bw_ctrl is set but the frequency of the switch subsystem is below the associated value, ALE will drop packets due to insufficient time to complete lookup under high traffic loads.
1.8.11 
