EDMA3 Driver Optional Setup for EDMA
[EDMA3 Driver Interface Definition]

Data Structures
struct	EDMA3_DRV_ParamentryRegs
	EDMA3 PaRAM Set. More...
struct	EDMA3_DRV_PaRAMRegs
	EDMA3 Parameter RAM Set in User Configurable format. More...
struct	EDMA3_DRV_EvtQuePriority
	Event queue priorities setup. More...
Enumerations
enum	EDMA3_DRV_PaRAMEntry {   EDMA3_DRV_PARAM_ENTRY_OPT = 0,   EDMA3_DRV_PARAM_ENTRY_SRC = 1,   EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT = 2,   EDMA3_DRV_PARAM_ENTRY_DST = 3,   EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX = 4,   EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD = 5,   EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX = 6,   EDMA3_DRV_PARAM_ENTRY_CCNT = 7 }
	PaRAM Set Entry type. More...
enum	EDMA3_DRV_PaRAMField {   EDMA3_DRV_PARAM_FIELD_OPT = 0,   EDMA3_DRV_PARAM_FIELD_SRCADDR = 1,   EDMA3_DRV_PARAM_FIELD_ACNT = 2,   EDMA3_DRV_PARAM_FIELD_BCNT = 3,   EDMA3_DRV_PARAM_FIELD_DESTADDR = 4,   EDMA3_DRV_PARAM_FIELD_SRCBIDX = 5,   EDMA3_DRV_PARAM_FIELD_DESTBIDX = 6,   EDMA3_DRV_PARAM_FIELD_LINKADDR = 7,   EDMA3_DRV_PARAM_FIELD_BCNTRELOAD = 8,   EDMA3_DRV_PARAM_FIELD_SRCCIDX = 9,   EDMA3_DRV_PARAM_FIELD_DESTCIDX = 10,   EDMA3_DRV_PARAM_FIELD_CCNT = 11 }
	PaRAM Set Field type. More...
enum	EDMA3_DRV_IoctlCmd {   EDMA3_DRV_IOCTL_MIN_IOCTL = 0,   EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION,   EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION,   EDMA3_DRV_IOCTL_MAX_IOCTL }
	EDMA3 Driver IOCTL commands. More...
Functions
EDMA3_DRV_Result	EDMA3_DRV_setQdmaTrigWord (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_RM_QdmaTrigWord trigWord)
	Assign a Trigger Word to the specified QDMA channel.
EDMA3_DRV_Result	EDMA3_DRV_setPaRAM (EDMA3_DRV_Handle hEdma, unsigned int lCh, const EDMA3_DRV_PaRAMRegs *newPaRAM)
	Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link).
EDMA3_DRV_Result	EDMA3_DRV_getPaRAM (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMRegs *currPaRAM)
	Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link).
EDMA3_DRV_Result	EDMA3_DRV_setPaRAMEntry (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMEntry paRAMEntry, unsigned int newPaRAMEntryVal)
	Set a particular PaRAM set entry of the specified PaRAM set.
EDMA3_DRV_Result	EDMA3_DRV_getPaRAMEntry (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMEntry paRAMEntry, unsigned int *paRAMEntryVal)
	Get a particular PaRAM set entry of the specified PaRAM set.
EDMA3_DRV_Result	EDMA3_DRV_setPaRAMField (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMField paRAMField, unsigned int newPaRAMFieldVal)
	Set a particular PaRAM set field of the specified PaRAM set.
EDMA3_DRV_Result	EDMA3_DRV_getPaRAMField (EDMA3_DRV_Handle hEdma, unsigned int lCh, EDMA3_DRV_PaRAMField paRAMField, unsigned int *currPaRAMFieldVal)
	Get a particular PaRAM set field of the specified PaRAM set.
EDMA3_DRV_Result	EDMA3_DRV_setEvtQPriority (EDMA3_DRV_Handle hEdma, const EDMA3_DRV_EvtQuePriority *evtQPriObj)
	Sets EDMA TC priority.
EDMA3_DRV_Result	EDMA3_DRV_mapChToEvtQ (EDMA3_DRV_Handle hEdma, unsigned int channelId, EDMA3_RM_EventQueue eventQ)
	Associate Channel to Event Queue.
EDMA3_DRV_Result	EDMA3_DRV_getMapChToEvtQ (EDMA3_DRV_Handle hEdma, unsigned int channelId, unsigned int *mappedEvtQ)
	Get the Event Queue mapped to the specified DMA/QDMA channel.
EDMA3_DRV_Result	EDMA3_DRV_setCCRegister (EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int newRegValue)
	Set the Channel Controller (CC) Register value.
EDMA3_DRV_Result	EDMA3_DRV_getCCRegister (EDMA3_DRV_Handle hEdma, unsigned int regOffset, unsigned int *regValue)
	Get the Channel Controller (CC) Register value.
EDMA3_DRV_Result	EDMA3_DRV_waitAndClearTcc (EDMA3_DRV_Handle hEdma, unsigned int tccNo)
	Wait for a transfer completion interrupt to occur and clear it.
EDMA3_DRV_Result	EDMA3_DRV_checkAndClearTcc (EDMA3_DRV_Handle hEdma, unsigned int tccNo, unsigned short *tccStatus)
	Returns the status of a previously initiated transfer.
EDMA3_DRV_Result	EDMA3_DRV_getPaRAMPhyAddr (EDMA3_DRV_Handle hEdma, unsigned int lCh, unsigned int *paramPhyAddr)
	Get the PaRAM Set Physical Address associated with a logical channel.
EDMA3_DRV_Result	EDMA3_DRV_Ioctl (EDMA3_DRV_Handle hEdma, EDMA3_DRV_IoctlCmd cmd, void *cmdArg, void *param)
	EDMA3 Driver IOCTL.
EDMA3_DRV_Handle	EDMA3_DRV_getInstHandle (unsigned int phyCtrllerInstId, EDMA3_RM_RegionId regionId, EDMA3_DRV_Result *errorCode)
	Return the previously opened EDMA3 Driver Instance handle.

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Detailed Description

Transfer.

The Optional EDMA transfer related Interface of the EDMA3 Driver

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Enumeration Type Documentation

enum EDMA3_DRV_IoctlCmd

EDMA3 Driver IOCTL commands.

Enumerator:

EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION

PaRAM Sets will be cleared OR will not be cleared during allocation, depending upon this option. For e.g., To clear the PaRAM Sets during allocation, cmdArg = (void *)1; To NOT clear the PaRAM Sets during allocation, cmdArg = (void *)0; For all other values, it will return error. By default, PaRAM Sets will be cleared during allocation. Note: Since this enum can change the behavior how the resources are initialized during their allocation, user is adviced to not use this command while allocating the resources. User should first change the behavior of resources' initialization and then should use start allocating resources.

EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION

To check whether PaRAM Sets will be cleared or not during allocation. If the value read is '1', it means that PaRAM Sets are getting cleared during allocation. If the value read is '0', it means that PaRAM Sets are NOT getting cleared during allocation. For e.g., unsigned short isParamClearingDone; cmdArg =

enum EDMA3_DRV_PaRAMEntry

PaRAM Set Entry type.

Use this enum to set or get any of the 8 DWords(unsigned int) within a Parameter RAM set

Enumerator:

EDMA3_DRV_PARAM_ENTRY_OPT	The OPT field (Offset Address 0x0 Bytes)
EDMA3_DRV_PARAM_ENTRY_SRC	The SRC field (Offset Address 0x4 Bytes)
EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT	The (ACNT+BCNT) field (Offset Address 0x8 Bytes)
EDMA3_DRV_PARAM_ENTRY_DST	The DST field (Offset Address 0xC Bytes)
EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX	The (SRCBIDX+DSTBIDX) field (Offset Address 0x10 Bytes)
EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD	The (LINK+BCNTRLD) field (Offset Address 0x14 Bytes)
EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX	The (SRCCIDX+DSTCIDX) field (Offset Address 0x18 Bytes)
EDMA3_DRV_PARAM_ENTRY_CCNT	The (CCNT+RSVD) field (Offset Address 0x1C Bytes)

enum EDMA3_DRV_PaRAMField

PaRAM Set Field type.

Use this enum to set or get any of the PaRAM set fields

Enumerator:

EDMA3_DRV_PARAM_FIELD_OPT	OPT field of PaRAM Set
EDMA3_DRV_PARAM_FIELD_SRCADDR	Starting byte address of Source For FIFO mode, srcAddr must be a 256-bit aligned address.
EDMA3_DRV_PARAM_FIELD_ACNT	Number of bytes in each Array (ACNT).
EDMA3_DRV_PARAM_FIELD_BCNT	Number of Arrays in each Frame (BCNT).
EDMA3_DRV_PARAM_FIELD_DESTADDR	Starting byte address of destination For FIFO mode, destAddr must be a 256-bit aligned address.
EDMA3_DRV_PARAM_FIELD_SRCBIDX	Index between consec. arrays of a Source Frame (SRCBIDX) If SAM is set to 1 (via channelOptions) then srcInterArrIndex should be an even multiple of 32 bytes.
EDMA3_DRV_PARAM_FIELD_DESTBIDX	Index between consec. arrays of a Destination Frame (DSTBIDX) If DAM is set to 1 (via channelOptions) then destInterArrIndex should be an even multiple of 32 bytes.
EDMA3_DRV_PARAM_FIELD_LINKADDR	Address for linking (AutoReloading of a PaRAM Set) This must point to a valid aligned 32-byte PaRAM set A value of 0xFFFF means no linking Linking is especially useful for use with ping-pong buffers and circular buffers.
EDMA3_DRV_PARAM_FIELD_BCNTRELOAD	Reload value of the numArrInFrame (BCNT) Relevant only for A-sync transfers.
EDMA3_DRV_PARAM_FIELD_SRCCIDX	Index between consecutive frames of a Source Block (SRCCIDX).
EDMA3_DRV_PARAM_FIELD_DESTCIDX	Index between consecutive frames of a Dest Block (DSTCIDX).
EDMA3_DRV_PARAM_FIELD_CCNT	Number of Frames in a block (CCNT).

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Function Documentation

EDMA3_DRV_Result EDMA3_DRV_checkAndClearTcc	(	EDMA3_DRV_Handle	hEdma,
		unsigned int	tccNo,
		unsigned short *	tccStatus
	)

Returns the status of a previously initiated transfer.

This is a non-blocking function that returns the status of a previously initiated transfer, based on the IPR/IPRH bit. This bit corresponds to the tccNo specified by the user. It clears the corresponding bit, if SET, while returning also.

Parameters:

	hEdma	[IN] Handle to the EDMA Driver Instance
	tccNo	[IN] TCC, specific to which the function checks the status of the IPR/IPRH bit.
	tccStatus	[IN/OUT] Status of the transfer is returned here. Returns "TRUE" if the transfer has completed (IPR/IPRH bit SET), "FALSE" if the transfer has not completed successfully (IPR/IPRH bit NOT SET).

Returns:

EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:

This function is re-entrant for different tccNo.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numTccs, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Instance::regionId.

EDMA3_DRV_Result EDMA3_DRV_getCCRegister	(	EDMA3_DRV_Handle	hEdma,
		unsigned int	regOffset,
		unsigned int *	regValue
	)

Get the Channel Controller (CC) Register value.

Parameters:

	hEdma	[IN] Handle to the EDMA Driver Instance
	regOffset	[IN] CC Register offset whose value is needed
	regValue	[IN/OUT] CC Register Value

Returns:

EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:

This function is re-entrant.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, and EDMA3_DRV_Instance::pDrvObjectHandle.

EDMA3_DRV_Handle EDMA3_DRV_getInstHandle	(	unsigned int	phyCtrllerInstId,
		EDMA3_RM_RegionId	regionId,
		EDMA3_DRV_Result *	errorCode
	)

Return the previously opened EDMA3 Driver Instance handle.

This API is used to return the previously opened EDMA3 Driver's Instance Handle (region specific), which could be used to call other EDMA3 Driver APIs. Since EDMA3 Driver does not allow multiple instances, for a single shadow region, this API is provided. This API is meant for users who DO NOT want to / could not open a new Driver Instance and hence re-use the existing Driver Instance to allocate EDMA3 resources and use various other EDMA3 Driver APIs.

In case the Driver Instance is not yet opened, NULL is returned as the function return value whereas EDMA3_DRV_E_INST_NOT_OPENED is returned in the errorCode.

Parameters:

	phyCtrllerInstId	[IN] EDMA3 Controller Instance Id (Hardware instance id, starting from 0).
	regionId	[IN] Shadow Region id for which the previously opened driver's instance handle is required.
	errorCode	[OUT] Error code while returning Driver Instance Handle.

Returns:

EDMA3_DRV_Handle : If successful, this API will return the driver's instance handle.

Note:

1) This API returns the previously opened EDMA3 Driver's Instance handle. The instance, if exists, could have been opened by some other user (most probably) or may be by the same user calling this API. If it was opened by some other user, then that user can very well close this instance anytime, without even knowing that the same instance handle is being used by other users as well. In that case, the handle becomes INVALID and user has to open a valid driver instance for his/her use.

2) This function is re-entrant.

References EDMA3_DRV_E_INST_NOT_OPENED, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::numRegions, and EDMA3_DRV_Instance::pDrvObjectHandle.

EDMA3_DRV_Result EDMA3_DRV_getMapChToEvtQ	(	EDMA3_DRV_Handle	hEdma,
		unsigned int	channelId,
		unsigned int *	mappedEvtQ
	)

Get the Event Queue mapped to the specified DMA/QDMA channel.

Parameters:

	hEdma	[IN] Handle to the EDMA Driver Instance
	channelId	[IN] Logical Channel whose associated Event Queue is needed
	mappedEvtQ	[IN/OUT] The Event Queue which is mapped to the DMA/QDMA channel

Returns:

EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:

This function is re-entrant.

References EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_DMAQNUM_CLR_MASK, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_QDMAQNUM_CLR_MASK, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, and EDMA3_DRV_Instance::pDrvObjectHandle.

EDMA3_DRV_Result EDMA3_DRV_getPaRAM	(	EDMA3_DRV_Handle	hEdma,
		unsigned int	lCh,
		EDMA3_DRV_PaRAMRegs *	currPaRAM
	)

Retrieve existing PaRAM set associated with specified logical channel (DMA/QDMA/Link).

Parameters:

	hEdma	[IN] Handle to the EDMA Instance object
	lCh	[IN] Logical Channel whose PaRAM set is requested
	currPaRAM	[IN/OUT] User gets the existing PaRAM here

Returns:

EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:

This function is re-entrant.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

EDMA3_DRV_Result EDMA3_DRV_getPaRAMEntry	(	EDMA3_DRV_Handle	hEdma,
		unsigned int	lCh,
		EDMA3_DRV_PaRAMEntry	paRAMEntry,
		unsigned int *	paRAMEntryVal
	)

Get a particular PaRAM set entry of the specified PaRAM set.

Parameters:

	hEdma	[IN] Handle to the EDMA Driver Instance
	lCh	[IN] Logical Channel bound to the Parameter RAM set whose specified field value is needed
	paRAMEntry	[IN] Specify the PaRAM set entry which needs to be obtained
	paRAMEntryVal	[IN/OUT] The value of the field is returned here

Returns:

EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:

This function is re-entrant.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_PARAM_ENTRY_CCNT, EDMA3_DRV_PARAM_ENTRY_OPT, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

EDMA3_DRV_Result EDMA3_DRV_getPaRAMField	(	EDMA3_DRV_Handle	hEdma,
		unsigned int	lCh,
		EDMA3_DRV_PaRAMField	paRAMField,
		unsigned int *	currPaRAMFieldVal
	)

Get a particular PaRAM set field of the specified PaRAM set.

Parameters:

	hEdma	[IN] Handle to the EDMA Driver Instance
	lCh	[IN] Logical Channel bound to the PaRAM set whose specified field value is needed
	paRAMField	[IN] Specify the PaRAM set field which needs to be obtained
	currPaRAMFieldVal	[IN/OUT] The value of the field is returned here

Returns:

EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:

This function is re-entrant.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT, EDMA3_DRV_PARAM_ENTRY_CCNT, EDMA3_DRV_PARAM_ENTRY_DST, EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD, EDMA3_DRV_PARAM_ENTRY_OPT, EDMA3_DRV_PARAM_ENTRY_SRC, EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX, EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX, EDMA3_DRV_PARAM_FIELD_ACNT, EDMA3_DRV_PARAM_FIELD_BCNT, EDMA3_DRV_PARAM_FIELD_BCNTRELOAD, EDMA3_DRV_PARAM_FIELD_CCNT, EDMA3_DRV_PARAM_FIELD_DESTADDR, EDMA3_DRV_PARAM_FIELD_DESTBIDX, EDMA3_DRV_PARAM_FIELD_DESTCIDX, EDMA3_DRV_PARAM_FIELD_LINKADDR, EDMA3_DRV_PARAM_FIELD_OPT, EDMA3_DRV_PARAM_FIELD_SRCADDR, EDMA3_DRV_PARAM_FIELD_SRCBIDX, EDMA3_DRV_PARAM_FIELD_SRCCIDX, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

EDMA3_DRV_Result EDMA3_DRV_getPaRAMPhyAddr	(	EDMA3_DRV_Handle	hEdma,
		unsigned int	lCh,
		unsigned int *	paramPhyAddr
	)

Get the PaRAM Set Physical Address associated with a logical channel.

This function returns the PaRAM Set Phy Address (unsigned 32 bits). The returned address could be used by the advanced users to program the PaRAM Set directly without using any APIs.

Least significant 16 bits of this address could be used to program the LINK field in the PaRAM Set. Users which program the LINK field directly SHOULD use this API to get the associated PaRAM Set address with the LINK channel.

Parameters:

	hEdma	[IN] Handle to the EDMA Driver Instance
	lCh	[IN] Logical Channel for which the PaRAM set physical address is required
	paramPhyAddr	[IN/OUT] PaRAM Set physical address is returned here.

Returns:

EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:

This function is re-entrant.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

EDMA3_DRV_Result EDMA3_DRV_Ioctl	(	EDMA3_DRV_Handle	hEdma,
		EDMA3_DRV_IoctlCmd	cmd,
		void *	cmdArg,
		void *	param
	)

EDMA3 Driver IOCTL.

This function provides IOCTL functionality for EDMA3 Driver.

Parameters:

	hEdma	[IN] Handle to the EDMA Driver Instance
	cmd	[IN] IOCTL command to be performed
	cmdArg	[IN/OUT] IOCTL command argument (if any)
	param	[IN/OUT] Device/Cmd specific argument

Returns:

EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:

For 'EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION', this function is re-entrant. For 'EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION', this function is re-entrant for different EDMA3 Driver Instances (handles).

This function provides IOCTL functionality for EDMA3 Driver.

Parameters:

	hEdma	[IN] Handle to the EDMA Driver Instance
	cmd	[IN] IOCTL command to be performed
	cmdArg	[IN/OUT] IOCTL command argument (if any)
	param	[IN/OUT] Device/Cmd specific argument

Returns:

EDMA3_DRV_SOK or EDMA3_DRV Error Code

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION, EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION, and EDMA3_DRV_Instance::resMgrInstance.

EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ	(	EDMA3_DRV_Handle	hEdma,
		unsigned int	channelId,
		EDMA3_RM_EventQueue	eventQ
	)

Associate Channel to Event Queue.

Parameters:

	hEdma	[IN] Handle to the EDMA Driver Instance
	channelId	[IN] Logical Channel to which the Event Queue is to be mapped
	eventQ	[IN] The Event Queue which is to be mapped to the DMA channel

Returns:

EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:

There should not be any data transfer going on while setting the mapping. Results could be unpredictable.

This function disables the global interrupts while modifying the global CC Registers, to make it re-entrant.

References EDMA3_DRV_DMA_CH_MAX_VAL, EDMA3_DRV_DMAQNUM_CLR_MASK, EDMA3_DRV_DMAQNUM_SET_MASK, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_QDMAQNUM_CLR_MASK, EDMA3_DRV_QDMAQNUM_SET_MASK, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numEvtQueue, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

EDMA3_DRV_Result EDMA3_DRV_setCCRegister	(	EDMA3_DRV_Handle	hEdma,
		unsigned int	regOffset,
		unsigned int	newRegValue
	)

Set the Channel Controller (CC) Register value.

Parameters:

	hEdma	[IN] Handle to the EDMA Driver Instance
	regOffset	[IN] CC Register offset whose value needs to be set
	newRegValue	[IN] New CC Register Value

Returns:

EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:

This function is non re-entrant for users using the same EDMA handle i.e. working on the same shadow region. Before modifying a register, it tries to acquire a semaphore (Driver instance specific), to protect simultaneous modification of the same register by two different users. After the successful change, it releases the semaphore. For users working on different shadow regions, thus different EDMA handles, this function is re-entrant.

Take the instance specific semaphore, to prevent simultaneous access to the shared resources.

References EDMA3_DRV_Instance::drvSemHandle, EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, and EDMA3_DRV_Instance::pDrvObjectHandle.

EDMA3_DRV_Result EDMA3_DRV_setEvtQPriority	(	EDMA3_DRV_Handle	hEdma,
		const EDMA3_DRV_EvtQuePriority *	evtQPriObj
	)

Sets EDMA TC priority.

User can program the priority of the Event Queues at a system-wide level. This means that the user can set the priority of an IO initiated by either of the TCs (Transfer Ctrllers) relative to IO initiated by the other bus masters on the device (ARM, DSP, USB, etc)

Parameters:

	hEdma	[IN] Handle to the EDMA Driver Instance
	evtQPriObj	[IN] Priority of the Event Queues

Returns:

EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:

This function disables the global interrupts while modifying the global CC Registers, to make it re-entrant.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_QPRIORITY_MAX_VAL, EDMA3_DRV_EvtQuePriority::evtQPri, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

EDMA3_DRV_Result EDMA3_DRV_setPaRAM	(	EDMA3_DRV_Handle	hEdma,
		unsigned int	lCh,
		const EDMA3_DRV_PaRAMRegs *	newPaRAM
	)

Copy the user specified PaRAM Set onto the PaRAM Set associated with the logical channel (DMA/QDMA/Link).

This API takes a PaRAM Set as input and copies it onto the actual PaRAM Set associated with the logical channel. OPT field of the PaRAM Set is written first and the CCNT field is written last.

Caution: It should be used carefully when programming the QDMA channels whose trigger words are not CCNT field.

Parameters:

	hEdma	[IN] Handle to the EDMA Instance object
	lCh	[IN] Logical Channel for which new PaRAM set is specified
	newPaRAM	[IN] Parameter RAM set to be copied onto existing PaRAM

Returns:

EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:

This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

EDMA3_DRV_Result EDMA3_DRV_setPaRAMEntry	(	EDMA3_DRV_Handle	hEdma,
		unsigned int	lCh,
		EDMA3_DRV_PaRAMEntry	paRAMEntry,
		unsigned int	newPaRAMEntryVal
	)

Set a particular PaRAM set entry of the specified PaRAM set.

Parameters:

	hEdma	[IN] Handle to the EDMA Driver Instance
	lCh	[IN] Logical Channel bound to the Parameter RAM set whose specified field needs to be set
	paRAMEntry	[IN] Specify the PaRAM set entry which needs to be set
	newPaRAMEntryVal	[IN] The new field setting

Returns:

EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:

This API should be used while setting the PaRAM set entry for QDMA channels. If EDMA3_DRV_setPaRAMField () used, it will trigger the QDMA channel before complete PaRAM set entry is written. For DMA channels, no such constraint is there.

This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_PARAM_ENTRY_CCNT, EDMA3_DRV_PARAM_ENTRY_OPT, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

EDMA3_DRV_Result EDMA3_DRV_setPaRAMField	(	EDMA3_DRV_Handle	hEdma,
		unsigned int	lCh,
		EDMA3_DRV_PaRAMField	paRAMField,
		unsigned int	newPaRAMFieldVal
	)

Set a particular PaRAM set field of the specified PaRAM set.

Parameters:

	hEdma	[IN] Handle to the EDMA Driver Instance
	lCh	[IN] Logical Channel bound to the PaRAM set whose specified field needs to be set
	paRAMField	[IN] Specify the PaRAM set field which needs to be set
	newPaRAMFieldVal	[IN] The new field setting

Returns:

EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:

This API CANNOT be used while setting the PaRAM set field for QDMA channels. It can trigger the QDMA channel before complete PaRAM set ENTRY (4-bytes field) is written (for eg, as soon one sets the ACNT field for QDMA channel, transfer is started, before one modifies the BCNT field). For DMA channels, no such constraint is there.

This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_LOG_CH_MAX_VAL, EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT, EDMA3_DRV_PARAM_ENTRY_CCNT, EDMA3_DRV_PARAM_ENTRY_DST, EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD, EDMA3_DRV_PARAM_ENTRY_OPT, EDMA3_DRV_PARAM_ENTRY_SRC, EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX, EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX, EDMA3_DRV_PARAM_FIELD_ACNT, EDMA3_DRV_PARAM_FIELD_BCNT, EDMA3_DRV_PARAM_FIELD_BCNTRELOAD, EDMA3_DRV_PARAM_FIELD_CCNT, EDMA3_DRV_PARAM_FIELD_DESTADDR, EDMA3_DRV_PARAM_FIELD_DESTBIDX, EDMA3_DRV_PARAM_FIELD_DESTCIDX, EDMA3_DRV_PARAM_FIELD_LINKADDR, EDMA3_DRV_PARAM_FIELD_OPT, EDMA3_DRV_PARAM_FIELD_SRCADDR, EDMA3_DRV_PARAM_FIELD_SRCBIDX, EDMA3_DRV_PARAM_FIELD_SRCCIDX, EDMA3_DRV_QDMA_CHANNEL_0, EDMA3_DRV_QDMA_CHANNEL_7, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numPaRAMSets, EDMA3_DRV_ChBoundResources::paRAMId, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Object::phyCtrllerInstId.

EDMA3_DRV_Result EDMA3_DRV_setQdmaTrigWord	(	EDMA3_DRV_Handle	hEdma,
		unsigned int	lCh,
		EDMA3_RM_QdmaTrigWord	trigWord
	)

Assign a Trigger Word to the specified QDMA channel.

This API sets the Trigger word for the specific QDMA channel in the QCHMAP Register. Default QDMA trigger word is CCNT.

Parameters:

	hEdma	[IN] Handle to the EDMA Instance object
	lCh	[IN] QDMA Channel which needs to be assigned the Trigger Word
	trigWord	[IN] The Trigger Word for the QDMA channel. Trigger Word is the word in the PaRAM Register Set which, when written to by CPU, will start the QDMA transfer automatically.

Returns:

EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:

This function is re-entrant for unique lCh values. It is non- re-entrant for same lCh value.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_QCH_TRWORD_CLR_MASK, EDMA3_DRV_QCH_TRWORD_SET_MASK, EDMA3_DRV_QDMA_CH_MAX_VAL, EDMA3_DRV_QDMA_CH_MIN_VAL, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, and EDMA3_DRV_Instance::pDrvObjectHandle.

EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc	(	EDMA3_DRV_Handle	hEdma,
		unsigned int	tccNo
	)

Wait for a transfer completion interrupt to occur and clear it.

This is a blocking function that returns when the IPR/IPRH bit corresponding to the tccNo specified, is SET. It clears the corresponding bit while returning also.

This function waits for the specific bit indefinitely in a tight loop, with out any delay in between. USE IT CAUTIOUSLY.

Parameters:

	hEdma	[IN] Handle to the EDMA Driver Instance
	tccNo	[IN] TCC, specific to which the function waits on a IPR/IPRH bit.

Returns:

EDMA3_DRV_SOK or EDMA3_DRV Error Code

Note:

This function is re-entrant for different tccNo.

Bit found SET, transfer is completed, clear the pending interrupt and return.

Bit found SET, transfer is completed, clear the pending interrupt and return.

References EDMA3_DRV_E_INVALID_PARAM, EDMA3_DRV_Object::gblCfgParams, EDMA3_DRV_GblConfigParams::globalRegs, EDMA3_DRV_GblConfigParams::numTccs, EDMA3_DRV_Instance::pDrvObjectHandle, and EDMA3_DRV_Instance::regionId.