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00039 #ifndef _EDMA3_H_
00040 #define _EDMA3_H_
00041
00042
00044 #include <ti/sdo/edma3/drv/edma3_drv.h>
00045
00046
00047 #include <ti/sdo/edma3/rm/src/edma3_rl_cc.h>
00048
00049 #ifdef __cplusplus
00050 extern "C" {
00051 #endif
00052
00053
00062
00065 #define EDMA3_DRV_OPT_SAM_CLR_MASK (~EDMA3_CCRL_OPT_SAM_MASK)
00066
00067 #define EDMA3_DRV_OPT_SAM_SET_MASK(mode) (((EDMA3_CCRL_OPT_SAM_MASK >> EDMA3_CCRL_OPT_SAM_SHIFT) & (mode)) << EDMA3_CCRL_OPT_SAM_SHIFT)
00068
00070 #define EDMA3_DRV_OPT_DAM_CLR_MASK (~EDMA3_CCRL_OPT_DAM_MASK)
00071
00072 #define EDMA3_DRV_OPT_DAM_SET_MASK(mode) (((EDMA3_CCRL_OPT_DAM_MASK >> EDMA3_CCRL_OPT_DAM_SHIFT) & (mode)) << EDMA3_CCRL_OPT_DAM_SHIFT)
00073
00075 #define EDMA3_DRV_OPT_SYNCDIM_CLR_MASK (~EDMA3_CCRL_OPT_SYNCDIM_MASK)
00076
00077 #define EDMA3_DRV_OPT_SYNCDIM_SET_MASK(synctype) (((EDMA3_CCRL_OPT_SYNCDIM_MASK >> EDMA3_CCRL_OPT_SYNCDIM_SHIFT) & (synctype)) << EDMA3_CCRL_OPT_SYNCDIM_SHIFT)
00078
00080 #define EDMA3_DRV_OPT_STATIC_CLR_MASK (~EDMA3_CCRL_OPT_STATIC_MASK)
00081
00082 #define EDMA3_DRV_OPT_STATIC_SET_MASK(en) (((EDMA3_CCRL_OPT_STATIC_MASK >> EDMA3_CCRL_OPT_STATIC_SHIFT) & (en)) << EDMA3_CCRL_OPT_STATIC_SHIFT)
00083
00085 #define EDMA3_DRV_OPT_FWID_CLR_MASK (~EDMA3_CCRL_OPT_FWID_MASK)
00086
00087 #define EDMA3_DRV_OPT_FWID_SET_MASK(width) (((EDMA3_CCRL_OPT_FWID_MASK >> EDMA3_CCRL_OPT_FWID_SHIFT) & (width)) << EDMA3_CCRL_OPT_FWID_SHIFT)
00088
00090 #define EDMA3_DRV_OPT_TCCMODE_CLR_MASK (~EDMA3_CCRL_OPT_TCCMODE_MASK)
00091
00092 #define EDMA3_DRV_OPT_TCCMODE_SET_MASK(early) (((EDMA3_CCRL_OPT_TCCMODE_MASK >> EDMA3_CCRL_OPT_TCCMODE_SHIFT) & (early)) << EDMA3_CCRL_OPT_TCCMODE_SHIFT)
00093
00095 #define EDMA3_DRV_OPT_TCC_CLR_MASK (~EDMA3_CCRL_OPT_TCC_MASK)
00096
00097 #define EDMA3_DRV_OPT_TCC_SET_MASK(tcc) (((EDMA3_CCRL_OPT_TCC_MASK >> EDMA3_CCRL_OPT_TCC_SHIFT) & (tcc)) << EDMA3_CCRL_OPT_TCC_SHIFT)
00098
00100 #define EDMA3_DRV_OPT_TCINTEN_CLR_MASK (~EDMA3_CCRL_OPT_TCINTEN_MASK)
00101
00102 #define EDMA3_DRV_OPT_TCINTEN_SET_MASK(tcinten) (((EDMA3_CCRL_OPT_TCINTEN_MASK >> EDMA3_CCRL_OPT_TCINTEN_SHIFT) & (tcinten)) << EDMA3_CCRL_OPT_TCINTEN_SHIFT)
00103
00105 #define EDMA3_DRV_OPT_ITCINTEN_CLR_MASK (~EDMA3_CCRL_OPT_ITCINTEN_MASK)
00106
00107 #define EDMA3_DRV_OPT_ITCINTEN_SET_MASK(itcinten) (((EDMA3_CCRL_OPT_ITCINTEN_MASK >> EDMA3_CCRL_OPT_ITCINTEN_SHIFT) & (itcinten)) << EDMA3_CCRL_OPT_ITCINTEN_SHIFT)
00108
00110 #define EDMA3_DRV_OPT_TCCHEN_CLR_MASK (~EDMA3_CCRL_OPT_TCCHEN_MASK)
00111
00112 #define EDMA3_DRV_OPT_TCCHEN_SET_MASK(tcchen) (((EDMA3_CCRL_OPT_TCCHEN_MASK >> EDMA3_CCRL_OPT_TCCHEN_SHIFT) & (tcchen)) << EDMA3_CCRL_OPT_TCCHEN_SHIFT)
00113
00115 #define EDMA3_DRV_OPT_ITCCHEN_CLR_MASK (~EDMA3_CCRL_OPT_ITCCHEN_MASK)
00116
00117 #define EDMA3_DRV_OPT_ITCCHEN_SET_MASK(itcchen) (((EDMA3_CCRL_OPT_ITCCHEN_MASK >> EDMA3_CCRL_OPT_ITCCHEN_SHIFT) & (itcchen)) << EDMA3_CCRL_OPT_ITCCHEN_SHIFT)
00118
00120 #define EDMA3_DRV_OPT_SAM_GET_MASK(mode) ((mode)&1u)
00121
00122 #define EDMA3_DRV_OPT_DAM_GET_MASK(mode) (((mode)&(1u<<1u))>>1u)
00123
00124 #define EDMA3_DRV_OPT_SYNCDIM_GET_MASK(synctype) (((synctype)&(1u<<2u))>>2u)
00125
00126 #define EDMA3_DRV_OPT_STATIC_GET_MASK(en) (((en)&(1u<<3u))>>3u)
00127
00128 #define EDMA3_DRV_OPT_FWID_GET_MASK(width) (((width)&(0x7u<<8u))>>8u)
00129
00130 #define EDMA3_DRV_OPT_TCCMODE_GET_MASK(early) (((early)&(1u<<11u))>>11u)
00131
00132 #define EDMA3_DRV_OPT_TCC_GET_MASK(tcc) (((tcc)&(0x3fu<<12u))>>12u)
00133
00134 #define EDMA3_DRV_OPT_TCINTEN_GET_MASK(tcinten) (((tcinten)&(1u<<20u))>>20u)
00135
00136 #define EDMA3_DRV_OPT_ITCINTEN_GET_MASK(itcinten) (((itcinten)&(1u<<21u))>>21u)
00137
00138 #define EDMA3_DRV_OPT_TCCHEN_GET_MASK(tcchen) (((tcchen)&(1u<<22u))>>22u)
00139
00140 #define EDMA3_DRV_OPT_ITCCHEN_GET_MASK(itcchen) (((itcchen)&(1u<<23u))>>23u)
00141
00143 #define EDMA3_DRV_DMAQNUM_CLR_MASK(chNum) (~(0x7u<<(((chNum)%8u)*4u)))
00144
00145 #define EDMA3_DRV_DMAQNUM_SET_MASK(chNum,queNum) ((0x7u & (queNum)) << (((chNum)%8u)*4u))
00146
00147 #define EDMA3_DRV_QDMAQNUM_CLR_MASK(chNum) (~(0x7u<<((chNum)*4u)))
00148
00149 #define EDMA3_DRV_QDMAQNUM_SET_MASK(chNum,queNum) ((0x7u & (queNum)) << ((chNum)*4u))
00150
00151
00152
00154 #define EDMA3_DRV_QCH_TRWORD_CLR_MASK (~EDMA3_CCRL_QCHMAP_TRWORD_MASK)
00155
00156 #define EDMA3_DRV_QCH_TRWORD_SET_MASK(paRAMId) (((EDMA3_CCRL_QCHMAP_TRWORD_MASK >> EDMA3_CCRL_QCHMAP_TRWORD_SHIFT) & (paRAMId)) << EDMA3_CCRL_QCHMAP_TRWORD_SHIFT)
00157
00158
00160 #define EDMA3_DRV_ACNT_MAX_VAL (0xFFFFu)
00161
00162 #define EDMA3_DRV_BCNT_MAX_VAL (0xFFFFu)
00163
00164 #define EDMA3_DRV_CCNT_MAX_VAL (0xFFFFu)
00165
00166 #define EDMA3_DRV_BCNTRELD_MAX_VAL (0xFFFFu)
00167
00168 #define EDMA3_DRV_SRCBIDX_MAX_VAL (0x7FFF)
00169
00170 #define EDMA3_DRV_SRCBIDX_MIN_VAL (-32768)
00171
00172 #define EDMA3_DRV_SRCCIDX_MAX_VAL (0x7FFF)
00173
00174 #define EDMA3_DRV_SRCCIDX_MIN_VAL (-32768)
00175
00176 #define EDMA3_DRV_DSTBIDX_MAX_VAL (0x7FFF)
00177
00178 #define EDMA3_DRV_DSTBIDX_MIN_VAL (-32768)
00179
00180 #define EDMA3_DRV_DSTCIDX_MAX_VAL (0x7FFF)
00181
00182 #define EDMA3_DRV_DSTCIDX_MIN_VAL (-32768)
00183
00184 #define EDMA3_DRV_QPRIORITY_MAX_VAL (7u)
00185
00186 #define EDMA3_DRV_QPRIORITY_MIN_VAL (0u)
00187
00188
00189
00190
00199 #define EDMA3_DRV_DMA_CH_MAX_VAL (EDMA3_MAX_DMA_CH - 1u)
00200
00202 #define EDMA3_DRV_LINK_CH_MIN_VAL (EDMA3_DRV_DMA_CH_MAX_VAL + 1u)
00203
00205 #define EDMA3_DRV_LINK_CH_MAX_VAL (EDMA3_DRV_LINK_CH_MIN_VAL + EDMA3_MAX_PARAM_SETS - 1u)
00206
00208 #define EDMA3_DRV_QDMA_CH_MIN_VAL (EDMA3_DRV_LINK_CH_MAX_VAL + 1u)
00209
00211 #define EDMA3_DRV_QDMA_CH_MAX_VAL (EDMA3_DRV_QDMA_CH_MIN_VAL + EDMA3_MAX_QDMA_CH - 1u)
00212
00214 #define EDMA3_DRV_LOG_CH_MAX_VAL (EDMA3_DRV_QDMA_CH_MAX_VAL)
00215
00216
00217
00218
00219
00228 typedef enum {
00230 EDMA3_DRV_DELETED = 0,
00232 EDMA3_DRV_CREATED = 1,
00234 EDMA3_DRV_OPENED = 2,
00236 EDMA3_DRV_CLOSED = 3
00237 } EDMA3_DRV_ObjState;
00238
00239
00248 typedef struct
00249 {
00251 unsigned int phyCtrllerInstId;
00252
00254 EDMA3_DRV_ObjState state;
00255
00257 unsigned int numOpens;
00258
00267 EDMA3_DRV_GblConfigParams gblCfgParams;
00268
00269 } EDMA3_DRV_Object;
00270
00271
00281 typedef struct
00282 {
00284 EDMA3_RM_RegionId regionId;
00285
00291 unsigned short isMaster;
00292
00298 EDMA3_DRV_InstanceInitConfig drvInstInitConfig;
00299
00300
00302 void *drvSemHandle;
00303
00305 EDMA3_RM_GblErrCallbackParams gblerrCbParams;
00306
00308 EDMA3_CCRL_ShadowRegs *shadowRegs;
00309
00314 EDMA3_DRV_Object *pDrvObjectHandle;
00315
00317 EDMA3_RM_Handle resMgrInstance;
00318
00319 }EDMA3_DRV_Instance;
00320
00321
00322
00323
00324
00333 typedef struct {
00335 int paRAMId;
00336
00338 unsigned int tcc;
00339
00341 EDMA3_DRV_TrigMode trigMode;
00342
00343 } EDMA3_DRV_ChBoundResources;
00344
00345
00349 typedef enum
00350 {
00352 EDMA3_DRV_CHANNEL_TYPE_NONE,
00353
00355 EDMA3_DRV_CHANNEL_TYPE_DMA = 1,
00356
00358 EDMA3_DRV_CHANNEL_TYPE_QDMA = 2,
00359
00361 EDMA3_DRV_CHANNEL_TYPE_LINK = 3
00362
00363 } EDMA3_DRV_ChannelType;
00364
00365 #ifdef __cplusplus
00366 }
00367 #endif
00368
00369
00370 #endif