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00041 #ifndef _EDMA3_DRV_H_
00042 #define _EDMA3_DRV_H_
00043
00044
00045
00046 #include <ti/sdo/edma3/rm/edma3_rm.h>
00047
00048 #ifdef __cplusplus
00049 extern "C" {
00050 #endif
00051
00061
00062
00063
00064
00403
00404
00405
00406
00407
00408
00409
00418 #define EDMA3_DRV_E_BASE (-128)
00419
00424 #define EDMA3_DRV_E_OBJ_NOT_DELETED (EDMA3_DRV_E_BASE)
00425
00430 #define EDMA3_DRV_E_OBJ_NOT_CLOSED (EDMA3_DRV_E_BASE-1)
00431
00436 #define EDMA3_DRV_E_OBJ_NOT_OPENED (EDMA3_DRV_E_BASE-2)
00437
00442 #define EDMA3_DRV_E_RM_CLOSE_FAIL (EDMA3_DRV_E_BASE-3)
00443
00445 #define EDMA3_DRV_E_DMA_CHANNEL_UNAVAIL (EDMA3_DRV_E_BASE-4)
00446
00448 #define EDMA3_DRV_E_QDMA_CHANNEL_UNAVAIL (EDMA3_DRV_E_BASE-5)
00449
00451 #define EDMA3_DRV_E_PARAM_SET_UNAVAIL (EDMA3_DRV_E_BASE-6)
00452
00454 #define EDMA3_DRV_E_TCC_UNAVAIL (EDMA3_DRV_E_BASE-7)
00455
00457 #define EDMA3_DRV_E_TCC_REGISTER_FAIL (EDMA3_DRV_E_BASE-8)
00458
00460 #define EDMA3_DRV_E_CH_PARAM_BIND_FAIL (EDMA3_DRV_E_BASE-9)
00461
00466 #define EDMA3_DRV_E_ADDRESS_NOT_ALIGNED (EDMA3_DRV_E_BASE-10)
00467
00469 #define EDMA3_DRV_E_INVALID_PARAM (EDMA3_DRV_E_BASE-11)
00470
00472 #define EDMA3_DRV_E_INVALID_STATE (EDMA3_DRV_E_BASE-12)
00473
00475 #define EDMA3_DRV_E_INST_ALREADY_EXISTS (EDMA3_DRV_E_BASE-13)
00476
00478 #define EDMA3_DRV_E_FIFO_WIDTH_NOT_SUPPORTED (EDMA3_DRV_E_BASE-14)
00479
00481 #define EDMA3_DRV_E_SEMAPHORE (EDMA3_DRV_E_BASE-15)
00482
00484 #define EDMA3_DRV_E_INST_NOT_OPENED (EDMA3_DRV_E_BASE-16)
00485
00486
00487
00488
00498 #define EDMA3_DRV_CH_NO_PARAM_MAP EDMA3_RM_CH_NO_PARAM_MAP
00499
00509 #define EDMA3_DRV_CH_NO_TCC_MAP EDMA3_RM_CH_NO_TCC_MAP
00510
00511
00512
00529 typedef struct {
00531 unsigned int numDmaChannels;
00532
00534 unsigned int numQdmaChannels;
00535
00540 unsigned int numTccs;
00541
00543 unsigned int numPaRAMSets;
00544
00546 unsigned int numEvtQueue;
00547
00551 unsigned int numTcs;
00552
00554 unsigned int numRegions;
00555
00569 unsigned short dmaChPaRAMMapExists;
00570
00572 unsigned short memProtectionExists;
00573
00575 void *globalRegs;
00576
00578 void *tcRegs[EDMA3_MAX_TC];
00579
00584 unsigned int xferCompleteInt;
00585
00587 unsigned int ccError;
00588
00590 unsigned int tcError[EDMA3_MAX_TC];
00591
00601 unsigned int evtQPri [EDMA3_MAX_EVT_QUE];
00602
00613 unsigned int evtQueueWaterMarkLvl [EDMA3_MAX_EVT_QUE];
00614
00622 unsigned int tcDefaultBurstSize[EDMA3_MAX_TC];
00623
00635 unsigned int dmaChannelPaRAMMap [EDMA3_MAX_DMA_CH];
00636
00646 unsigned int dmaChannelTccMap [EDMA3_MAX_DMA_CH];
00647
00660 unsigned int dmaChannelHwEvtMap [EDMA3_MAX_DMA_CHAN_DWRDS];
00661 } EDMA3_DRV_GblConfigParams;
00662
00663
00664
00728 typedef struct
00729 {
00731 unsigned int ownPaRAMSets[EDMA3_MAX_PARAM_DWRDS];
00732
00734 unsigned int ownDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];
00735
00737 unsigned int ownQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];
00738
00740 unsigned int ownTccs[EDMA3_MAX_TCC_DWRDS];
00741
00749 unsigned int resvdPaRAMSets[EDMA3_MAX_PARAM_DWRDS];
00750
00758 unsigned int resvdDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];
00759
00767 unsigned int resvdQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];
00768
00776 unsigned int resvdTccs[EDMA3_MAX_TCC_DWRDS];
00777 }EDMA3_DRV_InstanceInitConfig;
00778
00779
00780
00787 typedef struct
00788 {
00790 EDMA3_RM_RegionId regionId;
00791
00797 unsigned short isMaster;
00798
00807 EDMA3_DRV_InstanceInitConfig *drvInstInitConfig;
00808
00814 void *drvSemHandle;
00815
00821 EDMA3_RM_GblErrCallback gblerrCb;
00822
00827 void *gblerrData;
00828 } EDMA3_DRV_InitConfig;
00829
00830
00831
00840 typedef struct {
00847 unsigned short isSlave;
00848
00850 unsigned short param;
00851 }EDMA3_DRV_MiscParam;
00852
00853
00886 EDMA3_DRV_Result EDMA3_DRV_create (unsigned int phyCtrllerInstId,
00887 const EDMA3_DRV_GblConfigParams *gblCfgParams,
00888 const void *miscParam);
00889
00890
00911 EDMA3_DRV_Result EDMA3_DRV_delete (unsigned int phyCtrllerInstId,
00912 const void *param);
00913
00914
00915
00952 EDMA3_DRV_Handle EDMA3_DRV_open (unsigned int phyCtrllerInstId,
00953 const EDMA3_DRV_InitConfig *initCfg,
00954 EDMA3_DRV_Result *errorCode);
00955
00956
00973 EDMA3_DRV_Result EDMA3_DRV_close (EDMA3_DRV_Handle hEdma,
00974 const void *param);
00975
00976
00977
00986
00987
00994 #define EDMA3_DRV_DMA_CHANNEL_ANY 1002u
00995
01002 #define EDMA3_DRV_QDMA_CHANNEL_ANY 1003u
01003
01011 #define EDMA3_DRV_TCC_ANY 1004u
01012
01019 #define EDMA3_DRV_LINK_CHANNEL 1005u
01020
01021
01022
01041 typedef enum
01042 {
01044 EDMA3_DRV_HW_CHANNEL_EVENT_0 = 0,
01046 EDMA3_DRV_HW_CHANNEL_EVENT_1,
01048 EDMA3_DRV_HW_CHANNEL_EVENT_2,
01050 EDMA3_DRV_HW_CHANNEL_EVENT_3,
01052 EDMA3_DRV_HW_CHANNEL_EVENT_4,
01054 EDMA3_DRV_HW_CHANNEL_EVENT_5,
01056 EDMA3_DRV_HW_CHANNEL_EVENT_6,
01058 EDMA3_DRV_HW_CHANNEL_EVENT_7,
01060 EDMA3_DRV_HW_CHANNEL_EVENT_8,
01062 EDMA3_DRV_HW_CHANNEL_EVENT_9,
01064 EDMA3_DRV_HW_CHANNEL_EVENT_10,
01066 EDMA3_DRV_HW_CHANNEL_EVENT_11,
01068 EDMA3_DRV_HW_CHANNEL_EVENT_12,
01070 EDMA3_DRV_HW_CHANNEL_EVENT_13,
01072 EDMA3_DRV_HW_CHANNEL_EVENT_14,
01074 EDMA3_DRV_HW_CHANNEL_EVENT_15,
01076 EDMA3_DRV_HW_CHANNEL_EVENT_16,
01078 EDMA3_DRV_HW_CHANNEL_EVENT_17,
01080 EDMA3_DRV_HW_CHANNEL_EVENT_18,
01082 EDMA3_DRV_HW_CHANNEL_EVENT_19,
01084 EDMA3_DRV_HW_CHANNEL_EVENT_20,
01086 EDMA3_DRV_HW_CHANNEL_EVENT_21,
01088 EDMA3_DRV_HW_CHANNEL_EVENT_22,
01090 EDMA3_DRV_HW_CHANNEL_EVENT_23,
01092 EDMA3_DRV_HW_CHANNEL_EVENT_24,
01094 EDMA3_DRV_HW_CHANNEL_EVENT_25,
01096 EDMA3_DRV_HW_CHANNEL_EVENT_26,
01098 EDMA3_DRV_HW_CHANNEL_EVENT_27,
01100 EDMA3_DRV_HW_CHANNEL_EVENT_28,
01102 EDMA3_DRV_HW_CHANNEL_EVENT_29,
01104 EDMA3_DRV_HW_CHANNEL_EVENT_30,
01106 EDMA3_DRV_HW_CHANNEL_EVENT_31,
01108 EDMA3_DRV_HW_CHANNEL_EVENT_32,
01110 EDMA3_DRV_HW_CHANNEL_EVENT_33,
01112 EDMA3_DRV_HW_CHANNEL_EVENT_34,
01114 EDMA3_DRV_HW_CHANNEL_EVENT_35,
01116 EDMA3_DRV_HW_CHANNEL_EVENT_36,
01118 EDMA3_DRV_HW_CHANNEL_EVENT_37,
01120 EDMA3_DRV_HW_CHANNEL_EVENT_38,
01122 EDMA3_DRV_HW_CHANNEL_EVENT_39,
01124 EDMA3_DRV_HW_CHANNEL_EVENT_40,
01126 EDMA3_DRV_HW_CHANNEL_EVENT_41,
01128 EDMA3_DRV_HW_CHANNEL_EVENT_42,
01130 EDMA3_DRV_HW_CHANNEL_EVENT_43,
01132 EDMA3_DRV_HW_CHANNEL_EVENT_44,
01134 EDMA3_DRV_HW_CHANNEL_EVENT_45,
01136 EDMA3_DRV_HW_CHANNEL_EVENT_46,
01138 EDMA3_DRV_HW_CHANNEL_EVENT_47,
01140 EDMA3_DRV_HW_CHANNEL_EVENT_48,
01142 EDMA3_DRV_HW_CHANNEL_EVENT_49,
01144 EDMA3_DRV_HW_CHANNEL_EVENT_50,
01146 EDMA3_DRV_HW_CHANNEL_EVENT_51,
01148 EDMA3_DRV_HW_CHANNEL_EVENT_52,
01150 EDMA3_DRV_HW_CHANNEL_EVENT_53,
01152 EDMA3_DRV_HW_CHANNEL_EVENT_54,
01154 EDMA3_DRV_HW_CHANNEL_EVENT_55,
01156 EDMA3_DRV_HW_CHANNEL_EVENT_56,
01158 EDMA3_DRV_HW_CHANNEL_EVENT_57,
01160 EDMA3_DRV_HW_CHANNEL_EVENT_58,
01162 EDMA3_DRV_HW_CHANNEL_EVENT_59,
01164 EDMA3_DRV_HW_CHANNEL_EVENT_60,
01166 EDMA3_DRV_HW_CHANNEL_EVENT_61,
01168 EDMA3_DRV_HW_CHANNEL_EVENT_62,
01170 EDMA3_DRV_HW_CHANNEL_EVENT_63
01171 } EDMA3_DRV_HW_CHANNEL_EVENT;
01172
01173
01179 #define EDMA3_DRV_QDMA_CHANNEL_0 (EDMA3_MAX_DMA_CH + EDMA3_MAX_PARAM_SETS)
01180
01181 #define EDMA3_DRV_QDMA_CHANNEL_1 (EDMA3_DRV_QDMA_CHANNEL_0+1u)
01182
01183 #define EDMA3_DRV_QDMA_CHANNEL_2 (EDMA3_DRV_QDMA_CHANNEL_0+2u)
01184
01185 #define EDMA3_DRV_QDMA_CHANNEL_3 (EDMA3_DRV_QDMA_CHANNEL_0+3u)
01186
01187 #define EDMA3_DRV_QDMA_CHANNEL_4 (EDMA3_DRV_QDMA_CHANNEL_0+4u)
01188
01189 #define EDMA3_DRV_QDMA_CHANNEL_5 (EDMA3_DRV_QDMA_CHANNEL_0+5u)
01190
01191 #define EDMA3_DRV_QDMA_CHANNEL_6 (EDMA3_DRV_QDMA_CHANNEL_0+6u)
01192
01193 #define EDMA3_DRV_QDMA_CHANNEL_7 (EDMA3_DRV_QDMA_CHANNEL_0+7u)
01194
01195
01196
01316 EDMA3_DRV_Result EDMA3_DRV_requestChannel (EDMA3_DRV_Handle hEdma,
01317 unsigned int *pLCh,
01318 unsigned int *pTcc,
01319 EDMA3_RM_EventQueue evtQueue,
01320 EDMA3_RM_TccCallback tccCb,
01321 void *cbData);
01322
01323
01352 EDMA3_DRV_Result EDMA3_DRV_freeChannel (EDMA3_DRV_Handle hEdma,
01353 unsigned int channelId);
01354
01355
01356
01372 EDMA3_DRV_Result EDMA3_DRV_clearErrorBits (EDMA3_DRV_Handle hEdma,
01373 unsigned int channelId);
01374
01375
01410 EDMA3_DRV_Result EDMA3_DRV_linkChannel ( EDMA3_DRV_Handle hEdma,
01411 unsigned int lCh1,
01412 unsigned int lCh2);
01413
01414
01415
01431 EDMA3_DRV_Result EDMA3_DRV_unlinkChannel (EDMA3_DRV_Handle hEdma,
01432 unsigned int lCh);
01433
01434
01435
01436
01437
01452 typedef enum
01453 {
01458 EDMA3_DRV_OPT_FIELD_SAM = 0,
01459
01464 EDMA3_DRV_OPT_FIELD_DAM = 1,
01465
01470 EDMA3_DRV_OPT_FIELD_SYNCDIM = 2,
01471
01477 EDMA3_DRV_OPT_FIELD_STATIC = 3,
01478
01483 EDMA3_DRV_OPT_FIELD_FWID = 4,
01484
01491 EDMA3_DRV_OPT_FIELD_TCCMODE = 5,
01492
01500 EDMA3_DRV_OPT_FIELD_TCC = 6,
01501
01506 EDMA3_DRV_OPT_FIELD_TCINTEN = 7,
01507
01512 EDMA3_DRV_OPT_FIELD_ITCINTEN = 8,
01513
01518 EDMA3_DRV_OPT_FIELD_TCCHEN = 9,
01519
01524 EDMA3_DRV_OPT_FIELD_ITCCHEN = 10
01525
01526 } EDMA3_DRV_OptField;
01527
01528
01540 typedef enum
01541 {
01546 EDMA3_DRV_ADDR_MODE_INCR = 0,
01547
01552 EDMA3_DRV_ADDR_MODE_FIFO = 1
01553
01554 } EDMA3_DRV_AddrMode;
01555
01556
01557
01584 typedef enum
01585 {
01590 EDMA3_DRV_SYNC_A = 0 ,
01591
01596 EDMA3_DRV_SYNC_AB = 1
01597
01598 } EDMA3_DRV_SyncType;
01599
01600
01601
01606 typedef enum
01607 {
01614 EDMA3_DRV_STATIC_DIS = 0,
01615
01622 EDMA3_DRV_STATIC_EN = 1
01623 } EDMA3_DRV_StaticMode;
01624
01625
01634 typedef enum
01635 {
01637 EDMA3_DRV_W8BIT = 0,
01638
01640 EDMA3_DRV_W16BIT = 1,
01641
01643 EDMA3_DRV_W32BIT = 2,
01644
01646 EDMA3_DRV_W64BIT = 3,
01647
01649 EDMA3_DRV_W128BIT = 4,
01650
01652 EDMA3_DRV_W256BIT = 5
01653
01654 } EDMA3_DRV_FifoWidth;
01655
01656
01657
01658
01664 typedef enum
01665 {
01667 EDMA3_DRV_TCCMODE_NORMAL = 0,
01668
01674 EDMA3_DRV_TCCMODE_EARLY = 1
01675 } EDMA3_DRV_TccMode;
01676
01677
01681 typedef enum
01682 {
01684 EDMA3_DRV_TCINTEN_DIS = 0,
01685
01694 EDMA3_DRV_TCINTEN_EN = 1
01695 } EDMA3_DRV_TcintEn;
01696
01697
01701 typedef enum
01702 {
01704 EDMA3_DRV_ITCINTEN_DIS = 0,
01705
01715 EDMA3_DRV_ITCINTEN_EN = 1
01716 } EDMA3_DRV_ItcintEn;
01717
01718
01722 typedef enum
01723 {
01725 EDMA3_DRV_TCCHEN_DIS = 0,
01726
01734 EDMA3_DRV_TCCHEN_EN = 1
01735 } EDMA3_DRV_TcchEn;
01736
01737
01741 typedef enum
01742 {
01744 EDMA3_DRV_ITCCHEN_DIS = 0,
01745
01753 EDMA3_DRV_ITCCHEN_EN = 1
01754 } EDMA3_DRV_ItcchEn;
01755
01756
01761 typedef struct
01762 {
01764 EDMA3_DRV_TcchEn tcchEn;
01765
01767 EDMA3_DRV_ItcchEn itcchEn;
01768
01770 EDMA3_DRV_TcintEn tcintEn;
01771
01773 EDMA3_DRV_ItcintEn itcintEn;
01774 } EDMA3_DRV_ChainOptions;
01775
01776
01777
01798 EDMA3_DRV_Result EDMA3_DRV_setOptField (EDMA3_DRV_Handle hEdma,
01799 unsigned int lCh,
01800 EDMA3_DRV_OptField optField,
01801 unsigned int newOptFieldVal);
01802
01803
01823 EDMA3_DRV_Result EDMA3_DRV_getOptField (EDMA3_DRV_Handle hEdma,
01824 unsigned int lCh,
01825 EDMA3_DRV_OptField optField,
01826 unsigned int *optFieldVal);
01827
01828
01855 EDMA3_DRV_Result EDMA3_DRV_setSrcParams ( EDMA3_DRV_Handle hEdma,
01856 unsigned int lCh,
01857 unsigned int srcAddr,
01858 EDMA3_DRV_AddrMode addrMode,
01859 EDMA3_DRV_FifoWidth fifoWidth);
01860
01861
01862
01889 EDMA3_DRV_Result EDMA3_DRV_setDestParams ( EDMA3_DRV_Handle hEdma,
01890 unsigned int lCh,
01891 unsigned int destAddr,
01892 EDMA3_DRV_AddrMode addrMode,
01893 EDMA3_DRV_FifoWidth fifoWidth );
01894
01895
01896
01929 EDMA3_DRV_Result EDMA3_DRV_setSrcIndex ( EDMA3_DRV_Handle hEdma,
01930 unsigned int lCh,
01931 int srcBIdx,
01932 int srcCIdx );
01933
01934
01935
01968 EDMA3_DRV_Result EDMA3_DRV_setDestIndex (EDMA3_DRV_Handle hEdma,
01969 unsigned int lCh,
01970 int destBIdx,
01971 int destCIdx);
01972
01973
02034 EDMA3_DRV_Result EDMA3_DRV_setTransferParams (
02035 EDMA3_DRV_Handle hEdma,
02036 unsigned int lCh,
02037 unsigned int aCnt,
02038 unsigned int bCnt,
02039 unsigned int cCnt,
02040 unsigned int bCntReload,
02041 EDMA3_DRV_SyncType syncType);
02042
02043
02070 EDMA3_DRV_Result EDMA3_DRV_chainChannel (EDMA3_DRV_Handle hEdma,
02071 unsigned int lCh1,
02072 unsigned int lCh2,
02073 const EDMA3_DRV_ChainOptions *chainOptions);
02074
02075
02088 EDMA3_DRV_Result EDMA3_DRV_unchainChannel (EDMA3_DRV_Handle hEdma,
02089 unsigned int lCh);
02090
02091
02098 typedef enum
02099 {
02105 EDMA3_DRV_TRIG_MODE_MANUAL = 0,
02106
02115 EDMA3_DRV_TRIG_MODE_QDMA = 1,
02116
02122 EDMA3_DRV_TRIG_MODE_EVENT = 2,
02123
02125 EDMA3_DRV_TRIG_MODE_NONE = 3
02126 } EDMA3_DRV_TrigMode;
02127
02128
02160 EDMA3_DRV_Result EDMA3_DRV_enableTransfer (EDMA3_DRV_Handle hEdma,
02161 unsigned int lCh,
02162 EDMA3_DRV_TrigMode trigMode);
02163
02164
02192 EDMA3_DRV_Result EDMA3_DRV_disableTransfer (EDMA3_DRV_Handle hEdma,
02193 unsigned int lCh,
02194 EDMA3_DRV_TrigMode trigMode);
02195
02216 EDMA3_DRV_Result EDMA3_DRV_disableLogicalChannel (EDMA3_DRV_Handle hEdma,
02217 unsigned int lCh,
02218 EDMA3_DRV_TrigMode trigMode);
02219
02220
02221
02222
02223
02224
02239 typedef enum
02240 {
02244 EDMA3_DRV_PARAM_ENTRY_OPT = 0,
02245
02249 EDMA3_DRV_PARAM_ENTRY_SRC = 1,
02250
02254 EDMA3_DRV_PARAM_ENTRY_ACNT_BCNT = 2,
02255
02259 EDMA3_DRV_PARAM_ENTRY_DST = 3,
02260
02264 EDMA3_DRV_PARAM_ENTRY_SRC_DST_BIDX = 4,
02265
02269 EDMA3_DRV_PARAM_ENTRY_LINK_BCNTRLD = 5,
02270
02274 EDMA3_DRV_PARAM_ENTRY_SRC_DST_CIDX = 6,
02275
02279 EDMA3_DRV_PARAM_ENTRY_CCNT = 7
02280
02281 } EDMA3_DRV_PaRAMEntry;
02282
02283
02289 typedef enum
02290 {
02292 EDMA3_DRV_PARAM_FIELD_OPT = 0,
02293
02298 EDMA3_DRV_PARAM_FIELD_SRCADDR = 1,
02299
02303 EDMA3_DRV_PARAM_FIELD_ACNT = 2,
02304
02308 EDMA3_DRV_PARAM_FIELD_BCNT = 3,
02309
02314 EDMA3_DRV_PARAM_FIELD_DESTADDR = 4,
02315
02321 EDMA3_DRV_PARAM_FIELD_SRCBIDX = 5,
02322
02328 EDMA3_DRV_PARAM_FIELD_DESTBIDX = 6,
02329
02337 EDMA3_DRV_PARAM_FIELD_LINKADDR = 7,
02338
02343 EDMA3_DRV_PARAM_FIELD_BCNTRELOAD = 8,
02344
02348 EDMA3_DRV_PARAM_FIELD_SRCCIDX = 9,
02349
02353 EDMA3_DRV_PARAM_FIELD_DESTCIDX = 10,
02354
02358 EDMA3_DRV_PARAM_FIELD_CCNT = 11
02359
02360 } EDMA3_DRV_PaRAMField;
02361
02362
02363
02370 typedef struct {
02372 volatile unsigned int OPT;
02373
02378 volatile unsigned int SRC;
02379
02384 volatile unsigned int A_B_CNT;
02385
02391 volatile unsigned int DST;
02392
02403 volatile unsigned int SRC_DST_BIDX;
02404
02414 volatile unsigned int LINK_BCNTRLD;
02415
02421 volatile unsigned int SRC_DST_CIDX;
02422
02426 volatile unsigned int CCNT;
02427
02428 } EDMA3_DRV_ParamentryRegs;
02429
02430
02431
02438 typedef struct {
02440 volatile unsigned int opt;
02441
02446 volatile unsigned int srcAddr;
02447
02451 volatile unsigned short aCnt;
02452
02456 volatile unsigned short bCnt;
02457
02463 volatile unsigned int destAddr;
02464
02470 volatile short srcBIdx;
02471
02477 volatile short destBIdx;
02478
02486 volatile unsigned short linkAddr;
02487
02492 volatile unsigned short bCntReload;
02493
02497 volatile short srcCIdx;
02498
02502 volatile short destCIdx;
02503
02507 volatile unsigned short cCnt;
02508
02509 } EDMA3_DRV_PaRAMRegs;
02510
02511
02519 typedef struct
02520 {
02524 unsigned int evtQPri[EDMA3_MAX_EVT_QUE];
02525 }EDMA3_DRV_EvtQuePriority;
02526
02527
02547 EDMA3_DRV_Result EDMA3_DRV_setQdmaTrigWord (EDMA3_DRV_Handle hEdma,
02548 unsigned int lCh,
02549 EDMA3_RM_QdmaTrigWord trigWord);
02550
02551
02573 EDMA3_DRV_Result EDMA3_DRV_setPaRAM ( EDMA3_DRV_Handle hEdma,
02574 unsigned int lCh,
02575 const EDMA3_DRV_PaRAMRegs *newPaRAM);
02576
02577
02591 EDMA3_DRV_Result EDMA3_DRV_getPaRAM (EDMA3_DRV_Handle hEdma,
02592 unsigned int lCh,
02593 EDMA3_DRV_PaRAMRegs *currPaRAM);
02594
02595
02618 EDMA3_DRV_Result EDMA3_DRV_setPaRAMEntry (EDMA3_DRV_Handle hEdma,
02619 unsigned int lCh,
02620 EDMA3_DRV_PaRAMEntry paRAMEntry,
02621 unsigned int newPaRAMEntryVal);
02622
02623
02639 EDMA3_DRV_Result EDMA3_DRV_getPaRAMEntry (EDMA3_DRV_Handle hEdma,
02640 unsigned int lCh,
02641 EDMA3_DRV_PaRAMEntry paRAMEntry,
02642 unsigned int *paRAMEntryVal);
02643
02644
02668 EDMA3_DRV_Result EDMA3_DRV_setPaRAMField (EDMA3_DRV_Handle hEdma,
02669 unsigned int lCh,
02670 EDMA3_DRV_PaRAMField paRAMField,
02671 unsigned int newPaRAMFieldVal);
02672
02673
02689 EDMA3_DRV_Result EDMA3_DRV_getPaRAMField (EDMA3_DRV_Handle hEdma,
02690 unsigned int lCh,
02691 EDMA3_DRV_PaRAMField paRAMField,
02692 unsigned int *currPaRAMFieldVal);
02693
02694
02711 EDMA3_DRV_Result EDMA3_DRV_setEvtQPriority (EDMA3_DRV_Handle hEdma,
02712 const EDMA3_DRV_EvtQuePriority *evtQPriObj);
02713
02714
02733 EDMA3_DRV_Result EDMA3_DRV_mapChToEvtQ (EDMA3_DRV_Handle hEdma,
02734 unsigned int channelId,
02735 EDMA3_RM_EventQueue eventQ);
02736
02737
02751 EDMA3_DRV_Result EDMA3_DRV_getMapChToEvtQ (EDMA3_DRV_Handle hEdma,
02752 unsigned int channelId,
02753 unsigned int *mappedEvtQ);
02754
02755
02756
02775 EDMA3_DRV_Result EDMA3_DRV_setCCRegister (EDMA3_DRV_Handle hEdma,
02776 unsigned int regOffset,
02777 unsigned int newRegValue);
02778
02779
02791 EDMA3_DRV_Result EDMA3_DRV_getCCRegister (EDMA3_DRV_Handle hEdma,
02792 unsigned int regOffset,
02793 unsigned int *regValue);
02794
02795
02796
02815 EDMA3_DRV_Result EDMA3_DRV_waitAndClearTcc (EDMA3_DRV_Handle hEdma,
02816 unsigned int tccNo);
02817
02818
02819
02820
02842 EDMA3_DRV_Result EDMA3_DRV_checkAndClearTcc (EDMA3_DRV_Handle hEdma,
02843 unsigned int tccNo,
02844 unsigned short *tccStatus);
02845
02846
02847
02871 EDMA3_DRV_Result EDMA3_DRV_getPaRAMPhyAddr(EDMA3_DRV_Handle hEdma,
02872 unsigned int lCh,
02873 unsigned int *paramPhyAddr);
02874
02875
02879 typedef enum
02880 {
02881
02882 EDMA3_DRV_IOCTL_MIN_IOCTL = 0,
02883
02904 EDMA3_DRV_IOCTL_SET_PARAM_CLEAR_OPTION,
02905
02918 EDMA3_DRV_IOCTL_GET_PARAM_CLEAR_OPTION,
02919
02920
02921 EDMA3_DRV_IOCTL_MAX_IOCTL
02922 } EDMA3_DRV_IoctlCmd;
02923
02924
02941 EDMA3_DRV_Result EDMA3_DRV_Ioctl(
02942 EDMA3_DRV_Handle hEdma,
02943 EDMA3_DRV_IoctlCmd cmd,
02944 void *cmdArg,
02945 void *param
02946 );
02947
02948
02986 EDMA3_DRV_Handle EDMA3_DRV_getInstHandle(unsigned int phyCtrllerInstId,
02987 EDMA3_RM_RegionId regionId,
02988 EDMA3_DRV_Result *errorCode);
02989
02990
02991
02992
02993
02994
02995
02996 #ifdef __cplusplus
02997 }
02998 #endif
02999
03000 #endif