SPI driver implementation for a CC32XX SPI controller using the micro DMA controller.
The SPI header file should be included in an application as follows:
Refer to SPI.h for a complete description of APIs & example of use.
This SPI driver implementation is designed to operate on a CC32XX SPI controller using a micro DMA controller.
SPI Chip Select
This SPI controller supports a hardware chip select pin. Refer to the device's user manual on how this hardware chip select pin behaves in regards to the SPI frame format.
| Chip select type | SPI_MASTER mode | SPI_SLAVE mode |
| Hardware chip select | No action is needed by the application to select the peripheral. | See the device documentation on it's chip select requirements. |
| Software chip select | The application is responsible to ensure that correct SPI slave is selected before performing a SPI_transfer(). | See the device documentation on it's chip select requirements. |
DMA Interrupts
This driver is designed to operate with the micro DMA. The micro DMA generates an IRQ on the perpheral's interrupt vector. This implementation automatically installs a DMA aware hardware ISR to service the assigned micro DMA channels.
SPI data frames
SPI data frames can be any size from 4-bits to 32-bits. The SPI data frame size is set in SPI_Params.dataSize passed to SPI_open. The SPICC32XXDMA driver implementation makes assumptions on the element size of the SPI_Transaction txBuf and rxBuf arrays, based on the data frame size. If the data frame size is less than or equal to 8 bits, txBuf and rxBuf are assumed to be arrays of 8-bit uint8_t elements. If the data frame size is greater than 8 bits, but less than or equal to 16 bits, txBuf and rxBuf are assumed to be arrays of 16-bit uint16_t elements. Otherwise, txBuf and rxBuf are assumed to point to 32-bit uint32_t elements.
| data frame size | buffer element size |
| 4-8 bits | uint8_t |
| 9-16 bits | uint16_t |
| 16-32 bits | uint32_t |
DMA transfer size limit
The micro DMA controller only supports data transfers of up to 1024 data frames. A data frame can be 4 to 32 bits in length.
DMA accessible memory
As this driver uses uDMA to transfer data/from data buffers, it is the responsibility of the application to ensure that these buffers reside in memory that is accessible by the DMA.
SPICC32XXDMA Hardware attributes.
These fields, with the exception of intPriority, are used by driverlib APIs and therefore must be populated by driverlib macro definitions. For CCWare these definitions are found in:
- driverlib/prcm.h
- driverlib/spi.h
- driverlib/udma.h
- inc/hw_memmap.h
- inc/hw_ints.h
intPriority is the SPI peripheral's interrupt priority, as defined by the underlying OS. It is passed unmodified to the underlying OS's interrupt handler creation code, so you need to refer to the OS documentation for usage. For example, for SYS/BIOS applications, refer to the ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of interrupt priorities. If the driver uses the ti.dpl interface instead of making OS calls directly, then the HwiP port handles the interrupt priority in an OS specific way. In the case of the SYS/BIOS port, intPriority is passed unmodified to Hwi_create().
A sample structure is shown below:
#if defined(__TI_COMPILER_VERSION__)
#pragma DATA_ALIGN(scratchBuf, 32)
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma data_alignment=32
#elif defined(__GNUC__)
__attribute__ ((aligned (32)))
#endif
uint32_t scratchBuf;
{
.intNum = INT_GSPI,
.intPriority = (~0),
.spiPRCM = PRCM_GSPI,
.csControl = SPI_HW_CTRL_CS,
.csPolarity = SPI_CS_ACTIVELOW,
.pinMode = SPI_4PIN_MODE,
.turboMode = SPI_TURBO_OFF,
.scratchBufPtr = &scratchBuf,
.defaultTxBufValue = 0,
.rxChannelIndex = UDMA_CH6_GSPI_RX,
.txChannelIndex = UDMA_CH7_GSPI_TX,
.minDmaTransferSize = 100,
},
...
};
