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ti
sdo
fc
ires
edma3chan
ires_edma3Chan.h
Go to the documentation of this file.
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/*
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* Copyright 2013 by Texas Instruments Incorporated.
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*
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*/
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6
/*
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* Copyright (c) 2012, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* * Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef ti_sdo_fc_ires_edma3chan_IRES_EDMA3CHAN_
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#define ti_sdo_fc_ires_edma3chan_IRES_EDMA3CHAN_
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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#include <
ti/xdais/xdas.h
>
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#include <
ti/xdais/ires_common.h
>
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#define IRES_EDMA3CHAN_PROTOCOLNAME "ti.sdo.fc.ires.edma3chan"
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#define EDMA3CHAN_MODNAME "ti.sdo.fc.ires.edma3chan"
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/*
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* Note, we wrap the PROTOCOLVERSION in an ifdef so the
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* resource managers and algs get this version data placed in their object
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* files. Apps, which include rman.h, will have this 'NOPROTOCOLREV' defined.
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*/
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#ifndef ti_sdo_fc_ires_NOPROTOCOLREV
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static
IRES_ProtocolRevision
IRES_EDMA3CHAN_PROTOCOLREVISION = {1, 0, 0};
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#endif
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#define IRES_EDMA3CHAN_PROTOCOLREVISION_1_0_0 {1, 0, 0}
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#define IRES_EDMA3CHAN_SETPROTOCOLREVISION_1_0_0(rev) {(rev)->Major = 1; \
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(rev)->Source = 0; (rev)->Radius = 0;}
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#define IRES_EDMA3CHAN_PROTOCOLREVISION_2_0_0 {2, 0, 0}
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#define IRES_EDMA3CHAN_SETPROTOCOLREVISION_2_0_0(rev) {(rev)->Major = 2; \
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(rev)->Source = 0; (rev)->Radius = 0;}
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#define IRES_EDMA3CHAN_MAXPARAMS 512
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#define IRES_EDMA3CHAN_MAXTCCS 32
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#define IRES_EDMA3CHAN_NUMDESTTYPES 8
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#define IRES_EDMA3CHAN_PARAM_ANY 512
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#define IRES_EDMA3CHAN_PARAM_NONE 513
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#define IRES_EDMA3CHAN_TCC_ANY 514
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#define IRES_EDMA3CHAN_TCC_NONE 515
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#define IRES_EDMA3CHAN_EDMACHAN_ANY 516
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#define IRES_EDMA3CHAN_QDMACHAN_ANY 516
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#define IRES_EDMA3CHAN_CHAN_NONE 518
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typedef
struct
IRES_EDMA3CHAN_Obj
*
IRES_EDMA3CHAN_Handle
;
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typedef
struct
IRES_EDMA3CHAN2_Obj
*
IRES_EDMA3CHAN2_Handle
;
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146
/* Note that the field descriptions were originally taken from SPRU996. */
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typedef
struct
IRES_EDMA3CHAN_PaRamStruct
{
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unsigned
int
opt
;
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unsigned
int
src
;
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unsigned
short
acnt
;
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unsigned
short
bcnt
;
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unsigned
int
dst
;
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unsigned
short
srcElementIndex
;
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unsigned
short
dstElementIndex
;
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unsigned
short
link
;
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unsigned
short
bCntrld
;
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unsigned
short
srcFrameIndex
;
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unsigned
short
dstFrameIndex
;
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unsigned
short
ccnt
;
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unsigned
short
rsvd
;
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}
IRES_EDMA3CHAN_PaRamStruct
;
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typedef
struct
IRES_EDMA3CHAN_ProtocolArgs
{
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int
size
;
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IRES_RequestMode
mode
;
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short
numPaRams
;
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short
paRamIndex
;
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short
numTccs
;
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short
tccIndex
;
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short
qdmaChan
;
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short
edmaChan
;
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short
contiguousAllocation
;
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short
shadowPaRamsAllocation
;
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}
IRES_EDMA3CHAN_ProtocolArgs
;
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typedef
struct
IRES_EDMA3CHAN_Obj
{
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IRES_Obj
ires
;
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IRES_EDMA3CHAN_PaRamStruct
*
shadowPaRams
;
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unsigned
int
*
assignedPaRamAddresses
;
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short
*
assignedPaRamIndices
;
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short
*
assignedTccIndices
;
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short
assignedNumPaRams
;
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short
assignedNumTccs
;
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short
assignedQdmaChannelIndex
;
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short
assignedEdmaChannelIndex
;
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unsigned
int
esrBitMaskL
;
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unsigned
int
esrBitMaskH
;
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unsigned
int
iprBitMaskL
;
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unsigned
int
iprBitMaskH
;
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}
IRES_EDMA3CHAN_Obj
;
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typedef
struct
IRES_EDMA3CHAN_EDMA3ShadowRegister
{
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volatile
unsigned
int
ER
;
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volatile
unsigned
int
ERH
;
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volatile
unsigned
int
ECR
;
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volatile
unsigned
int
ECRH
;
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volatile
unsigned
int
ESR
;
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volatile
unsigned
int
ESRH
;
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volatile
unsigned
int
CER
;
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volatile
unsigned
int
CERH
;
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volatile
unsigned
int
EER
;
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volatile
unsigned
int
EERH
;
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volatile
unsigned
int
EECR
;
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volatile
unsigned
int
EECRH
;
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volatile
unsigned
int
EESR
;
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volatile
unsigned
int
EESRH
;
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volatile
unsigned
int
SER
;
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volatile
unsigned
int
SERH
;
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volatile
unsigned
int
SECR
;
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volatile
unsigned
int
SECRH
;
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volatile
unsigned
char
RSVD0
[8];
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volatile
unsigned
int
IER
;
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volatile
unsigned
int
IERH
;
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volatile
unsigned
int
IECR
;
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volatile
unsigned
int
IECRH
;
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volatile
unsigned
int
IESR
;
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volatile
unsigned
int
IESRH
;
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volatile
unsigned
int
IPR
;
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volatile
unsigned
int
IPRH
;
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volatile
unsigned
int
ICR
;
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volatile
unsigned
int
ICRH
;
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volatile
unsigned
int
IEVAL
;
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volatile
unsigned
char
RSVD1
[4];
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volatile
unsigned
int
QER
;
493
volatile
unsigned
int
QEER
;
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volatile
unsigned
int
QEECR
;
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volatile
unsigned
int
QEESR
;
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volatile
unsigned
int
QSER
;
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volatile
unsigned
int
QSECR
;
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volatile
unsigned
char
RSVD2
[360];
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}
IRES_EDMA3CHAN_EDMA3ShadowRegister
;
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typedef
struct
IRES_EDMA3CHAN_EDMA3DraeRegister
{
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volatile
unsigned
int
DRAE
;
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volatile
unsigned
int
DRAEH
;
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}
IRES_EDMA3CHAN_EDMA3DraeRegister
;
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typedef
struct
IRES_EDMA3CHAN_EDMA3RegisterLayer
{
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volatile
unsigned
int
REV
;
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volatile
unsigned
int
CCCFG
;
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volatile
unsigned
char
RSVD0
[248];
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volatile
unsigned
int
DCHMAP
[64];
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volatile
unsigned
int
QCHMAP
[8];
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volatile
unsigned
char
RSVD1
[32];
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volatile
unsigned
int
DMAQNUM
[8];
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volatile
unsigned
int
QDMAQNUM
;
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volatile
unsigned
char
RSVD2
[28];
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volatile
unsigned
int
QUETCMAP
;
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volatile
unsigned
int
QUEPRI
;
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volatile
unsigned
char
RSVD3
[120];
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volatile
unsigned
int
EMR
;
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volatile
unsigned
int
EMRH
;
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volatile
unsigned
int
EMCR
;
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volatile
unsigned
int
EMCRH
;
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volatile
unsigned
int
QEMR
;
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volatile
unsigned
int
QEMCR
;
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volatile
unsigned
int
CCERR
;
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volatile
unsigned
int
CCERRCLR
;
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volatile
unsigned
int
EEVAL
;
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volatile
unsigned
char
RSVD4
[28];
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IRES_EDMA3CHAN_EDMA3DraeRegister
DRA
[8];
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volatile
unsigned
int
QRAE
[8];
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volatile
unsigned
char
RSVD5
[96];
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volatile
unsigned
int
QUEEVTENTRY
[8][16];
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volatile
unsigned
int
QSTAT
[8];
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volatile
unsigned
int
QWMTHRA
;
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volatile
unsigned
int
QWMTHRB
;
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volatile
unsigned
char
RSVD6
[24];
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volatile
unsigned
int
CCSTAT
;
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volatile
unsigned
char
RSVD7
[188];
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volatile
unsigned
int
AETCTL
;
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volatile
unsigned
int
AETSTAT
;
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volatile
unsigned
int
AETCMD
;
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volatile
unsigned
char
RSVD8
[244];
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volatile
unsigned
int
MPFAR
;
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volatile
unsigned
int
MPFSR
;
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volatile
unsigned
int
MPFCR
;
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volatile
unsigned
int
MPPAG
;
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volatile
unsigned
int
MPPA
[8];
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volatile
unsigned
char
RSVD9
[2000];
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volatile
unsigned
int
ER
;
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volatile
unsigned
int
ERH
;
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volatile
unsigned
int
ECR
;
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volatile
unsigned
int
ECRH
;
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volatile
unsigned
int
ESR
;
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volatile
unsigned
int
ESRH
;
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volatile
unsigned
int
CER
;
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volatile
unsigned
int
CERH
;
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volatile
unsigned
int
EER
;
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volatile
unsigned
int
EERH
;
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volatile
unsigned
int
EECR
;
568
volatile
unsigned
int
EECRH
;
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volatile
unsigned
int
EESR
;
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volatile
unsigned
int
EESRH
;
571
volatile
unsigned
int
SER
;
572
volatile
unsigned
int
SERH
;
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volatile
unsigned
int
SECR
;
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volatile
unsigned
int
SECRH
;
575
volatile
unsigned
char
RSVD10
[8];
576
volatile
unsigned
int
IER
;
577
volatile
unsigned
int
IERH
;
578
volatile
unsigned
int
IECR
;
579
volatile
unsigned
int
IECRH
;
580
volatile
unsigned
int
IESR
;
581
volatile
unsigned
int
IESRH
;
582
volatile
unsigned
int
IPR
;
583
volatile
unsigned
int
IPRH
;
584
volatile
unsigned
int
ICR
;
585
volatile
unsigned
int
ICRH
;
586
volatile
unsigned
int
IEVAL
;
587
volatile
unsigned
char
RSVD11
[4];
588
volatile
unsigned
int
QER
;
589
volatile
unsigned
int
QEER
;
590
volatile
unsigned
int
QEECR
;
591
volatile
unsigned
int
QEESR
;
592
volatile
unsigned
int
QSER
;
593
volatile
unsigned
int
QSECR
;
594
volatile
unsigned
char
RSVD12
[3944];
595
IRES_EDMA3CHAN_EDMA3ShadowRegister
SHADOW
[8];
596
volatile
unsigned
char
RSVD13
[4096];
597
IRES_EDMA3CHAN_PaRamStruct
PARAMENTRY
[512];
598
}
IRES_EDMA3CHAN_EDMA3RegisterLayer
;
599
603
typedef
struct
IRES_EDMA3CHAN_Properties
{
604
605
unsigned
int
numDmaChannels
;
608
unsigned
int
numQdmaChannels
;
612
unsigned
int
numTccs
;
615
unsigned
int
numPaRAMSets
;
618
unsigned
int
numEvtQueue
;
621
unsigned
int
numTcs
;
625
unsigned
int
numRegions
;
636
unsigned
short
dmaChPaRAMMapExists
;
637
638
unsigned
short
memProtectionExists
;
642
IRES_EDMA3CHAN_EDMA3RegisterLayer
*
globalRegs
;
646
}
IRES_EDMA3CHAN_Properties
;
647
655
typedef
enum
IRES_EDMA3CHAN_DmaDestType
{
656
INTMEMORY0
= 0,
657
INTMEMORY1
= 1,
658
INTMEMORY2
= 2,
659
EXTMEMORY0
= 3,
660
EXTMEMORY1
= 4,
661
EXTMEMORY2
= 5,
662
OTHER0
= 6,
663
OTHER1
= 7
664
}
IRES_EDMA3CHAN_DmaDestType
;
665
684
typedef
struct
IRES_EDMA3CHAN2_Obj
{
685
686
IRES_Obj
ires
;
687
689
IRES_EDMA3CHAN_PaRamStruct
*
shadowPaRams
;
690
692
unsigned
int
*
assignedPaRamAddresses
;
693
695
short
*
assignedPaRamIndices
;
696
698
short
*
assignedTccIndices
;
699
701
short
assignedNumPaRams
;
702
704
short
assignedNumTccs
;
705
707
short
assignedQdmaChannelIndex
;
708
710
short
assignedEdmaChannelIndex
;
711
713
unsigned
int
esrBitMaskL
;
714
716
unsigned
int
esrBitMaskH
;
717
719
unsigned
int
iprBitMaskL
;
720
722
unsigned
int
iprBitMaskH
;
723
724
XDAS_Int32
*
queueMap
;
738
}
IRES_EDMA3CHAN2_Obj
;
739
740
#ifdef __cplusplus
741
}
742
#endif
/* extern "C" */
743
746
#endif
747
/*
748
* @(#) ti.sdo.fc.ires.edma3chan; 1, 0, 0,; 10-29-2013 18:38:30; /db/atree/library/trees/fc/fc-t15/src/ xlibrary
749
750
*/
751
Copyright 2013, Texas Instruments Incorporated