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Central repository for error and status code bases and ranges for DSP/BIOS LINK and any Algorithm Framework built on top of LINK.
============================================================================
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
* Neither the name of Texas Instruments Incorporated nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ============================================================================
#include <gpptypes.h>
Go to the source code of this file.
Defines | |
| #define | DSP_SUCCEEDED(status) |
| #define | DSP_FAILED(status) (!DSP_SUCCEEDED (status)) |
| #define | RINGIO_SUCCEEDED(status) |
| #define | RINGIO_FAILED(status) |
| #define | DSP_SBASE (DSP_STATUS)0x00008000l |
| #define | DSP_SLAST (DSP_STATUS)0x00008500l |
| #define | RINGIO_SBASE (DSP_STATUS)0x00008100l |
| #define | RINGIO_SLAST (DSP_STATUS)0x000081FFl |
| #define | DSP_EBASE (DSP_STATUS)0x80008000l |
| #define | DSP_ELAST (DSP_STATUS)0x800081FFl |
| #define | DSP_COMP_EBASE (DSP_STATUS)0x80040200l |
| #define | DSP_COMP_ELAST (DSP_STATUS)0x80047fffl |
| #define | DSP_SOK (DSP_SBASE + 0x0l) |
| #define | DSP_SALREADYATTACHED (DSP_SBASE + 0x1l) |
| #define | DSP_SENUMCOMPLETE (DSP_SBASE + 0x2l) |
| #define | DSP_SFINALIZED (DSP_SBASE + 0x3l) |
| #define | DSP_SALREADYOPENED (DSP_SBASE + 0x4l) |
| #define | DSP_SEXISTS (DSP_SBASE + 0x5l) |
| #define | DSP_SFREE (DSP_SBASE + 0x6l) |
| #define | DSP_SALREADYSETUP (DSP_SBASE + 0x7l) |
| #define | DSP_SDESTROYED (DSP_SBASE + 0x8l) |
| #define | DSP_SDETACHED (DSP_SBASE + 0x9l) |
| #define | DSP_SALREADYLOADED (DSP_SBASE + 0xAl) |
| #define | DSP_SALREADYSTARTED (DSP_SBASE + 0xBl) |
| #define | DSP_SSTOPPED (DSP_SBASE + 0xCl) |
| #define | DSP_SCLOSED (DSP_SBASE + 0xDl) |
| #define | RINGIO_SUCCESS (RINGIO_SBASE + 0x0l) |
| #define | RINGIO_SPENDINGATTRIBUTE (RINGIO_SBASE + 0x1l) |
| #define | DSP_EACCESSDENIED (DSP_EBASE + 0x0l) |
| #define | DSP_EALREADYCONNECTED (DSP_EBASE + 0x1l) |
| #define | DSP_EATTACHED (DSP_EBASE + 0x2l) |
| #define | DSP_ECHANGEDURINGENUM (DSP_EBASE + 0x3l) |
| #define | DSP_ECORRUPTFILE (DSP_EBASE + 0x4l) |
| #define | DSP_EDELETE (DSP_EBASE + 0x5l) |
| #define | DSP_EDIRECTION (DSP_EBASE + 0x6l) |
| #define | DSP_ESTREAMFULL (DSP_EBASE + 0x7l) |
| #define | DSP_EFAIL (DSP_EBASE + 0x8l) |
| #define | DSP_EFILE (DSP_EBASE + 0x9l) |
| #define | DSP_EHANDLE (DSP_EBASE + 0xAl) |
| #define | DSP_EINVALIDARG (DSP_EBASE + 0xBl) |
| #define | DSP_EMEMORY (DSP_EBASE + 0xCl) |
| #define | DSP_ESETUP (DSP_EBASE + 0xDl) |
| #define | DSP_ESTARTED (DSP_EBASE + 0xEl) |
| #define | DSP_EINIT (DSP_EBASE + 0xFl) |
| #define | DSP_ENOTIMPL (DSP_EBASE + 0x10l) |
| #define | DSP_EPENDING (DSP_EBASE + 0x11l) |
| #define | DSP_EPOINTER (DSP_EBASE + 0x12l) |
| #define | DSP_ERANGE (DSP_EBASE + 0x13l) |
| #define | DSP_ESIZE (DSP_EBASE + 0x14l) |
| #define | DSP_ESTREAM (DSP_EBASE + 0x15l) |
| #define | DSP_ETASK (DSP_EBASE + 0x16l) |
| #define | DSP_ETIMEOUT (DSP_EBASE + 0x17l) |
| #define | DSP_ETRUNCATED (DSP_EBASE + 0x18l) |
| #define | DSP_EOPENED (DSP_EBASE + 0x19l) |
| #define | DSP_EVALUE (DSP_EBASE + 0x1Al) |
| #define | DSP_EWRONGSTATE (DSP_EBASE + 0x1Bl) |
| #define | DSP_EALREADYSETUP (DSP_EBASE + 0x1Cl) |
| #define | DSP_EINTR (DSP_EBASE + 0x1Dl) |
| #define | DSP_EALREADYSTARTED (DSP_EBASE + 0x1El) |
| #define | DSP_EALREADYOPENED (DSP_EBASE + 0x1Fl) |
| #define | DSP_ERESERVED_06 (DSP_EBASE + 0x20l) |
| #define | DSP_ERESERVED_07 (DSP_EBASE + 0x21l) |
| #define | DSP_ERESERVED_08 (DSP_EBASE + 0x22l) |
| #define | DSP_ERESERVED_09 (DSP_EBASE + 0x23l) |
| #define | DSP_ERESERVED_0A (DSP_EBASE + 0x24l) |
| #define | DSP_ERESERVED_0B (DSP_EBASE + 0x25l) |
| #define | DSP_ERESERVED_0C (DSP_EBASE + 0x26l) |
| #define | DSP_ERESERVED_0D (DSP_EBASE + 0x27l) |
| #define | DSP_ERESOURCE (DSP_EBASE + 0x28l) |
| #define | DSP_ERESTART (DSP_EBASE + 0x29l) |
| #define | DSP_EFREE (DSP_EBASE + 0x2Al) |
| #define | DSP_EIOFREE (DSP_EBASE + 0x2Bl) |
| #define | DSP_EMULINST (DSP_EBASE + 0x2Cl) |
| #define | DSP_ENOTFOUND (DSP_EBASE + 0x2Dl) |
| #define | DSP_EOUTOFIO (DSP_EBASE + 0x2El) |
| #define | DSP_ETRANSLATE (DSP_EBASE + 0x2fl) |
| #define | DSP_EVERSION (DSP_EBASE + 0x30l) |
| #define | DSP_EFWRITE (DSP_EBASE + 0x31l) |
| #define | DSP_ENOSECT (DSP_EBASE + 0x32l) |
| #define | DSP_ERESERVED_0F (DSP_EBASE + 0x33l) |
| #define | DSP_ERESERVED_10 (DSP_EBASE + 0x34l) |
| #define | DSP_ERESERVED_11 (DSP_EBASE + 0x35l) |
| #define | DSP_ERESERVED_12 (DSP_EBASE + 0x36l) |
| #define | DSP_ERESERVED_13 (DSP_EBASE + 0x37l) |
| #define | DSP_ERESERVED_14 (DSP_EBASE + 0x38l) |
| #define | DSP_ERESERVED_15 (DSP_EBASE + 0x39l) |
| #define | DSP_ERESERVED_16 (DSP_EBASE + 0x3Al) |
| #define | DSP_ERESERVED_17 (DSP_EBASE + 0x3Bl) |
| #define | DSP_ERESERVED_18 (DSP_EBASE + 0x3Cl) |
| #define | DSP_ERESERVED_19 (DSP_EBASE + 0x3Dl) |
| #define | DSP_ERESERVED_1A (DSP_EBASE + 0x3El) |
| #define | DSP_ERESERVED_1B (DSP_EBASE + 0x3Fl) |
| #define | DSP_ERESERVED_1C (DSP_EBASE + 0x40l) |
| #define | DSP_ERESERVED_1D (DSP_EBASE + 0x41l) |
| #define | DSP_ERESERVED_1E (DSP_EBASE + 0x42l) |
| #define | DSP_ERESERVED_1F (DSP_EBASE + 0x43l) |
| #define | DSP_ERESERVED_20 (DSP_EBASE + 0x44l) |
| #define | DSP_ERESERVED_21 (DSP_EBASE + 0x45l) |
| #define | DSP_ERESERVED_22 (DSP_EBASE + 0x46l) |
| #define | DSP_ERESERVED_23 (DSP_EBASE + 0x47l) |
| #define | DSP_ERESERVED_24 (DSP_EBASE + 0x48l) |
| #define | DSP_ERESERVED_25 (DSP_EBASE + 0x49l) |
| #define | DSP_ERESERVED_26 (DSP_EBASE + 0x4al) |
| #define | DSP_ERESERVED_27 (DSP_EBASE + 0x4bl) |
| #define | DSP_ERESERVED_28 (DSP_EBASE + 0x4cl) |
| #define | DSP_ERESERVED_29 (DSP_EBASE + 0x4dl) |
| #define | DSP_ERESERVED_2A (DSP_EBASE + 0x4el) |
| #define | DSP_ERESERVED_2B (DSP_EBASE + 0x4fl) |
| #define | DSP_EALREADYEXISTS (DSP_EBASE + 0x50l) |
| #define | DSP_ENOTCOMPLETE (DSP_EBASE + 0x51l) |
| #define | DSP_ECONFIG (DSP_EBASE + 0x52l) |
| #define | DSP_ENOTSUPPORTED (DSP_EBASE + 0x53l) |
| #define | DSP_ENOTREADY (DSP_EBASE + 0x54l) |
| #define | RINGIO_EBASE (DSP_EBASE + 0x55l) |
| #define | RINGIO_EFAILURE (RINGIO_EBASE + 0x00l) |
| #define | RINGIO_EBUFWRAP (RINGIO_EBASE + 0x01l) |
| #define | RINGIO_EBUFEMPTY (RINGIO_EBASE + 0x02l) |
| #define | RINGIO_EBUFFULL (RINGIO_EBASE + 0x03l) |
| #define | RINGIO_EPENDINGDATA (RINGIO_EBASE + 0x04l) |
| #define | RINGIO_EVARIABLEATTRIBUTE (RINGIO_EBASE + 0x05l) |
| #define | RINGIO_EALREADYEXISTS (RINGIO_EBASE + 0x06l) |
| #define | RINGIO_ENOTCONTIGUOUSDATA (RINGIO_EBASE + 0x07l) |
| #define | RINGIO_EWRONGSTATE (RINGIO_EBASE + 0x08l) |
| #define | DSP_ERESERVED_BASE_1 (DSP_COMP_EBASE + 0x000l) |
| #define | DSP_ERESERVED_BASE_2 (DSP_COMP_EBASE + 0x100l) |
| #define | DSP_ERESERVED_BASE_3 (DSP_COMP_EBASE + 0x200l) |
| #define | DSP_ERESERVED_BASE_4 (DSP_COMP_EBASE + 0x300l) |
| #define | DSP_ERESERVED_BASE_5 (DSP_COMP_EBASE + 0x400l) |
| #define | CHNL_EBASE (DSP_COMP_EBASE + 0x500l) |
| #define | CHNL_E_MAXCHANNELS (CHNL_EBASE + 0x00l) |
| #define | CHNL_E_RESERVED_1 (CHNL_EBASE + 0x01l) |
| #define | CHNL_E_OUTOFSTREAMS (CHNL_EBASE + 0x02l) |
| #define | CHNL_E_BADCHANID (CHNL_EBASE + 0x03l) |
| #define | CHNL_E_CHANBUSY (CHNL_EBASE + 0x04l) |
| #define | CHNL_E_BADMODE (CHNL_EBASE + 0x05l) |
| #define | CHNL_E_NOIOC (CHNL_EBASE + 0x06l) |
| #define | CHNL_E_CANCELLED (CHNL_EBASE + 0x07l) |
| #define | CHNL_E_EOS (CHNL_EBASE + 0x09l) |
| #define | CHNL_E_CREATEEVENT (CHNL_EBASE + 0x0Al) |
| #define | CHNL_E_RESERVED_2 (CHNL_EBASE + 0x0Bl) |
| #define | CHNL_E_RESERVED_3 (CHNL_EBASE + 0x0Cl) |
| #define | CHNL_E_INVALIDWORDSIZE (CHNL_EBASE + 0x0Dl) |
| #define | CHNL_E_RESERVED_4 (CHNL_EBASE + 0x0El) |
| #define | CHNL_E_RESERVED_5 (CHNL_EBASE + 0x0Fl) |
| #define | CHNL_E_RESERVED_6 (CHNL_EBASE + 0x10l) |
| #define | CHNL_E_ISR (CHNL_EBASE + 0x11l) |
| #define | CHNL_E_NOIORPS (CHNL_EBASE + 0x12l) |
| #define | CHNL_E_BUFSIZE (CHNL_EBASE + 0x13l) |
| #define | CHNL_E_NOEOS (CHNL_EBASE + 0x14l) |
| #define | CHNL_E_WAITTIMEOUT (CHNL_EBASE + 0x15l) |
| #define | CHNL_E_RESERVED_7 (CHNL_EBASE + 0x16l) |
| #define | CHNL_E_RESERVED_8 (CHNL_EBASE + 0x17l) |
| #define | CHNL_E_RESERVED_9 (CHNL_EBASE + 0x18l) |
| #define | CHNL_E_RESERVED_10 (CHNL_EBASE + 0x19l) |
| #define | CHNL_E_WRONGSTATE (CHNL_EBASE + 0x1Al) |
| #define | SYNC_EBASE (DSP_COMP_EBASE + 0x600l) |
| #define | SYNC_E_FAIL (SYNC_EBASE + 0x00l) |
| #define | SYNC_E_TIMEOUT (SYNC_EBASE + 0x01l) |
| #define | DSP_ERESERVED_BASE_6 (DSP_COMP_EBASE + 0x700l) |
| #define | DSP_ERESERVED_BASE_7 (DSP_COMP_EBASE + 0x800l) |
| #define | DSP_EIRQNONE (DSP_COMP_EBASE + 0x900l) |
Typedefs | |
| typedef Int32 | DSP_STATUS |
| #define DSP_SUCCEEDED | ( | status ) |
| #define DSP_FAILED | ( | status ) | (!DSP_SUCCEEDED (status)) |
| #define RINGIO_SUCCEEDED | ( | status ) |
( ((Int32) (status) >= (RINGIO_SBASE)) \ && ((Int32) (status) <= (RINGIO_SLAST)))
| #define RINGIO_FAILED | ( | status ) |
( (!RINGIO_SUCCEEDED (status)) \ && (DSP_FAILED (status)))
| #define DSP_SBASE (DSP_STATUS)0x00008000l |
| #define DSP_SLAST (DSP_STATUS)0x00008500l |
| #define RINGIO_SBASE (DSP_STATUS)0x00008100l |
| #define RINGIO_SLAST (DSP_STATUS)0x000081FFl |
| #define DSP_EBASE (DSP_STATUS)0x80008000l |
| #define DSP_ELAST (DSP_STATUS)0x800081FFl |
| #define DSP_COMP_EBASE (DSP_STATUS)0x80040200l |
| #define DSP_COMP_ELAST (DSP_STATUS)0x80047fffl |
| #define DSP_SOK (DSP_SBASE + 0x0l) |
| #define DSP_SALREADYATTACHED (DSP_SBASE + 0x1l) |
| #define DSP_SENUMCOMPLETE (DSP_SBASE + 0x2l) |
| #define DSP_SFINALIZED (DSP_SBASE + 0x3l) |
| #define DSP_SALREADYOPENED (DSP_SBASE + 0x4l) |
| #define DSP_SEXISTS (DSP_SBASE + 0x5l) |
| #define DSP_SFREE (DSP_SBASE + 0x6l) |
| #define DSP_SALREADYSETUP (DSP_SBASE + 0x7l) |
| #define DSP_SDESTROYED (DSP_SBASE + 0x8l) |
| #define DSP_SDETACHED (DSP_SBASE + 0x9l) |
| #define DSP_SALREADYLOADED (DSP_SBASE + 0xAl) |
| #define DSP_SALREADYSTARTED (DSP_SBASE + 0xBl) |
| #define DSP_SSTOPPED (DSP_SBASE + 0xCl) |
| #define DSP_SCLOSED (DSP_SBASE + 0xDl) |
| #define RINGIO_SUCCESS (RINGIO_SBASE + 0x0l) |
| #define RINGIO_SPENDINGATTRIBUTE (RINGIO_SBASE + 0x1l) |
| #define DSP_EACCESSDENIED (DSP_EBASE + 0x0l) |
| #define DSP_EALREADYCONNECTED (DSP_EBASE + 0x1l) |
| #define DSP_EATTACHED (DSP_EBASE + 0x2l) |
| #define DSP_ECHANGEDURINGENUM (DSP_EBASE + 0x3l) |
| #define DSP_ECORRUPTFILE (DSP_EBASE + 0x4l) |
| #define DSP_EDELETE (DSP_EBASE + 0x5l) |
| #define DSP_EDIRECTION (DSP_EBASE + 0x6l) |
| #define DSP_ESTREAMFULL (DSP_EBASE + 0x7l) |
| #define DSP_EFAIL (DSP_EBASE + 0x8l) |
| #define DSP_EFILE (DSP_EBASE + 0x9l) |
| #define DSP_EHANDLE (DSP_EBASE + 0xAl) |
| #define DSP_EINVALIDARG (DSP_EBASE + 0xBl) |
| #define DSP_EMEMORY (DSP_EBASE + 0xCl) |
| #define DSP_ESETUP (DSP_EBASE + 0xDl) |
| #define DSP_ESTARTED (DSP_EBASE + 0xEl) |
| #define DSP_EINIT (DSP_EBASE + 0xFl) |
| #define DSP_ENOTIMPL (DSP_EBASE + 0x10l) |
| #define DSP_EPENDING (DSP_EBASE + 0x11l) |
| #define DSP_EPOINTER (DSP_EBASE + 0x12l) |
| #define DSP_ERANGE (DSP_EBASE + 0x13l) |
| #define DSP_ESIZE (DSP_EBASE + 0x14l) |
| #define DSP_ESTREAM (DSP_EBASE + 0x15l) |
| #define DSP_ETASK (DSP_EBASE + 0x16l) |
| #define DSP_ETIMEOUT (DSP_EBASE + 0x17l) |
| #define DSP_ETRUNCATED (DSP_EBASE + 0x18l) |
| #define DSP_EOPENED (DSP_EBASE + 0x19l) |
| #define DSP_EVALUE (DSP_EBASE + 0x1Al) |
| #define DSP_EWRONGSTATE (DSP_EBASE + 0x1Bl) |
| #define DSP_EALREADYSETUP (DSP_EBASE + 0x1Cl) |
| #define DSP_EINTR (DSP_EBASE + 0x1Dl) |
| #define DSP_EALREADYSTARTED (DSP_EBASE + 0x1El) |
| #define DSP_EALREADYOPENED (DSP_EBASE + 0x1Fl) |
| #define DSP_ERESERVED_06 (DSP_EBASE + 0x20l) |
| #define DSP_ERESERVED_07 (DSP_EBASE + 0x21l) |
| #define DSP_ERESERVED_08 (DSP_EBASE + 0x22l) |
| #define DSP_ERESERVED_09 (DSP_EBASE + 0x23l) |
| #define DSP_ERESERVED_0A (DSP_EBASE + 0x24l) |
| #define DSP_ERESERVED_0B (DSP_EBASE + 0x25l) |
| #define DSP_ERESERVED_0C (DSP_EBASE + 0x26l) |
| #define DSP_ERESERVED_0D (DSP_EBASE + 0x27l) |
| #define DSP_ERESOURCE (DSP_EBASE + 0x28l) |
| #define DSP_ERESTART (DSP_EBASE + 0x29l) |
| #define DSP_EFREE (DSP_EBASE + 0x2Al) |
| #define DSP_EIOFREE (DSP_EBASE + 0x2Bl) |
| #define DSP_EMULINST (DSP_EBASE + 0x2Cl) |
| #define DSP_ENOTFOUND (DSP_EBASE + 0x2Dl) |
| #define DSP_EOUTOFIO (DSP_EBASE + 0x2El) |
| #define DSP_ETRANSLATE (DSP_EBASE + 0x2fl) |
| #define DSP_EVERSION (DSP_EBASE + 0x30l) |
| #define DSP_EFWRITE (DSP_EBASE + 0x31l) |
| #define DSP_ENOSECT (DSP_EBASE + 0x32l) |
| #define DSP_ERESERVED_0F (DSP_EBASE + 0x33l) |
| #define DSP_ERESERVED_10 (DSP_EBASE + 0x34l) |
| #define DSP_ERESERVED_11 (DSP_EBASE + 0x35l) |
| #define DSP_ERESERVED_12 (DSP_EBASE + 0x36l) |
| #define DSP_ERESERVED_13 (DSP_EBASE + 0x37l) |
| #define DSP_ERESERVED_14 (DSP_EBASE + 0x38l) |
| #define DSP_ERESERVED_15 (DSP_EBASE + 0x39l) |
| #define DSP_ERESERVED_16 (DSP_EBASE + 0x3Al) |
| #define DSP_ERESERVED_17 (DSP_EBASE + 0x3Bl) |
| #define DSP_ERESERVED_18 (DSP_EBASE + 0x3Cl) |
| #define DSP_ERESERVED_19 (DSP_EBASE + 0x3Dl) |
| #define DSP_ERESERVED_1A (DSP_EBASE + 0x3El) |
| #define DSP_ERESERVED_1B (DSP_EBASE + 0x3Fl) |
| #define DSP_ERESERVED_1C (DSP_EBASE + 0x40l) |
| #define DSP_ERESERVED_1D (DSP_EBASE + 0x41l) |
| #define DSP_ERESERVED_1E (DSP_EBASE + 0x42l) |
| #define DSP_ERESERVED_1F (DSP_EBASE + 0x43l) |
| #define DSP_ERESERVED_20 (DSP_EBASE + 0x44l) |
| #define DSP_ERESERVED_21 (DSP_EBASE + 0x45l) |
| #define DSP_ERESERVED_22 (DSP_EBASE + 0x46l) |
| #define DSP_ERESERVED_23 (DSP_EBASE + 0x47l) |
| #define DSP_ERESERVED_24 (DSP_EBASE + 0x48l) |
| #define DSP_ERESERVED_25 (DSP_EBASE + 0x49l) |
| #define DSP_ERESERVED_26 (DSP_EBASE + 0x4al) |
| #define DSP_ERESERVED_27 (DSP_EBASE + 0x4bl) |
| #define DSP_ERESERVED_28 (DSP_EBASE + 0x4cl) |
| #define DSP_ERESERVED_29 (DSP_EBASE + 0x4dl) |
| #define DSP_ERESERVED_2A (DSP_EBASE + 0x4el) |
| #define DSP_ERESERVED_2B (DSP_EBASE + 0x4fl) |
| #define DSP_EALREADYEXISTS (DSP_EBASE + 0x50l) |
| #define DSP_ENOTCOMPLETE (DSP_EBASE + 0x51l) |
| #define DSP_ECONFIG (DSP_EBASE + 0x52l) |
| #define DSP_ENOTSUPPORTED (DSP_EBASE + 0x53l) |
| #define DSP_ENOTREADY (DSP_EBASE + 0x54l) |
| #define RINGIO_EBASE (DSP_EBASE + 0x55l) |
| #define RINGIO_EFAILURE (RINGIO_EBASE + 0x00l) |
| #define RINGIO_EBUFWRAP (RINGIO_EBASE + 0x01l) |
| #define RINGIO_EBUFEMPTY (RINGIO_EBASE + 0x02l) |
| #define RINGIO_EBUFFULL (RINGIO_EBASE + 0x03l) |
| #define RINGIO_EPENDINGDATA (RINGIO_EBASE + 0x04l) |
| #define RINGIO_EVARIABLEATTRIBUTE (RINGIO_EBASE + 0x05l) |
| #define RINGIO_EALREADYEXISTS (RINGIO_EBASE + 0x06l) |
| #define RINGIO_ENOTCONTIGUOUSDATA (RINGIO_EBASE + 0x07l) |
| #define RINGIO_EWRONGSTATE (RINGIO_EBASE + 0x08l) |
| #define DSP_ERESERVED_BASE_1 (DSP_COMP_EBASE + 0x000l) |
| #define DSP_ERESERVED_BASE_2 (DSP_COMP_EBASE + 0x100l) |
| #define DSP_ERESERVED_BASE_3 (DSP_COMP_EBASE + 0x200l) |
| #define DSP_ERESERVED_BASE_4 (DSP_COMP_EBASE + 0x300l) |
| #define DSP_ERESERVED_BASE_5 (DSP_COMP_EBASE + 0x400l) |
| #define CHNL_EBASE (DSP_COMP_EBASE + 0x500l) |
| #define CHNL_E_MAXCHANNELS (CHNL_EBASE + 0x00l) |
| #define CHNL_E_RESERVED_1 (CHNL_EBASE + 0x01l) |
| #define CHNL_E_OUTOFSTREAMS (CHNL_EBASE + 0x02l) |
| #define CHNL_E_BADCHANID (CHNL_EBASE + 0x03l) |
| #define CHNL_E_CHANBUSY (CHNL_EBASE + 0x04l) |
| #define CHNL_E_BADMODE (CHNL_EBASE + 0x05l) |
| #define CHNL_E_NOIOC (CHNL_EBASE + 0x06l) |
| #define CHNL_E_CANCELLED (CHNL_EBASE + 0x07l) |
| #define CHNL_E_EOS (CHNL_EBASE + 0x09l) |
| #define CHNL_E_CREATEEVENT (CHNL_EBASE + 0x0Al) |
| #define CHNL_E_RESERVED_2 (CHNL_EBASE + 0x0Bl) |
| #define CHNL_E_RESERVED_3 (CHNL_EBASE + 0x0Cl) |
| #define CHNL_E_INVALIDWORDSIZE (CHNL_EBASE + 0x0Dl) |
| #define CHNL_E_RESERVED_4 (CHNL_EBASE + 0x0El) |
| #define CHNL_E_RESERVED_5 (CHNL_EBASE + 0x0Fl) |
| #define CHNL_E_RESERVED_6 (CHNL_EBASE + 0x10l) |
| #define CHNL_E_ISR (CHNL_EBASE + 0x11l) |
| #define CHNL_E_NOIORPS (CHNL_EBASE + 0x12l) |
| #define CHNL_E_BUFSIZE (CHNL_EBASE + 0x13l) |
| #define CHNL_E_NOEOS (CHNL_EBASE + 0x14l) |
| #define CHNL_E_WAITTIMEOUT (CHNL_EBASE + 0x15l) |
| #define CHNL_E_RESERVED_7 (CHNL_EBASE + 0x16l) |
| #define CHNL_E_RESERVED_8 (CHNL_EBASE + 0x17l) |
| #define CHNL_E_RESERVED_9 (CHNL_EBASE + 0x18l) |
| #define CHNL_E_RESERVED_10 (CHNL_EBASE + 0x19l) |
| #define CHNL_E_WRONGSTATE (CHNL_EBASE + 0x1Al) |
| #define SYNC_EBASE (DSP_COMP_EBASE + 0x600l) |
| #define SYNC_E_FAIL (SYNC_EBASE + 0x00l) |
| #define SYNC_E_TIMEOUT (SYNC_EBASE + 0x01l) |
| #define DSP_ERESERVED_BASE_6 (DSP_COMP_EBASE + 0x700l) |
| #define DSP_ERESERVED_BASE_7 (DSP_COMP_EBASE + 0x800l) |
| #define DSP_EIRQNONE (DSP_COMP_EBASE + 0x900l) |
| typedef Int32 DSP_STATUS |