Go to the documentation of this file.00001
00044 #if !defined (ERRBASE_H)
00045 #define ERRBASE_H
00046
00047
00048
00049 #include <gpptypes.h>
00050
00051
00052 #if defined (__cplusplus)
00053 extern "C" {
00054 #endif
00055
00056
00057
00058 typedef Int32 DSP_STATUS ;
00059
00060
00061 #define DSP_SUCCEEDED(status) ( ((Int32) (status) >= (DSP_SBASE)) \
00062 && ((Int32) (status) <= (DSP_SLAST)))
00063
00064 #define DSP_FAILED(status) (!DSP_SUCCEEDED (status))
00065
00066
00067 #define RINGIO_SUCCEEDED(status) ( ((Int32) (status) >= (RINGIO_SBASE)) \
00068 && ((Int32) (status) <= (RINGIO_SLAST)))
00069
00070 #define RINGIO_FAILED(status) ( (!RINGIO_SUCCEEDED (status)) \
00071 && (DSP_FAILED (status)))
00072
00073
00074
00075 #define DSP_SBASE (DSP_STATUS)0x00008000l
00076 #define DSP_SLAST (DSP_STATUS)0x00008500l
00077
00078
00079 #define RINGIO_SBASE (DSP_STATUS)0x00008100l
00080 #define RINGIO_SLAST (DSP_STATUS)0x000081FFl
00081
00082
00083 #define DSP_EBASE (DSP_STATUS)0x80008000l
00084 #define DSP_ELAST (DSP_STATUS)0x800081FFl
00085
00086
00087 #define DSP_COMP_EBASE (DSP_STATUS)0x80040200l
00088 #define DSP_COMP_ELAST (DSP_STATUS)0x80047fffl
00089
00090
00091
00092
00093
00094
00095
00096
00097
00098
00099
00100
00101 #define DSP_SOK (DSP_SBASE + 0x0l)
00102
00103
00104
00105 #define DSP_SALREADYATTACHED (DSP_SBASE + 0x1l)
00106
00107
00108 #define DSP_SENUMCOMPLETE (DSP_SBASE + 0x2l)
00109
00110
00111 #define DSP_SFINALIZED (DSP_SBASE + 0x3l)
00112
00113
00114 #define DSP_SALREADYOPENED (DSP_SBASE + 0x4l)
00115
00116
00117 #define DSP_SEXISTS (DSP_SBASE + 0x5l)
00118
00119
00120 #define DSP_SFREE (DSP_SBASE + 0x6l)
00121
00122
00123
00124
00125 #define DSP_SALREADYSETUP (DSP_SBASE + 0x7l)
00126
00127
00128 #define DSP_SDESTROYED (DSP_SBASE + 0x8l)
00129
00130
00131 #define DSP_SDETACHED (DSP_SBASE + 0x9l)
00132
00133
00134 #define DSP_SALREADYLOADED (DSP_SBASE + 0xAl)
00135
00136
00137 #define DSP_SALREADYSTARTED (DSP_SBASE + 0xBl)
00138
00139
00140 #define DSP_SSTOPPED (DSP_SBASE + 0xCl)
00141
00142
00143 #define DSP_SCLOSED (DSP_SBASE + 0xDl)
00144
00145
00146
00147
00148
00149
00150
00151 #define RINGIO_SUCCESS (RINGIO_SBASE + 0x0l)
00152
00153
00154
00155
00156
00157 #define RINGIO_SPENDINGATTRIBUTE (RINGIO_SBASE + 0x1l)
00158
00159
00160
00161
00162
00163
00164
00165
00166
00167
00168
00169 #define DSP_EACCESSDENIED (DSP_EBASE + 0x0l)
00170
00171
00172 #define DSP_EALREADYCONNECTED (DSP_EBASE + 0x1l)
00173
00174
00175 #define DSP_EATTACHED (DSP_EBASE + 0x2l)
00176
00177
00178
00179
00180 #define DSP_ECHANGEDURINGENUM (DSP_EBASE + 0x3l)
00181
00182
00183 #define DSP_ECORRUPTFILE (DSP_EBASE + 0x4l)
00184
00185
00186 #define DSP_EDELETE (DSP_EBASE + 0x5l)
00187
00188
00189 #define DSP_EDIRECTION (DSP_EBASE + 0x6l)
00190
00191
00192
00193
00194
00195 #define DSP_ESTREAMFULL (DSP_EBASE + 0x7l)
00196
00197
00198 #define DSP_EFAIL (DSP_EBASE + 0x8l)
00199
00200
00201 #define DSP_EFILE (DSP_EBASE + 0x9l)
00202
00203
00204 #define DSP_EHANDLE (DSP_EBASE + 0xAl)
00205
00206
00207 #define DSP_EINVALIDARG (DSP_EBASE + 0xBl)
00208
00209
00210 #define DSP_EMEMORY (DSP_EBASE + 0xCl)
00211
00212
00213 #define DSP_ESETUP (DSP_EBASE + 0xDl)
00214
00215
00216 #define DSP_ESTARTED (DSP_EBASE + 0xEl)
00217
00218
00219 #define DSP_EINIT (DSP_EBASE + 0xFl)
00220
00221
00222 #define DSP_ENOTIMPL (DSP_EBASE + 0x10l)
00223
00224
00225 #define DSP_EPENDING (DSP_EBASE + 0x11l)
00226
00227
00228 #define DSP_EPOINTER (DSP_EBASE + 0x12l)
00229
00230
00231 #define DSP_ERANGE (DSP_EBASE + 0x13l)
00232
00233
00234 #define DSP_ESIZE (DSP_EBASE + 0x14l)
00235
00236
00237 #define DSP_ESTREAM (DSP_EBASE + 0x15l)
00238
00239
00240 #define DSP_ETASK (DSP_EBASE + 0x16l)
00241
00242
00243 #define DSP_ETIMEOUT (DSP_EBASE + 0x17l)
00244
00245
00246
00247
00248 #define DSP_ETRUNCATED (DSP_EBASE + 0x18l)
00249
00250
00251 #define DSP_EOPENED (DSP_EBASE + 0x19l)
00252
00253
00254 #define DSP_EVALUE (DSP_EBASE + 0x1Al)
00255
00256
00257
00258
00259 #define DSP_EWRONGSTATE (DSP_EBASE + 0x1Bl)
00260
00261
00262 #define DSP_EALREADYSETUP (DSP_EBASE + 0x1Cl)
00263
00264
00265 #define DSP_EINTR (DSP_EBASE + 0x1Dl)
00266
00267
00268 #define DSP_EALREADYSTARTED (DSP_EBASE + 0x1El)
00269
00270
00271 #define DSP_EALREADYOPENED (DSP_EBASE + 0x1Fl)
00272
00273
00274 #define DSP_ERESERVED_06 (DSP_EBASE + 0x20l)
00275 #define DSP_ERESERVED_07 (DSP_EBASE + 0x21l)
00276 #define DSP_ERESERVED_08 (DSP_EBASE + 0x22l)
00277 #define DSP_ERESERVED_09 (DSP_EBASE + 0x23l)
00278 #define DSP_ERESERVED_0A (DSP_EBASE + 0x24l)
00279 #define DSP_ERESERVED_0B (DSP_EBASE + 0x25l)
00280 #define DSP_ERESERVED_0C (DSP_EBASE + 0x26l)
00281 #define DSP_ERESERVED_0D (DSP_EBASE + 0x27l)
00282
00283
00284 #define DSP_ERESOURCE (DSP_EBASE + 0x28l)
00285
00286
00287 #define DSP_ERESTART (DSP_EBASE + 0x29l)
00288
00289
00290 #define DSP_EFREE (DSP_EBASE + 0x2Al)
00291
00292
00293 #define DSP_EIOFREE (DSP_EBASE + 0x2Bl)
00294
00295
00296 #define DSP_EMULINST (DSP_EBASE + 0x2Cl)
00297
00298
00299 #define DSP_ENOTFOUND (DSP_EBASE + 0x2Dl)
00300
00301
00302 #define DSP_EOUTOFIO (DSP_EBASE + 0x2El)
00303
00304
00305 #define DSP_ETRANSLATE (DSP_EBASE + 0x2fl)
00306
00307
00308 #define DSP_EVERSION (DSP_EBASE + 0x30l)
00309
00310
00311 #define DSP_EFWRITE (DSP_EBASE + 0x31l)
00312
00313
00314 #define DSP_ENOSECT (DSP_EBASE + 0x32l)
00315
00316
00317 #define DSP_ERESERVED_0F (DSP_EBASE + 0x33l)
00318 #define DSP_ERESERVED_10 (DSP_EBASE + 0x34l)
00319 #define DSP_ERESERVED_11 (DSP_EBASE + 0x35l)
00320 #define DSP_ERESERVED_12 (DSP_EBASE + 0x36l)
00321 #define DSP_ERESERVED_13 (DSP_EBASE + 0x37l)
00322 #define DSP_ERESERVED_14 (DSP_EBASE + 0x38l)
00323 #define DSP_ERESERVED_15 (DSP_EBASE + 0x39l)
00324 #define DSP_ERESERVED_16 (DSP_EBASE + 0x3Al)
00325 #define DSP_ERESERVED_17 (DSP_EBASE + 0x3Bl)
00326 #define DSP_ERESERVED_18 (DSP_EBASE + 0x3Cl)
00327 #define DSP_ERESERVED_19 (DSP_EBASE + 0x3Dl)
00328 #define DSP_ERESERVED_1A (DSP_EBASE + 0x3El)
00329 #define DSP_ERESERVED_1B (DSP_EBASE + 0x3Fl)
00330 #define DSP_ERESERVED_1C (DSP_EBASE + 0x40l)
00331 #define DSP_ERESERVED_1D (DSP_EBASE + 0x41l)
00332 #define DSP_ERESERVED_1E (DSP_EBASE + 0x42l)
00333 #define DSP_ERESERVED_1F (DSP_EBASE + 0x43l)
00334 #define DSP_ERESERVED_20 (DSP_EBASE + 0x44l)
00335 #define DSP_ERESERVED_21 (DSP_EBASE + 0x45l)
00336 #define DSP_ERESERVED_22 (DSP_EBASE + 0x46l)
00337 #define DSP_ERESERVED_23 (DSP_EBASE + 0x47l)
00338 #define DSP_ERESERVED_24 (DSP_EBASE + 0x48l)
00339 #define DSP_ERESERVED_25 (DSP_EBASE + 0x49l)
00340 #define DSP_ERESERVED_26 (DSP_EBASE + 0x4al)
00341 #define DSP_ERESERVED_27 (DSP_EBASE + 0x4bl)
00342 #define DSP_ERESERVED_28 (DSP_EBASE + 0x4cl)
00343 #define DSP_ERESERVED_29 (DSP_EBASE + 0x4dl)
00344 #define DSP_ERESERVED_2A (DSP_EBASE + 0x4el)
00345 #define DSP_ERESERVED_2B (DSP_EBASE + 0x4fl)
00346
00347
00348 #define DSP_EALREADYEXISTS (DSP_EBASE + 0x50l)
00349
00350
00351
00352
00353 #define DSP_ENOTCOMPLETE (DSP_EBASE + 0x51l)
00354
00355
00356
00357
00358
00359 #define DSP_ECONFIG (DSP_EBASE + 0x52l)
00360
00361
00362 #define DSP_ENOTSUPPORTED (DSP_EBASE + 0x53l)
00363
00364
00365 #define DSP_ENOTREADY (DSP_EBASE + 0x54l)
00366
00367
00368
00369
00370
00371
00372 #define RINGIO_EBASE (DSP_EBASE + 0x55l)
00373
00374
00375 #define RINGIO_EFAILURE (RINGIO_EBASE + 0x00l)
00376
00377
00378
00379 #define RINGIO_EBUFWRAP (RINGIO_EBASE + 0x01l)
00380
00381
00382 #define RINGIO_EBUFEMPTY (RINGIO_EBASE + 0x02l)
00383
00384
00385 #define RINGIO_EBUFFULL (RINGIO_EBASE + 0x03l)
00386
00387
00388
00389 #define RINGIO_EPENDINGDATA (RINGIO_EBASE + 0x04l)
00390
00391
00392
00393 #define RINGIO_EVARIABLEATTRIBUTE (RINGIO_EBASE + 0x05l)
00394
00395
00396 #define RINGIO_EALREADYEXISTS (RINGIO_EBASE + 0x06l)
00397
00398
00399
00400
00401 #define RINGIO_ENOTCONTIGUOUSDATA (RINGIO_EBASE + 0x07l)
00402
00403
00404 #define RINGIO_EWRONGSTATE (RINGIO_EBASE + 0x08l)
00405
00406
00407
00408 #define DSP_ERESERVED_BASE_1 (DSP_COMP_EBASE + 0x000l)
00409 #define DSP_ERESERVED_BASE_2 (DSP_COMP_EBASE + 0x100l)
00410 #define DSP_ERESERVED_BASE_3 (DSP_COMP_EBASE + 0x200l)
00411 #define DSP_ERESERVED_BASE_4 (DSP_COMP_EBASE + 0x300l)
00412 #define DSP_ERESERVED_BASE_5 (DSP_COMP_EBASE + 0x400l)
00413
00414
00415
00416
00417
00418
00419 #define CHNL_EBASE (DSP_COMP_EBASE + 0x500l)
00420
00421
00422 #define CHNL_E_MAXCHANNELS (CHNL_EBASE + 0x00l)
00423
00424
00425 #define CHNL_E_RESERVED_1 (CHNL_EBASE + 0x01l)
00426
00427
00428 #define CHNL_E_OUTOFSTREAMS (CHNL_EBASE + 0x02l)
00429
00430
00431 #define CHNL_E_BADCHANID (CHNL_EBASE + 0x03l)
00432
00433
00434 #define CHNL_E_CHANBUSY (CHNL_EBASE + 0x04l)
00435
00436
00437 #define CHNL_E_BADMODE (CHNL_EBASE + 0x05l)
00438
00439
00440
00441
00442 #define CHNL_E_NOIOC (CHNL_EBASE + 0x06l)
00443
00444
00445 #define CHNL_E_CANCELLED (CHNL_EBASE + 0x07l)
00446
00447
00448 #define CHNL_E_EOS (CHNL_EBASE + 0x09l)
00449
00450
00451 #define CHNL_E_CREATEEVENT (CHNL_EBASE + 0x0Al)
00452
00453
00454 #define CHNL_E_RESERVED_2 (CHNL_EBASE + 0x0Bl)
00455
00456
00457 #define CHNL_E_RESERVED_3 (CHNL_EBASE + 0x0Cl)
00458
00459
00460 #define CHNL_E_INVALIDWORDSIZE (CHNL_EBASE + 0x0Dl)
00461
00462
00463 #define CHNL_E_RESERVED_4 (CHNL_EBASE + 0x0El)
00464
00465
00466 #define CHNL_E_RESERVED_5 (CHNL_EBASE + 0x0Fl)
00467
00468
00469 #define CHNL_E_RESERVED_6 (CHNL_EBASE + 0x10l)
00470
00471
00472 #define CHNL_E_ISR (CHNL_EBASE + 0x11l)
00473
00474
00475 #define CHNL_E_NOIORPS (CHNL_EBASE + 0x12l)
00476
00477
00478 #define CHNL_E_BUFSIZE (CHNL_EBASE + 0x13l)
00479
00480
00481 #define CHNL_E_NOEOS (CHNL_EBASE + 0x14l)
00482
00483
00484 #define CHNL_E_WAITTIMEOUT (CHNL_EBASE + 0x15l)
00485
00486
00487 #define CHNL_E_RESERVED_7 (CHNL_EBASE + 0x16l)
00488
00489
00490 #define CHNL_E_RESERVED_8 (CHNL_EBASE + 0x17l)
00491
00492
00493 #define CHNL_E_RESERVED_9 (CHNL_EBASE + 0x18l)
00494
00495
00496 #define CHNL_E_RESERVED_10 (CHNL_EBASE + 0x19l)
00497
00498
00499 #define CHNL_E_WRONGSTATE (CHNL_EBASE + 0x1Al)
00500
00501
00502
00503
00504
00505
00506 #define SYNC_EBASE (DSP_COMP_EBASE + 0x600l)
00507
00508
00509 #define SYNC_E_FAIL (SYNC_EBASE + 0x00l)
00510
00511
00512 #define SYNC_E_TIMEOUT (SYNC_EBASE + 0x01l)
00513
00514
00515
00516 #define DSP_ERESERVED_BASE_6 (DSP_COMP_EBASE + 0x700l)
00517 #define DSP_ERESERVED_BASE_7 (DSP_COMP_EBASE + 0x800l)
00518
00519
00520
00521
00522
00523
00524
00525
00526
00527
00528 #define DSP_EIRQNONE (DSP_COMP_EBASE + 0x900l)
00529
00530
00531 #if defined (__cplusplus)
00532 }
00533 #endif
00534
00535
00536 #endif