Defines which are common to C64XX device type.
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Defines | |
#define | SHMEM_INTERFACE 0 |
Interface number for shared memory interface. ============================================================================. | |
#define | PCI_INTERFACE 1 |
Interface number for PCI interface. ============================================================================. | |
#define | VLYNQ_INTERFACE 2 |
Interface number for VLYNQ interface. ============================================================================. | |
#define | DSPLINK_BUF_ALIGN 128 |
Value of Align parameter to alloc/create calls. ============================================================================. | |
#define | DSP_MAUSIZE 1 |
Size of the DSP MAU (in bytes). ============================================================================. | |
#define | CACHE_L2_LINESIZE 128 |
Line size of DSP L2 cache (in bytes). ============================================================================. | |
#define | ADD_PADDING(padVar, count) Uint16 padVar [count] ; |
Macro to add padding to a structure. ============================================================================. | |
#define | DSPLINK_ALIGN(x, y) (Uint32)((Uint32)((x + y - 1) / y) * y) |
#define | DSPLINK_16BIT_PADDING ((CACHE_L2_LINESIZE - sizeof (Uint16)) / 2) |
Padding required for alignment of a 16-bit value (for L2 cache) in 16-bit words. ============================================================================. | |
#define | DSPLINK_32BIT_PADDING ((CACHE_L2_LINESIZE - sizeof (Uint32)) / 2) |
Padding required for alignment of a 32-bit value (for L2 cache) in 16-bit words. ============================================================================. | |
#define | DSPLINK_BOOL_PADDING ((CACHE_L2_LINESIZE - sizeof (Bool)) / 2) |
Padding required for alignment of a Boolean value (for L2 cache) in 16-bit words. ============================================================================. | |
#define | DSPLINK_PTR_PADDING ((CACHE_L2_LINESIZE - sizeof (Void *)) / 2) |
Padding required for alignment of a pointer value (for L2 cache) in 16-bit words. ============================================================================. | |
#define | DRV_CTRL_SIZE |
Padding required for DSP L2 cache line alignment within DRV control structure. ============================================================================. | |
#define | DRV_PADDING |
#define | IPS_EVENT_ENTRY_PADDING |
Padding length for IPS event entry. ============================================================================. | |
#define | IPS_CTRL_PADDING |
Padding length for IPS control structure. ============================================================================. | |
#define | DSPLINKIPS_CTRL_PADDING |
Padding length for the DSPLINKIPS shared configuration structure. ============================================================================. |
#define SHMEM_INTERFACE 0 |
Interface number for shared memory interface. ============================================================================.
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#define PCI_INTERFACE 1 |
Interface number for PCI interface. ============================================================================.
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#define VLYNQ_INTERFACE 2 |
Interface number for VLYNQ interface. ============================================================================.
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#define DSPLINK_BUF_ALIGN 128 |
Value of Align parameter to alloc/create calls. ============================================================================.
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#define DSP_MAUSIZE 1 |
Size of the DSP MAU (in bytes). ============================================================================.
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#define CACHE_L2_LINESIZE 128 |
Line size of DSP L2 cache (in bytes). ============================================================================.
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#define ADD_PADDING | ( | padVar, | |
count | |||
) | Uint16 padVar [count] ; |
Macro to add padding to a structure. ============================================================================.
============================================================================
#define DSPLINK_16BIT_PADDING ((CACHE_L2_LINESIZE - sizeof (Uint16)) / 2) |
Padding required for alignment of a 16-bit value (for L2 cache) in 16-bit words. ============================================================================.
============================================================================
#define DSPLINK_32BIT_PADDING ((CACHE_L2_LINESIZE - sizeof (Uint32)) / 2) |
Padding required for alignment of a 32-bit value (for L2 cache) in 16-bit words. ============================================================================.
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#define DSPLINK_BOOL_PADDING ((CACHE_L2_LINESIZE - sizeof (Bool)) / 2) |
Padding required for alignment of a Boolean value (for L2 cache) in 16-bit words. ============================================================================.
============================================================================
#define DSPLINK_PTR_PADDING ((CACHE_L2_LINESIZE - sizeof (Void *)) / 2) |
Padding required for alignment of a pointer value (for L2 cache) in 16-bit words. ============================================================================.
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#define DRV_CTRL_SIZE |
( (sizeof (Uint32) * 23) \ + (sizeof (Char) * DSP_MAX_STRLEN) \ + (sizeof (Uint32) * 4))
Padding required for DSP L2 cache line alignment within DRV control structure. ============================================================================.
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#define DRV_PADDING |
(( DSPLINK_ALIGN (DRV_CTRL_SIZE, \ DSPLINK_BUF_ALIGN) \ - DRV_CTRL_SIZE) / 2)
#define IPS_EVENT_ENTRY_PADDING |
( (CACHE_L2_LINESIZE \ - ((sizeof (Uint32)) * 3)) / 2)
Padding length for IPS event entry. ============================================================================.
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#define IPS_CTRL_PADDING |
( (CACHE_L2_LINESIZE \ - (sizeof (Void *) * 6)) / 2)
Padding length for IPS control structure. ============================================================================.
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#define DSPLINKIPS_CTRL_PADDING |
( (CACHE_L2_LINESIZE \ - ( sizeof (Uint32) \ + (sizeof (Uint32) * 6))) / 2)
Padding length for the DSPLINKIPS shared configuration structure. ============================================================================.
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