J721E Interrupt Management Device Descriptions¶
Introduction¶
This chapter provides information on the Interrupt Management devices in the J721E SoC. Some System Firmware TISCI messages take device specific inputs. This chapter provides information on the valid values for Interrupt Management TISCI message parameters.
Interrupt Router Device IDs¶
Some System Firmware TISCI message APIs require the Interrupt Router device ID be provided as part of the request. Based on J721E Device IDs these are the valid Interrupt Router device IDs.
| Interrupt Router Device Name | Interrupt Router Device ID |
|---|---|
| J721E_DEV_C66SS0_INTROUTER0 | 121 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 |
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 |
| J721E_DEV_NAVSS0_INTR_ROUTER_0 | 213 |
| J721E_DEV_MCU_NAVSS0_INTR_0 | 237 |
C66SS0_INTROUTER0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 0 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 1 | J721E_DEV_TIMER0 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 2 | J721E_DEV_TIMER1 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 3 | J721E_DEV_TIMER2 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 4 | J721E_DEV_TIMER3 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 5 | J721E_DEV_TIMER4 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 6 | J721E_DEV_TIMER5 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 7 | J721E_DEV_TIMER6 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 8 | J721E_DEV_TIMER7 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 9 | J721E_DEV_TIMER8 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 10 | J721E_DEV_TIMER9 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 11 | J721E_DEV_TIMER10 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 12 | J721E_DEV_TIMER11 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 13 | J721E_DEV_TIMER16 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 14 | J721E_DEV_TIMER17 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 15 | J721E_DEV_TIMER18 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 16 | J721E_DEV_TIMER19 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 17 | J721E_DEV_MCSPI3 | intr_spi | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 18 | J721E_DEV_MCSPI4 | intr_spi | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 19 | J721E_DEV_MCSPI5 | intr_spi | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 20 | J721E_DEV_MCSPI6 | intr_spi | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 21 | J721E_DEV_MCAN2 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 22 | J721E_DEV_MCAN2 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 23 | J721E_DEV_MCAN2 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 24 | J721E_DEV_MCAN3 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 25 | J721E_DEV_MCAN3 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 26 | J721E_DEV_MCAN3 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 27 | J721E_DEV_I2C3 | pointrpend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 28 | J721E_DEV_I2C4 | pointrpend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 29 | J721E_DEV_I2C5 | pointrpend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 30 | J721E_DEV_I2C6 | pointrpend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 31 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 32 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 33 | J721E_DEV_EHRPWM0 | epwm_etint | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 34 | J721E_DEV_EHRPWM1 | epwm_etint | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 35 | J721E_DEV_EHRPWM2 | epwm_etint | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 36 | J721E_DEV_EHRPWM3 | epwm_etint | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 37 | J721E_DEV_EHRPWM4 | epwm_etint | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 38 | J721E_DEV_EHRPWM5 | epwm_etint | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 39 | J721E_DEV_EHRPWM0 | epwm_tripzint | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 40 | J721E_DEV_EHRPWM1 | epwm_tripzint | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 41 | J721E_DEV_EHRPWM2 | epwm_tripzint | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 42 | J721E_DEV_EHRPWM3 | epwm_tripzint | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 43 | J721E_DEV_EHRPWM4 | epwm_tripzint | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 44 | J721E_DEV_EHRPWM5 | epwm_tripzint | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 45 | J721E_DEV_ECAP0 | ecap_int | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 46 | J721E_DEV_ECAP1 | ecap_int | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 47 | J721E_DEV_ECAP2 | ecap_int | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 48 | J721E_DEV_EQEP0 | eqep_int | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 49 | J721E_DEV_EQEP1 | eqep_int | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 50 | J721E_DEV_EQEP2 | eqep_int | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 51 | J721E_DEV_UART3 | usart_irq | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 52 | J721E_DEV_UART4 | usart_irq | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 53 | J721E_DEV_UART5 | usart_irq | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 54 | J721E_DEV_UART6 | usart_irq | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 55 | J721E_DEV_UART7 | usart_irq | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 56 | J721E_DEV_UART8 | usart_irq | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 57 | J721E_DEV_UART9 | usart_irq | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 58 | J721E_DEV_MCAN4 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 59 | J721E_DEV_MCAN4 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 60 | J721E_DEV_MCAN4 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 61 | J721E_DEV_MCAN5 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 62 | J721E_DEV_MCAN5 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 63 | J721E_DEV_MCAN5 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 64 | J721E_DEV_MCAN6 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 65 | J721E_DEV_MCAN6 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 66 | J721E_DEV_MCAN6 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 67 | J721E_DEV_MCAN7 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 68 | J721E_DEV_MCAN7 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 69 | J721E_DEV_MCAN7 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 70 | J721E_DEV_MCAN8 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 71 | J721E_DEV_MCAN8 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 72 | J721E_DEV_MCAN8 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 73 | J721E_DEV_MCAN9 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 74 | J721E_DEV_MCAN9 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 75 | J721E_DEV_MCAN9 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 76 | J721E_DEV_MCAN10 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 77 | J721E_DEV_MCAN10 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 78 | J721E_DEV_MCAN10 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 79 | J721E_DEV_MCAN11 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 80 | J721E_DEV_MCAN11 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 81 | J721E_DEV_MCAN11 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 82 | J721E_DEV_MCAN12 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 83 | J721E_DEV_MCAN12 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 84 | J721E_DEV_MCAN12 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 85 | J721E_DEV_MCAN13 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 86 | J721E_DEV_MCAN13 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 87 | J721E_DEV_MCAN13 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 88 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 89 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 90 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 91 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 92 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 93 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 94 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 95 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 96 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 (Reserved by System Firmware) | 121 | 97 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 344 |
| J721E_DEV_C66SS0_INTROUTER0 (Reserved by System Firmware) | 121 | 98 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 345 |
| J721E_DEV_C66SS0_INTROUTER0 (Reserved by System Firmware) | 121 | 99 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 346 |
| J721E_DEV_C66SS0_INTROUTER0 (Reserved by System Firmware) | 121 | 100 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 347 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 101 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 348 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 102 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 349 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 103 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 350 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 104 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 351 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 105 | J721E_DEV_DSS0 | dss_inst0_dispc_func_irq_proc0 | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 106 | J721E_DEV_DSS0 | dss_inst0_dispc_func_irq_proc1 | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 107 | J721E_DEV_DSS0 | dss_inst0_dispc_secure_irq_proc0 | 4 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 108 | J721E_DEV_DSS0 | dss_inst0_dispc_secure_irq_proc1 | 5 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 109 | J721E_DEV_DSS0 | dss_inst0_dispc_safety_error_irq_proc0 | 2 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 110 | J721E_DEV_DSS0 | dss_inst0_dispc_safety_error_irq_proc1 | 3 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 111 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 112 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 113 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 114 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 115 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 116 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 117 | J721E_DEV_CPSW0 | stat_pend | 6 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 118 | J721E_DEV_CPSW0 | mdio_pend | 5 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 119 | J721E_DEV_CPSW0 | evnt_pend | 4 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 120 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 121 | J721E_DEV_SA2_UL0 | sa_ul_pka | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 122 | J721E_DEV_SA2_UL0 | sa_ul_trng | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 123 | J721E_DEV_ESM0 | esm_int_low_lvl | 2 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 124 | J721E_DEV_ESM0 | esm_int_hi_lvl | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 125 | J721E_DEV_ESM0 | esm_int_cfg_lvl | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 126 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 127 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 128 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 40 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 129 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 41 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 130 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 42 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 131 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 43 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 132 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 44 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 133 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 45 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 134 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 46 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 135 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 47 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 136 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 48 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 137 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 49 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 138 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 50 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 139 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 51 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 140 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 52 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 141 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 53 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 142 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 54 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 143 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 55 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 144 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 56 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 145 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 57 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 146 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 58 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 147 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 59 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 148 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 60 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 149 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 61 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 150 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 62 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 151 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 63 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 152 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 4 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 153 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 5 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 154 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 6 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 155 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 7 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 156 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 8 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 157 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 9 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 158 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 10 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 159 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 11 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 160 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 4 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 161 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 5 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 162 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 6 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 163 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 7 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 164 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 8 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 165 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 9 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 166 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 10 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 167 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 11 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 168 | J721E_DEV_PRU_ICSSG0 | pr1_tx_sof_intr_req | 54 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 169 | J721E_DEV_PRU_ICSSG0 | pr1_tx_sof_intr_req | 55 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 170 | J721E_DEV_PRU_ICSSG0 | pr1_rx_sof_intr_req | 52 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 171 | J721E_DEV_PRU_ICSSG0 | pr1_rx_sof_intr_req | 53 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 172 | J721E_DEV_PRU_ICSSG1 | pr1_tx_sof_intr_req | 54 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 173 | J721E_DEV_PRU_ICSSG1 | pr1_tx_sof_intr_req | 55 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 174 | J721E_DEV_PRU_ICSSG1 | pr1_rx_sof_intr_req | 52 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 175 | J721E_DEV_PRU_ICSSG1 | pr1_rx_sof_intr_req | 53 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 176 | J721E_DEV_USB0 | irq | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 177 | J721E_DEV_USB0 | irq | 2 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 178 | J721E_DEV_USB0 | irq | 3 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 179 | J721E_DEV_USB0 | irq | 4 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 180 | J721E_DEV_USB0 | irq | 5 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 181 | J721E_DEV_USB0 | irq | 6 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 182 | J721E_DEV_USB0 | irq | 7 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 183 | J721E_DEV_USB0 | irq | 8 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 184 | J721E_DEV_USB1 | irq | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 185 | J721E_DEV_USB1 | irq | 2 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 186 | J721E_DEV_USB1 | irq | 3 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 187 | J721E_DEV_USB1 | irq | 4 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 188 | J721E_DEV_USB1 | irq | 5 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 189 | J721E_DEV_USB1 | irq | 6 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 190 | J721E_DEV_USB1 | irq | 7 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 191 | J721E_DEV_USB1 | irq | 8 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 192 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 193 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 194 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 195 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 196 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 197 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 198 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 199 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 200 | J721E_DEV_USB0 | otgirq | 9 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 201 | J721E_DEV_USB1 | otgirq | 9 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 202 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 203 | J721E_DEV_PCIE0 | pcie_legacy_pulse | 5 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 204 | J721E_DEV_PCIE0 | pcie_downstream_pulse | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 205 | J721E_DEV_PCIE0 | pcie_flr_pulse | 3 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 206 | J721E_DEV_PCIE0 | pcie_phy_level | 8 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 207 | J721E_DEV_PCIE0 | pcie_local_level | 7 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 208 | J721E_DEV_PCIE0 | pcie_error_pulse | 2 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 209 | J721E_DEV_PCIE0 | pcie_link_state_pulse | 6 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 210 | J721E_DEV_PCIE0 | pcie_pwr_state_pulse | 10 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 211 | J721E_DEV_PCIE0 | pcie_ptm_valid_pulse | 9 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 212 | J721E_DEV_PCIE0 | pcie_hot_reset_pulse | 4 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 213 | J721E_DEV_PCIE0 | pcie_cpts_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 214 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 215 | J721E_DEV_PCIE1 | pcie_legacy_pulse | 5 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 216 | J721E_DEV_PCIE1 | pcie_downstream_pulse | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 217 | J721E_DEV_PCIE1 | pcie_flr_pulse | 3 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 218 | J721E_DEV_PCIE1 | pcie_phy_level | 8 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 219 | J721E_DEV_PCIE1 | pcie_local_level | 7 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 220 | J721E_DEV_PCIE1 | pcie_error_pulse | 2 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 221 | J721E_DEV_PCIE1 | pcie_link_state_pulse | 6 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 222 | J721E_DEV_PCIE1 | pcie_pwr_state_pulse | 10 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 223 | J721E_DEV_PCIE1 | pcie_ptm_valid_pulse | 9 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 224 | J721E_DEV_PCIE1 | pcie_hot_reset_pulse | 4 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 225 | J721E_DEV_PCIE1 | pcie_cpts_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 226 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 227 | J721E_DEV_PCIE2 | pcie_legacy_pulse | 5 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 228 | J721E_DEV_PCIE2 | pcie_downstream_pulse | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 229 | J721E_DEV_PCIE2 | pcie_flr_pulse | 3 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 230 | J721E_DEV_PCIE2 | pcie_phy_level | 8 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 231 | J721E_DEV_PCIE2 | pcie_local_level | 7 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 232 | J721E_DEV_PCIE2 | pcie_error_pulse | 2 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 233 | J721E_DEV_PCIE2 | pcie_link_state_pulse | 6 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 234 | J721E_DEV_PCIE2 | pcie_pwr_state_pulse | 10 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 235 | J721E_DEV_PCIE2 | pcie_ptm_valid_pulse | 9 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 236 | J721E_DEV_PCIE2 | pcie_hot_reset_pulse | 4 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 237 | J721E_DEV_PCIE2 | pcie_cpts_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 238 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 239 | J721E_DEV_PCIE3 | pcie_legacy_pulse | 5 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 240 | J721E_DEV_PCIE3 | pcie_downstream_pulse | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 241 | J721E_DEV_PCIE3 | pcie_flr_pulse | 3 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 242 | J721E_DEV_PCIE3 | pcie_phy_level | 8 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 243 | J721E_DEV_PCIE3 | pcie_local_level | 7 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 244 | J721E_DEV_PCIE3 | pcie_error_pulse | 2 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 245 | J721E_DEV_PCIE3 | pcie_link_state_pulse | 6 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 246 | J721E_DEV_PCIE3 | pcie_pwr_state_pulse | 10 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 247 | J721E_DEV_PCIE3 | pcie_ptm_valid_pulse | 9 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 248 | J721E_DEV_PCIE3 | pcie_hot_reset_pulse | 4 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 249 | J721E_DEV_PCIE3 | pcie_cpts_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 250 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 251 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 252 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 253 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 16 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 254 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 17 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 255 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 18 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 256 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 19 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 257 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 20 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 258 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 21 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 259 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 22 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 260 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 23 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 261 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 24 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 262 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 25 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 263 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 26 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 264 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 27 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 265 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 28 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 266 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 29 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 267 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 30 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 268 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 31 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 269 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 270 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 271 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 272 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 273 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 274 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 275 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 276 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 277 | J721E_DEV_USB0 | host_system_error | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 278 | J721E_DEV_USB1 | host_system_error | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 279 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 280 | J721E_DEV_MCU_CPSW0 | stat_pend | 6 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 281 | J721E_DEV_MCU_CPSW0 | mdio_pend | 5 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 282 | J721E_DEV_MCU_CPSW0 | evnt_pend | 4 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 283 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 284 | J721E_DEV_MCU_TIMER0 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 285 | J721E_DEV_MCU_TIMER1 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 286 | J721E_DEV_MCU_TIMER2 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 287 | J721E_DEV_MCU_TIMER3 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 288 | J721E_DEV_MCU_TIMER4 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 289 | J721E_DEV_MCU_TIMER5 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 290 | J721E_DEV_MCU_TIMER6 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 291 | J721E_DEV_MCU_TIMER7 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 292 | J721E_DEV_MCU_TIMER8 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 293 | J721E_DEV_MCU_TIMER9 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 294 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 295 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 296 | J721E_DEV_MCU_ESM0 | esm_int_low_lvl | 2 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 297 | J721E_DEV_MCU_ESM0 | esm_int_hi_lvl | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 298 | J721E_DEV_MCU_ESM0 | esm_int_cfg_lvl | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 299 | J721E_DEV_WKUP_ESM0 | esm_int_low_lvl | 2 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 300 | J721E_DEV_WKUP_ESM0 | esm_int_hi_lvl | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 301 | J721E_DEV_WKUP_ESM0 | esm_int_cfg_lvl | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 302 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 303 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 304 | J721E_DEV_TIMER12 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 305 | J721E_DEV_TIMER13 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 306 | J721E_DEV_TIMER14 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 307 | J721E_DEV_TIMER15 | intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 308 | J721E_DEV_RTI24 | intr_wwd | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 309 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 310 | J721E_DEV_MCASP0 | rec_intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 311 | J721E_DEV_MCASP1 | rec_intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 312 | J721E_DEV_MCASP2 | rec_intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 313 | J721E_DEV_MCASP3 | rec_intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 314 | J721E_DEV_MCASP4 | rec_intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 315 | J721E_DEV_MCASP5 | rec_intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 316 | J721E_DEV_MCASP6 | rec_intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 317 | J721E_DEV_MCASP7 | rec_intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 318 | J721E_DEV_MCASP8 | rec_intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 319 | J721E_DEV_MCASP9 | rec_intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 320 | J721E_DEV_MCASP10 | rec_intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 321 | J721E_DEV_MCASP11 | rec_intr_pend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 322 | J721E_DEV_MCASP0 | xmit_intr_pend | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 323 | J721E_DEV_MCASP1 | xmit_intr_pend | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 324 | J721E_DEV_MCASP2 | xmit_intr_pend | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 325 | J721E_DEV_MCASP3 | xmit_intr_pend | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 326 | J721E_DEV_MCASP4 | xmit_intr_pend | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 327 | J721E_DEV_MCASP5 | xmit_intr_pend | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 328 | J721E_DEV_MCASP6 | xmit_intr_pend | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 329 | J721E_DEV_MCASP7 | xmit_intr_pend | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 330 | J721E_DEV_MCASP8 | xmit_intr_pend | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 331 | J721E_DEV_MCASP9 | xmit_intr_pend | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 332 | J721E_DEV_MCASP10 | xmit_intr_pend | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 333 | J721E_DEV_MCASP11 | xmit_intr_pend | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 334 | J721E_DEV_AASRC0 | infifo_level | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 335 | J721E_DEV_AASRC0 | ingroup_level | 2 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 336 | J721E_DEV_AASRC0 | outfifo_level | 3 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 337 | J721E_DEV_AASRC0 | outgroup_level | 4 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 338 | J721E_DEV_AASRC0 | err_level | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 339 | J721E_DEV_I3C0 | i3c__int | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 340 | J721E_DEV_MCSPI0 | intr_spi | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 341 | J721E_DEV_MCSPI1 | intr_spi | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 342 | J721E_DEV_MCSPI2 | intr_spi | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 343 | J721E_DEV_MCSPI7 | intr_spi | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 344 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 12 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 345 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 13 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 346 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 14 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 347 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 15 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 348 | J721E_DEV_I2C0 | pointrpend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 349 | J721E_DEV_I2C1 | pointrpend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 350 | J721E_DEV_I2C2 | pointrpend | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 351 | J721E_DEV_UART0 | usart_irq | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 352 | J721E_DEV_UART1 | usart_irq | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 353 | J721E_DEV_UART2 | usart_irq | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 354 | J721E_DEV_MCU_I3C0 | i3c__int | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 355 | J721E_DEV_MCU_I3C1 | i3c__int | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 356 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 357 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 358 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 320 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 359 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 321 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 360 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 322 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 361 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 323 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 362 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 324 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 363 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 325 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 364 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 326 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 365 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 327 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 366 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 328 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 367 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 329 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 368 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 330 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 369 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 331 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 370 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 332 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 371 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 333 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 372 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 334 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 373 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 335 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 374 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 336 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 375 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 337 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 376 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 338 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 377 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 339 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 378 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 340 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 379 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 341 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 380 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 342 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 381 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 343 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 382 | J721E_DEV_MCAN0 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 383 | J721E_DEV_MCAN0 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 384 | J721E_DEV_MCAN0 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 385 | J721E_DEV_MCAN1 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 386 | J721E_DEV_MCAN1 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 387 | J721E_DEV_MCAN1 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 388 | J721E_DEV_MLB0 | mlbss_mlb_ahb_int | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 389 | J721E_DEV_MLB0 | mlbss_mlb_ahb_int | 1 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 390 | J721E_DEV_MLB0 | mlbss_mlb_int | 2 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 391 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 32 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 392 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 33 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 393 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 34 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 394 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 35 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 395 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 36 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 396 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 37 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 397 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 38 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 398 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 39 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 399 | J721E_DEV_MCU_ADC12_16FFC0 | gen_level | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 400 | J721E_DEV_MCU_ADC12_16FFC1 | gen_level | 0 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 401 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 402 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 403 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 404 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 405 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 406 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 407 | Use TRM - Not managed by TISCI |
C66SS0_INTROUTER0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| J721E_DEV_C66SS0_INTROUTER0 (Reserved by System Firmware) | 121 | 0 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 4 |
| J721E_DEV_C66SS0_INTROUTER0 (Reserved by System Firmware) | 121 | 1 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 5 |
| J721E_DEV_C66SS0_INTROUTER0 (Reserved by System Firmware) | 121 | 2 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 6 |
| J721E_DEV_C66SS0_INTROUTER0 (Reserved by System Firmware) | 121 | 3 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 7 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 4 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 8 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 5 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 15 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 6 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 16 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 7 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 17 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 8 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 18 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 9 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 19 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 10 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 20 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 11 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 21 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 12 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 22 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 13 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 23 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 14 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 24 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 15 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 25 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 16 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 26 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 17 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 27 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 18 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 28 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 19 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 29 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 20 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 30 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 21 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 31 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 22 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 32 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 23 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 33 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 24 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 34 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 25 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 35 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 26 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 36 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 27 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 37 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 28 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 38 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 29 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 39 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 30 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 40 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 31 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 41 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 32 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 42 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 33 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 43 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 34 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 44 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 35 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 45 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 36 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 46 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 37 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 47 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 38 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 48 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 39 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 49 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 40 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 50 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 41 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 51 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 42 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 52 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 43 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 53 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 44 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 54 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 45 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 55 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 46 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 56 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 47 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 57 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 48 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 58 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 49 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 59 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 50 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 60 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 51 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 61 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 52 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 62 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 53 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 63 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 54 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 64 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 55 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 65 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 56 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 66 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 57 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 67 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 58 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 68 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 59 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 69 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 60 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 70 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 61 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 71 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 62 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 72 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 63 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 73 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 64 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 74 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 65 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 75 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 66 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 76 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 67 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 77 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 68 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 78 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 69 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 79 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 70 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 80 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 71 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 81 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 72 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 82 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 73 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 83 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 74 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 84 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 75 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 85 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 76 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 86 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 77 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 87 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 78 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 88 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 79 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 89 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 80 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 90 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 81 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 91 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 82 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 92 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 83 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 93 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 84 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 94 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 85 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 95 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 86 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 99 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 87 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 102 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 88 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 103 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 89 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 104 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 90 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 105 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 91 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 106 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 92 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 107 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 93 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 108 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 94 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 109 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 95 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 114 |
| J721E_DEV_C66SS0_INTROUTER0 | 121 | 96 | J721E_DEV_C66SS0_CORE0 | c66_event_in_sync | 115 |
C66SS1_INTROUTER0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 0 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 1 | J721E_DEV_TIMER0 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 2 | J721E_DEV_TIMER1 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 3 | J721E_DEV_TIMER2 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 4 | J721E_DEV_TIMER3 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 5 | J721E_DEV_TIMER4 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 6 | J721E_DEV_TIMER5 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 7 | J721E_DEV_TIMER6 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 8 | J721E_DEV_TIMER7 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 9 | J721E_DEV_TIMER8 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 10 | J721E_DEV_TIMER9 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 11 | J721E_DEV_TIMER10 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 12 | J721E_DEV_TIMER11 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 13 | J721E_DEV_TIMER16 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 14 | J721E_DEV_TIMER17 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 15 | J721E_DEV_TIMER18 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 16 | J721E_DEV_TIMER19 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 17 | J721E_DEV_MCSPI3 | intr_spi | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 18 | J721E_DEV_MCSPI4 | intr_spi | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 19 | J721E_DEV_MCSPI5 | intr_spi | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 20 | J721E_DEV_MCSPI6 | intr_spi | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 21 | J721E_DEV_MCAN2 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 22 | J721E_DEV_MCAN2 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 23 | J721E_DEV_MCAN2 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 24 | J721E_DEV_MCAN3 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 25 | J721E_DEV_MCAN3 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 26 | J721E_DEV_MCAN3 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 27 | J721E_DEV_I2C3 | pointrpend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 28 | J721E_DEV_I2C4 | pointrpend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 29 | J721E_DEV_I2C5 | pointrpend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 30 | J721E_DEV_I2C6 | pointrpend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 31 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 32 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 33 | J721E_DEV_EHRPWM0 | epwm_etint | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 34 | J721E_DEV_EHRPWM1 | epwm_etint | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 35 | J721E_DEV_EHRPWM2 | epwm_etint | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 36 | J721E_DEV_EHRPWM3 | epwm_etint | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 37 | J721E_DEV_EHRPWM4 | epwm_etint | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 38 | J721E_DEV_EHRPWM5 | epwm_etint | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 39 | J721E_DEV_EHRPWM0 | epwm_tripzint | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 40 | J721E_DEV_EHRPWM1 | epwm_tripzint | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 41 | J721E_DEV_EHRPWM2 | epwm_tripzint | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 42 | J721E_DEV_EHRPWM3 | epwm_tripzint | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 43 | J721E_DEV_EHRPWM4 | epwm_tripzint | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 44 | J721E_DEV_EHRPWM5 | epwm_tripzint | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 45 | J721E_DEV_ECAP0 | ecap_int | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 46 | J721E_DEV_ECAP1 | ecap_int | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 47 | J721E_DEV_ECAP2 | ecap_int | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 48 | J721E_DEV_EQEP0 | eqep_int | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 49 | J721E_DEV_EQEP1 | eqep_int | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 50 | J721E_DEV_EQEP2 | eqep_int | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 51 | J721E_DEV_UART3 | usart_irq | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 52 | J721E_DEV_UART4 | usart_irq | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 53 | J721E_DEV_UART5 | usart_irq | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 54 | J721E_DEV_UART6 | usart_irq | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 55 | J721E_DEV_UART7 | usart_irq | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 56 | J721E_DEV_UART8 | usart_irq | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 57 | J721E_DEV_UART9 | usart_irq | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 58 | J721E_DEV_MCAN4 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 59 | J721E_DEV_MCAN4 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 60 | J721E_DEV_MCAN4 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 61 | J721E_DEV_MCAN5 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 62 | J721E_DEV_MCAN5 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 63 | J721E_DEV_MCAN5 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 64 | J721E_DEV_MCAN6 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 65 | J721E_DEV_MCAN6 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 66 | J721E_DEV_MCAN6 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 67 | J721E_DEV_MCAN7 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 68 | J721E_DEV_MCAN7 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 69 | J721E_DEV_MCAN7 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 70 | J721E_DEV_MCAN8 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 71 | J721E_DEV_MCAN8 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 72 | J721E_DEV_MCAN8 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 73 | J721E_DEV_MCAN9 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 74 | J721E_DEV_MCAN9 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 75 | J721E_DEV_MCAN9 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 76 | J721E_DEV_MCAN10 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 77 | J721E_DEV_MCAN10 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 78 | J721E_DEV_MCAN10 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 79 | J721E_DEV_MCAN11 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 80 | J721E_DEV_MCAN11 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 81 | J721E_DEV_MCAN11 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 82 | J721E_DEV_MCAN12 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 83 | J721E_DEV_MCAN12 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 84 | J721E_DEV_MCAN12 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 85 | J721E_DEV_MCAN13 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 86 | J721E_DEV_MCAN13 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 87 | J721E_DEV_MCAN13 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 88 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 89 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 90 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 91 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 92 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 93 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 94 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 95 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 96 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 (Reserved by System Firmware) | 122 | 97 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 376 |
| J721E_DEV_C66SS1_INTROUTER0 (Reserved by System Firmware) | 122 | 98 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 377 |
| J721E_DEV_C66SS1_INTROUTER0 (Reserved by System Firmware) | 122 | 99 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 378 |
| J721E_DEV_C66SS1_INTROUTER0 (Reserved by System Firmware) | 122 | 100 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 379 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 101 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 380 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 102 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 381 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 103 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 382 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 104 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 383 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 105 | J721E_DEV_DSS0 | dss_inst0_dispc_func_irq_proc0 | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 106 | J721E_DEV_DSS0 | dss_inst0_dispc_func_irq_proc1 | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 107 | J721E_DEV_DSS0 | dss_inst0_dispc_secure_irq_proc0 | 4 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 108 | J721E_DEV_DSS0 | dss_inst0_dispc_secure_irq_proc1 | 5 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 109 | J721E_DEV_DSS0 | dss_inst0_dispc_safety_error_irq_proc0 | 2 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 110 | J721E_DEV_DSS0 | dss_inst0_dispc_safety_error_irq_proc1 | 3 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 111 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 112 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 113 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 114 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 115 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 116 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 117 | J721E_DEV_CPSW0 | stat_pend | 6 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 118 | J721E_DEV_CPSW0 | mdio_pend | 5 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 119 | J721E_DEV_CPSW0 | evnt_pend | 4 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 120 | J721E_DEV_SA2_UL0 | sa_ul_pka | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 121 | J721E_DEV_SA2_UL0 | sa_ul_trng | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 122 | J721E_DEV_ESM0 | esm_int_low_lvl | 2 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 123 | J721E_DEV_ESM0 | esm_int_hi_lvl | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 124 | J721E_DEV_ESM0 | esm_int_cfg_lvl | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 125 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 126 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 127 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 128 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 40 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 129 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 41 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 130 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 42 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 131 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 43 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 132 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 44 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 133 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 45 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 134 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 46 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 135 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 47 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 136 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 48 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 137 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 49 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 138 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 50 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 139 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 51 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 140 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 52 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 141 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 53 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 142 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 54 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 143 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 55 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 144 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 56 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 145 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 57 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 146 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 58 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 147 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 59 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 148 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 60 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 149 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 61 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 150 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 62 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 151 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 63 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 152 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 4 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 153 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 5 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 154 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 6 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 155 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 7 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 156 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 8 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 157 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 9 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 158 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 10 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 159 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 11 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 160 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 4 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 161 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 5 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 162 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 6 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 163 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 7 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 164 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 8 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 165 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 9 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 166 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 10 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 167 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 11 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 168 | J721E_DEV_PRU_ICSSG0 | pr1_tx_sof_intr_req | 54 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 169 | J721E_DEV_PRU_ICSSG0 | pr1_tx_sof_intr_req | 55 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 170 | J721E_DEV_PRU_ICSSG0 | pr1_rx_sof_intr_req | 52 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 171 | J721E_DEV_PRU_ICSSG0 | pr1_rx_sof_intr_req | 53 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 172 | J721E_DEV_PRU_ICSSG1 | pr1_tx_sof_intr_req | 54 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 173 | J721E_DEV_PRU_ICSSG1 | pr1_tx_sof_intr_req | 55 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 174 | J721E_DEV_PRU_ICSSG1 | pr1_rx_sof_intr_req | 52 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 175 | J721E_DEV_PRU_ICSSG1 | pr1_rx_sof_intr_req | 53 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 176 | J721E_DEV_USB0 | irq | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 177 | J721E_DEV_USB0 | irq | 2 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 178 | J721E_DEV_USB0 | irq | 3 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 179 | J721E_DEV_USB0 | irq | 4 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 180 | J721E_DEV_USB0 | irq | 5 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 181 | J721E_DEV_USB0 | irq | 6 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 182 | J721E_DEV_USB0 | irq | 7 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 183 | J721E_DEV_USB0 | irq | 8 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 184 | J721E_DEV_USB1 | irq | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 185 | J721E_DEV_USB1 | irq | 2 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 186 | J721E_DEV_USB1 | irq | 3 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 187 | J721E_DEV_USB1 | irq | 4 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 188 | J721E_DEV_USB1 | irq | 5 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 189 | J721E_DEV_USB1 | irq | 6 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 190 | J721E_DEV_USB1 | irq | 7 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 191 | J721E_DEV_USB1 | irq | 8 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 192 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 193 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 194 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 195 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 196 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 197 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 198 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 199 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 200 | J721E_DEV_USB0 | otgirq | 9 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 201 | J721E_DEV_USB1 | otgirq | 9 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 202 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 203 | J721E_DEV_PCIE0 | pcie_legacy_pulse | 5 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 204 | J721E_DEV_PCIE0 | pcie_downstream_pulse | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 205 | J721E_DEV_PCIE0 | pcie_flr_pulse | 3 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 206 | J721E_DEV_PCIE0 | pcie_phy_level | 8 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 207 | J721E_DEV_PCIE0 | pcie_local_level | 7 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 208 | J721E_DEV_PCIE0 | pcie_error_pulse | 2 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 209 | J721E_DEV_PCIE0 | pcie_link_state_pulse | 6 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 210 | J721E_DEV_PCIE0 | pcie_pwr_state_pulse | 10 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 211 | J721E_DEV_PCIE0 | pcie_ptm_valid_pulse | 9 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 212 | J721E_DEV_PCIE0 | pcie_hot_reset_pulse | 4 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 213 | J721E_DEV_PCIE0 | pcie_cpts_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 214 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 215 | J721E_DEV_PCIE1 | pcie_legacy_pulse | 5 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 216 | J721E_DEV_PCIE1 | pcie_downstream_pulse | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 217 | J721E_DEV_PCIE1 | pcie_flr_pulse | 3 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 218 | J721E_DEV_PCIE1 | pcie_phy_level | 8 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 219 | J721E_DEV_PCIE1 | pcie_local_level | 7 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 220 | J721E_DEV_PCIE1 | pcie_error_pulse | 2 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 221 | J721E_DEV_PCIE1 | pcie_link_state_pulse | 6 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 222 | J721E_DEV_PCIE1 | pcie_pwr_state_pulse | 10 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 223 | J721E_DEV_PCIE1 | pcie_ptm_valid_pulse | 9 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 224 | J721E_DEV_PCIE1 | pcie_hot_reset_pulse | 4 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 225 | J721E_DEV_PCIE1 | pcie_cpts_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 226 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 227 | J721E_DEV_PCIE2 | pcie_legacy_pulse | 5 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 228 | J721E_DEV_PCIE2 | pcie_downstream_pulse | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 229 | J721E_DEV_PCIE2 | pcie_flr_pulse | 3 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 230 | J721E_DEV_PCIE2 | pcie_phy_level | 8 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 231 | J721E_DEV_PCIE2 | pcie_local_level | 7 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 232 | J721E_DEV_PCIE2 | pcie_error_pulse | 2 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 233 | J721E_DEV_PCIE2 | pcie_link_state_pulse | 6 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 234 | J721E_DEV_PCIE2 | pcie_pwr_state_pulse | 10 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 235 | J721E_DEV_PCIE2 | pcie_ptm_valid_pulse | 9 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 236 | J721E_DEV_PCIE2 | pcie_hot_reset_pulse | 4 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 237 | J721E_DEV_PCIE2 | pcie_cpts_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 238 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 239 | J721E_DEV_PCIE3 | pcie_legacy_pulse | 5 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 240 | J721E_DEV_PCIE3 | pcie_downstream_pulse | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 241 | J721E_DEV_PCIE3 | pcie_flr_pulse | 3 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 242 | J721E_DEV_PCIE3 | pcie_phy_level | 8 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 243 | J721E_DEV_PCIE3 | pcie_local_level | 7 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 244 | J721E_DEV_PCIE3 | pcie_error_pulse | 2 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 245 | J721E_DEV_PCIE3 | pcie_link_state_pulse | 6 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 246 | J721E_DEV_PCIE3 | pcie_pwr_state_pulse | 10 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 247 | J721E_DEV_PCIE3 | pcie_ptm_valid_pulse | 9 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 248 | J721E_DEV_PCIE3 | pcie_hot_reset_pulse | 4 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 249 | J721E_DEV_PCIE3 | pcie_cpts_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 250 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 251 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 252 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 253 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 16 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 254 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 17 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 255 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 18 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 256 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 19 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 257 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 20 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 258 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 21 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 259 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 22 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 260 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 23 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 261 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 24 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 262 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 25 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 263 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 26 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 264 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 27 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 265 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 28 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 266 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 29 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 267 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 30 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 268 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 31 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 269 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 270 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 271 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 272 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 273 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 274 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 275 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 276 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 277 | J721E_DEV_USB0 | host_system_error | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 278 | J721E_DEV_USB1 | host_system_error | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 279 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 280 | J721E_DEV_MCU_CPSW0 | stat_pend | 6 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 281 | J721E_DEV_MCU_CPSW0 | mdio_pend | 5 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 282 | J721E_DEV_MCU_CPSW0 | evnt_pend | 4 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 283 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 284 | J721E_DEV_MCU_TIMER0 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 285 | J721E_DEV_MCU_TIMER1 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 286 | J721E_DEV_MCU_TIMER2 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 287 | J721E_DEV_MCU_TIMER3 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 288 | J721E_DEV_MCU_TIMER4 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 289 | J721E_DEV_MCU_TIMER5 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 290 | J721E_DEV_MCU_TIMER6 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 291 | J721E_DEV_MCU_TIMER7 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 292 | J721E_DEV_MCU_TIMER8 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 293 | J721E_DEV_MCU_TIMER9 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 294 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 295 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 296 | J721E_DEV_MCU_ESM0 | esm_int_low_lvl | 2 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 297 | J721E_DEV_MCU_ESM0 | esm_int_hi_lvl | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 298 | J721E_DEV_MCU_ESM0 | esm_int_cfg_lvl | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 299 | J721E_DEV_WKUP_ESM0 | esm_int_low_lvl | 2 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 300 | J721E_DEV_WKUP_ESM0 | esm_int_hi_lvl | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 301 | J721E_DEV_WKUP_ESM0 | esm_int_cfg_lvl | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 302 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 303 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 304 | J721E_DEV_TIMER12 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 305 | J721E_DEV_TIMER13 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 306 | J721E_DEV_TIMER14 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 307 | J721E_DEV_TIMER15 | intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 308 | J721E_DEV_RTI25 | intr_wwd | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 309 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 310 | J721E_DEV_MCASP0 | rec_intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 311 | J721E_DEV_MCASP1 | rec_intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 312 | J721E_DEV_MCASP2 | rec_intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 313 | J721E_DEV_MCASP3 | rec_intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 314 | J721E_DEV_MCASP4 | rec_intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 315 | J721E_DEV_MCASP5 | rec_intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 316 | J721E_DEV_MCASP6 | rec_intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 317 | J721E_DEV_MCASP7 | rec_intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 318 | J721E_DEV_MCASP8 | rec_intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 319 | J721E_DEV_MCASP9 | rec_intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 320 | J721E_DEV_MCASP10 | rec_intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 321 | J721E_DEV_MCASP11 | rec_intr_pend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 322 | J721E_DEV_MCASP0 | xmit_intr_pend | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 323 | J721E_DEV_MCASP1 | xmit_intr_pend | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 324 | J721E_DEV_MCASP2 | xmit_intr_pend | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 325 | J721E_DEV_MCASP3 | xmit_intr_pend | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 326 | J721E_DEV_MCASP4 | xmit_intr_pend | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 327 | J721E_DEV_MCASP5 | xmit_intr_pend | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 328 | J721E_DEV_MCASP6 | xmit_intr_pend | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 329 | J721E_DEV_MCASP7 | xmit_intr_pend | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 330 | J721E_DEV_MCASP8 | xmit_intr_pend | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 331 | J721E_DEV_MCASP9 | xmit_intr_pend | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 332 | J721E_DEV_MCASP10 | xmit_intr_pend | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 333 | J721E_DEV_MCASP11 | xmit_intr_pend | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 334 | J721E_DEV_AASRC0 | infifo_level | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 335 | J721E_DEV_AASRC0 | ingroup_level | 2 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 336 | J721E_DEV_AASRC0 | outfifo_level | 3 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 337 | J721E_DEV_AASRC0 | outgroup_level | 4 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 338 | J721E_DEV_AASRC0 | err_level | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 339 | J721E_DEV_I3C0 | i3c__int | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 340 | J721E_DEV_MCSPI0 | intr_spi | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 341 | J721E_DEV_MCSPI1 | intr_spi | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 342 | J721E_DEV_MCSPI2 | intr_spi | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 343 | J721E_DEV_MCSPI7 | intr_spi | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 344 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 12 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 345 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 13 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 346 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 14 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 347 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 15 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 348 | J721E_DEV_I2C0 | pointrpend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 349 | J721E_DEV_I2C1 | pointrpend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 350 | J721E_DEV_I2C2 | pointrpend | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 351 | J721E_DEV_UART0 | usart_irq | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 352 | J721E_DEV_UART1 | usart_irq | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 353 | J721E_DEV_UART2 | usart_irq | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 354 | J721E_DEV_MCU_I3C0 | i3c__int | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 355 | J721E_DEV_MCU_I3C1 | i3c__int | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 356 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 357 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 358 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 352 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 359 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 353 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 360 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 354 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 361 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 355 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 362 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 356 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 363 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 357 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 364 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 358 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 365 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 359 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 366 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 360 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 367 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 361 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 368 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 362 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 369 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 363 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 370 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 364 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 371 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 365 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 372 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 366 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 373 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 367 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 374 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 368 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 375 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 369 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 376 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 370 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 377 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 371 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 378 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 372 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 379 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 373 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 380 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 374 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 381 | J721E_DEV_NAVSS0_INTR_ROUTER_0 | outl_intr | 375 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 382 | J721E_DEV_MCAN0 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 383 | J721E_DEV_MCAN0 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 384 | J721E_DEV_MCAN0 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 385 | J721E_DEV_MCAN1 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 386 | J721E_DEV_MCAN1 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 387 | J721E_DEV_MCAN1 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 388 | J721E_DEV_MLB0 | mlbss_mlb_ahb_int | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 389 | J721E_DEV_MLB0 | mlbss_mlb_ahb_int | 1 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 390 | J721E_DEV_MLB0 | mlbss_mlb_int | 2 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 391 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 32 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 392 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 33 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 393 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 34 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 394 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 35 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 395 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 36 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 396 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 37 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 397 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 38 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 398 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 39 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 399 | J721E_DEV_MCU_ADC12_16FFC0 | gen_level | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 400 | J721E_DEV_MCU_ADC12_16FFC1 | gen_level | 0 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 401 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 402 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 403 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 404 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 405 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 406 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 407 | Use TRM - Not managed by TISCI |
C66SS1_INTROUTER0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| J721E_DEV_C66SS1_INTROUTER0 (Reserved by System Firmware) | 122 | 0 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 4 |
| J721E_DEV_C66SS1_INTROUTER0 (Reserved by System Firmware) | 122 | 1 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 5 |
| J721E_DEV_C66SS1_INTROUTER0 (Reserved by System Firmware) | 122 | 2 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 6 |
| J721E_DEV_C66SS1_INTROUTER0 (Reserved by System Firmware) | 122 | 3 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 7 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 4 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 8 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 5 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 15 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 6 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 16 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 7 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 17 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 8 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 18 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 9 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 19 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 10 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 20 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 11 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 21 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 12 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 22 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 13 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 23 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 14 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 24 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 15 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 25 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 16 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 26 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 17 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 27 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 18 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 28 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 19 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 29 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 20 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 30 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 21 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 31 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 22 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 32 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 23 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 33 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 24 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 34 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 25 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 35 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 26 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 36 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 27 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 37 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 28 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 38 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 29 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 39 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 30 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 40 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 31 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 41 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 32 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 42 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 33 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 43 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 34 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 44 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 35 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 45 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 36 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 46 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 37 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 47 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 38 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 48 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 39 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 49 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 40 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 50 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 41 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 51 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 42 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 52 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 43 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 53 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 44 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 54 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 45 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 55 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 46 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 56 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 47 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 57 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 48 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 58 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 49 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 59 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 50 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 60 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 51 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 61 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 52 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 62 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 53 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 63 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 54 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 64 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 55 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 65 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 56 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 66 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 57 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 67 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 58 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 68 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 59 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 69 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 60 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 70 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 61 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 71 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 62 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 72 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 63 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 73 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 64 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 74 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 65 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 75 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 66 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 76 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 67 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 77 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 68 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 78 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 69 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 79 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 70 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 80 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 71 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 81 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 72 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 82 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 73 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 83 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 74 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 84 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 75 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 85 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 76 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 86 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 77 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 87 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 78 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 88 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 79 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 89 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 80 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 90 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 81 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 91 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 82 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 92 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 83 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 93 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 84 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 94 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 85 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 95 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 86 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 99 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 87 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 102 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 88 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 103 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 89 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 104 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 90 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 105 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 91 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 106 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 92 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 107 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 93 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 108 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 94 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 109 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 95 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 114 |
| J721E_DEV_C66SS1_INTROUTER0 | 122 | 96 | J721E_DEV_C66SS1_CORE0 | c66_event_in_sync | 115 |
CMPEVENT_INTRTR0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 0 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 1 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 2 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 3 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 4 | J721E_DEV_PCIE0 | pcie_cpts_comp | 11 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 5 | J721E_DEV_PCIE1 | pcie_cpts_comp | 11 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 6 | J721E_DEV_PCIE2 | pcie_cpts_comp | 11 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 7 | J721E_DEV_PCIE3 | pcie_cpts_comp | 11 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 8 | J721E_DEV_NAVSS0 | cpts0_comp | 0 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 9 | J721E_DEV_CPSW0 | cpts_comp | 0 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 10 | J721E_DEV_MCU_CPSW0 | cpts_comp | 0 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 11 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 12 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 13 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 14 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 15 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 16 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_req | 12 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 17 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_req | 13 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 18 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_req | 14 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 19 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_req | 15 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 20 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_req | 16 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 21 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_req | 17 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 22 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_req | 18 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 23 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_req | 19 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 24 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_req | 12 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 25 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_req | 13 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 26 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_req | 14 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 27 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_req | 15 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 28 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_req | 16 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 29 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_req | 17 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 30 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_req | 18 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 31 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_req | 19 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 32 | J721E_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 20 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 33 | J721E_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 21 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 34 | J721E_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 22 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 35 | J721E_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 23 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 36 | J721E_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 24 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 37 | J721E_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 25 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 38 | J721E_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 26 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 39 | J721E_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 27 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 40 | J721E_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 28 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 41 | J721E_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 29 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 42 | J721E_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 30 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 43 | J721E_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 31 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 44 | J721E_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 32 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 45 | J721E_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 33 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 46 | J721E_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 34 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 47 | J721E_DEV_PRU_ICSSG0 | pr1_iep0_cmp_intr_req | 35 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 48 | J721E_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 36 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 49 | J721E_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 37 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 50 | J721E_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 38 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 51 | J721E_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 39 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 52 | J721E_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 40 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 53 | J721E_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 41 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 54 | J721E_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 42 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 55 | J721E_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 43 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 56 | J721E_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 44 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 57 | J721E_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 45 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 58 | J721E_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 46 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 59 | J721E_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 47 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 60 | J721E_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 48 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 61 | J721E_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 49 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 62 | J721E_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 50 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 63 | J721E_DEV_PRU_ICSSG0 | pr1_iep1_cmp_intr_req | 51 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 64 | J721E_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 20 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 65 | J721E_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 21 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 66 | J721E_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 22 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 67 | J721E_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 23 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 68 | J721E_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 24 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 69 | J721E_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 25 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 70 | J721E_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 26 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 71 | J721E_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 27 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 72 | J721E_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 28 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 73 | J721E_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 29 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 74 | J721E_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 30 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 75 | J721E_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 31 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 76 | J721E_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 32 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 77 | J721E_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 33 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 78 | J721E_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 34 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 79 | J721E_DEV_PRU_ICSSG1 | pr1_iep0_cmp_intr_req | 35 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 80 | J721E_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 36 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 81 | J721E_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 37 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 82 | J721E_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 38 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 83 | J721E_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 39 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 84 | J721E_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 40 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 85 | J721E_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 41 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 86 | J721E_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 42 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 87 | J721E_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 43 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 88 | J721E_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 44 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 89 | J721E_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 45 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 90 | J721E_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 46 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 91 | J721E_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 47 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 92 | J721E_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 48 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 93 | J721E_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 49 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 94 | J721E_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 50 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 95 | J721E_DEV_PRU_ICSSG1 | pr1_iep1_cmp_intr_req | 51 |
CMPEVENT_INTRTR0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 0 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 544 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 544 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 0 | J721E_DEV_R5FSS0_INTROUTER0 | in | 288 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 288 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 1 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 545 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 545 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 1 | J721E_DEV_R5FSS0_INTROUTER0 | in | 289 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 289 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 2 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 546 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 546 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 2 | J721E_DEV_R5FSS0_INTROUTER0 | in | 290 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 290 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 3 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 547 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 547 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 3 | J721E_DEV_R5FSS0_INTROUTER0 | in | 291 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 291 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 4 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 548 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 548 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 4 | J721E_DEV_R5FSS0_INTROUTER0 | in | 292 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 292 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 5 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 549 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 549 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 5 | J721E_DEV_R5FSS0_INTROUTER0 | in | 293 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 293 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 6 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 550 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 550 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 6 | J721E_DEV_R5FSS0_INTROUTER0 | in | 294 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 294 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 7 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 551 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 551 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 7 | J721E_DEV_R5FSS0_INTROUTER0 | in | 295 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 295 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 8 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 552 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 552 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 8 | J721E_DEV_R5FSS0_INTROUTER0 | in | 296 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 296 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 9 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 553 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 553 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 9 | J721E_DEV_R5FSS0_INTROUTER0 | in | 297 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 297 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 10 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 554 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 554 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 10 | J721E_DEV_R5FSS0_INTROUTER0 | in | 298 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 298 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 11 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 555 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 555 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 11 | J721E_DEV_R5FSS0_INTROUTER0 | in | 299 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 299 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 12 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 556 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 556 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 12 | J721E_DEV_C66SS0_INTROUTER0 | in | 344 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 344 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 12 | J721E_DEV_R5FSS0_INTROUTER0 | in | 300 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 300 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 13 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 557 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 557 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 13 | J721E_DEV_C66SS0_INTROUTER0 | in | 345 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 345 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 13 | J721E_DEV_R5FSS0_INTROUTER0 | in | 301 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 301 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 14 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 558 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 558 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 14 | J721E_DEV_C66SS0_INTROUTER0 | in | 346 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 346 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 14 | J721E_DEV_R5FSS0_INTROUTER0 | in | 302 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 302 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 15 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 559 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 559 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 15 | J721E_DEV_C66SS0_INTROUTER0 | in | 347 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 347 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 15 | J721E_DEV_R5FSS0_INTROUTER0 | in | 303 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 303 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 16 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 96 |
| J721E_DEV_R5FSS0_INTROUTER0 | in | 100 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 16 | J721E_DEV_R5FSS1_INTROUTER0 | in | 100 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 17 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 97 |
| J721E_DEV_R5FSS0_INTROUTER0 | in | 101 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 17 | J721E_DEV_R5FSS1_INTROUTER0 | in | 101 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 18 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 98 |
| J721E_DEV_R5FSS0_INTROUTER0 | in | 102 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 18 | J721E_DEV_R5FSS1_INTROUTER0 | in | 102 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 19 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 99 |
| J721E_DEV_R5FSS0_INTROUTER0 | in | 103 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 19 | J721E_DEV_R5FSS1_INTROUTER0 | in | 103 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 20 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 100 |
| J721E_DEV_R5FSS0_INTROUTER0 | in | 104 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 20 | J721E_DEV_R5FSS1_INTROUTER0 | in | 104 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 21 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 101 |
| J721E_DEV_R5FSS0_INTROUTER0 | in | 105 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 21 | J721E_DEV_R5FSS1_INTROUTER0 | in | 105 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 22 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 102 |
| J721E_DEV_R5FSS0_INTROUTER0 | in | 106 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 22 | J721E_DEV_R5FSS1_INTROUTER0 | in | 106 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 23 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 103 |
| J721E_DEV_R5FSS0_INTROUTER0 | in | 107 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 23 | J721E_DEV_R5FSS1_INTROUTER0 | in | 107 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 24 | J721E_DEV_R5FSS0_INTROUTER0 | in | 108 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 108 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 24 | J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 60 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 25 | J721E_DEV_R5FSS0_INTROUTER0 | in | 109 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 109 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 25 | J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 61 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 26 | J721E_DEV_R5FSS0_INTROUTER0 | in | 110 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 110 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 26 | J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 62 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 27 | J721E_DEV_R5FSS0_INTROUTER0 | in | 111 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 111 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 27 | J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 63 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 28 | J721E_DEV_R5FSS0_INTROUTER0 | in | 112 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 112 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 28 | J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 64 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 29 | J721E_DEV_R5FSS0_INTROUTER0 | in | 113 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 113 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 29 | J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 65 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 30 | J721E_DEV_R5FSS0_INTROUTER0 | in | 114 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 114 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 30 | J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 66 |
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 31 | J721E_DEV_R5FSS0_INTROUTER0 | in | 115 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 115 | |||
| J721E_DEV_CMPEVENT_INTRTR0 | 123 | 31 | J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 67 |
MAIN2MCU_LVL_INTRTR0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 0 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 1 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 2 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 3 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 4 | J721E_DEV_SA2_UL0 | sa_ul_trng | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 5 | J721E_DEV_SA2_UL0 | sa_ul_pka | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 6 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 7 | J721E_DEV_ELM0 | elm_porocpsinterrupt_lvl | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 8 | J721E_DEV_GPMC0 | gpmc_sinterrupt | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 9 | J721E_DEV_DDR0 | ddrss_pll_freq_change_req | 2 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 10 | J721E_DEV_DDR0 | ddrss_controller | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 11 | J721E_DEV_DDR0 | ddrss_v2a_other_err_lvl | 3 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 12 | J721E_DEV_DDR0 | ddrss_hs_phy_global_error | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 13 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 14 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 15 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 16 | J721E_DEV_MCAN0 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 17 | J721E_DEV_MCAN0 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 18 | J721E_DEV_MCAN0 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 19 | J721E_DEV_MCAN1 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 20 | J721E_DEV_MCAN1 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 21 | J721E_DEV_MCAN1 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 22 | J721E_DEV_MCAN2 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 23 | J721E_DEV_MCAN2 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 24 | J721E_DEV_MCAN2 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 25 | J721E_DEV_MCAN3 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 26 | J721E_DEV_MCAN3 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 27 | J721E_DEV_MCAN3 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 28 | J721E_DEV_MMCSD0 | emmcss_intr | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 29 | J721E_DEV_MMCSD1 | emmcsdss_intr | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 30 | J721E_DEV_MMCSD2 | emmcsdss_intr | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 31 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 32 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 4 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 33 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 5 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 34 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 6 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 35 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 7 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 36 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 8 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 37 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 9 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 38 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 10 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 39 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 11 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 40 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 4 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 41 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 5 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 42 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 6 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 43 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 7 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 44 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 8 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 45 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 9 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 46 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 10 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 47 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 11 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 48 | J721E_DEV_MCSPI0 | intr_spi | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 49 | J721E_DEV_MCSPI1 | intr_spi | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 50 | J721E_DEV_MCSPI2 | intr_spi | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 51 | J721E_DEV_MCSPI3 | intr_spi | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 52 | J721E_DEV_MCSPI4 | intr_spi | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 53 | J721E_DEV_MCSPI5 | intr_spi | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 54 | J721E_DEV_MCSPI6 | intr_spi | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 55 | J721E_DEV_MCSPI7 | intr_spi | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 56 | J721E_DEV_I2C0 | pointrpend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 57 | J721E_DEV_I2C1 | pointrpend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 58 | J721E_DEV_I2C2 | pointrpend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 59 | J721E_DEV_I2C3 | pointrpend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 60 | J721E_DEV_I2C4 | pointrpend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 61 | J721E_DEV_I2C5 | pointrpend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 62 | J721E_DEV_I2C6 | pointrpend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 63 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 64 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 65 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 66 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 67 | J721E_DEV_PCIE0 | pcie_phy_level | 8 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 68 | J721E_DEV_PCIE0 | pcie_local_level | 7 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 69 | J721E_DEV_PCIE0 | pcie_cpts_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 70 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 71 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 72 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 73 | J721E_DEV_PCIE1 | pcie_phy_level | 8 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 74 | J721E_DEV_PCIE1 | pcie_local_level | 7 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 75 | J721E_DEV_PCIE1 | pcie_cpts_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 76 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 77 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 78 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 79 | J721E_DEV_PCIE2 | pcie_phy_level | 8 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 80 | J721E_DEV_PCIE2 | pcie_local_level | 7 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 81 | J721E_DEV_PCIE2 | pcie_cpts_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 82 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 83 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 84 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 85 | J721E_DEV_PCIE3 | pcie_phy_level | 8 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 86 | J721E_DEV_PCIE3 | pcie_local_level | 7 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 87 | J721E_DEV_PCIE3 | pcie_cpts_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 88 | J721E_DEV_DCC0 | intr_done_level | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 89 | J721E_DEV_DCC1 | intr_done_level | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 90 | J721E_DEV_DCC2 | intr_done_level | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 91 | J721E_DEV_DCC3 | intr_done_level | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 92 | J721E_DEV_DCC4 | intr_done_level | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 93 | J721E_DEV_DCC5 | intr_done_level | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 94 | J721E_DEV_DCC6 | intr_done_level | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 95 | J721E_DEV_DCC7 | intr_done_level | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 96 | J721E_DEV_UART0 | usart_irq | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 97 | J721E_DEV_UART1 | usart_irq | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 98 | J721E_DEV_UART2 | usart_irq | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 99 | J721E_DEV_UART3 | usart_irq | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 100 | J721E_DEV_UART4 | usart_irq | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 101 | J721E_DEV_UART5 | usart_irq | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 102 | J721E_DEV_UART6 | usart_irq | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 103 | J721E_DEV_UART7 | usart_irq | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 104 | J721E_DEV_UART8 | usart_irq | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 105 | J721E_DEV_UART9 | usart_irq | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 106 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 107 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 108 | J721E_DEV_TIMER0 | intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 109 | J721E_DEV_TIMER1 | intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 110 | J721E_DEV_TIMER2 | intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 111 | J721E_DEV_TIMER3 | intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 112 | J721E_DEV_TIMER4 | intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 113 | J721E_DEV_TIMER5 | intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 114 | J721E_DEV_TIMER6 | intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 115 | J721E_DEV_TIMER7 | intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 116 | J721E_DEV_TIMER8 | intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 117 | J721E_DEV_TIMER9 | intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 118 | J721E_DEV_TIMER10 | intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 119 | J721E_DEV_TIMER11 | intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 120 | J721E_DEV_TIMER12 | intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 121 | J721E_DEV_TIMER13 | intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 122 | J721E_DEV_TIMER14 | intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 123 | J721E_DEV_TIMER15 | intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 124 | J721E_DEV_TIMER16 | intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 125 | J721E_DEV_TIMER17 | intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 126 | J721E_DEV_TIMER18 | intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 127 | J721E_DEV_TIMER19 | intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 128 | J721E_DEV_USB0 | irq | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 129 | J721E_DEV_USB0 | irq | 2 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 130 | J721E_DEV_USB0 | irq | 3 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 131 | J721E_DEV_USB0 | irq | 4 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 132 | J721E_DEV_USB0 | irq | 5 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 133 | J721E_DEV_USB0 | irq | 6 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 134 | J721E_DEV_USB0 | irq | 7 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 135 | J721E_DEV_USB0 | irq | 8 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 136 | J721E_DEV_USB1 | irq | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 137 | J721E_DEV_USB1 | irq | 2 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 138 | J721E_DEV_USB1 | irq | 3 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 139 | J721E_DEV_USB1 | irq | 4 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 140 | J721E_DEV_USB1 | irq | 5 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 141 | J721E_DEV_USB1 | irq | 6 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 142 | J721E_DEV_USB1 | irq | 7 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 143 | J721E_DEV_USB1 | irq | 8 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 144 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 145 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 146 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 147 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 148 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 149 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 150 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 151 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 152 | J721E_DEV_USB0 | otgirq | 9 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 153 | J721E_DEV_USB1 | otgirq | 9 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 154 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 155 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 156 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 157 | J721E_DEV_USB0 | host_system_error | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 158 | J721E_DEV_USB1 | host_system_error | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 159 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 160 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 161 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 162 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 163 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 164 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 165 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 166 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 167 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 168 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 169 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 170 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 171 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 172 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 173 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 174 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 175 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 176 | J721E_DEV_MCASP0 | xmit_intr_pend | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 177 | J721E_DEV_MCASP0 | rec_intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 178 | J721E_DEV_MCASP1 | xmit_intr_pend | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 179 | J721E_DEV_MCASP1 | rec_intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 180 | J721E_DEV_MCASP2 | xmit_intr_pend | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 181 | J721E_DEV_MCASP2 | rec_intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 182 | J721E_DEV_MCASP3 | xmit_intr_pend | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 183 | J721E_DEV_MCASP3 | rec_intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 184 | J721E_DEV_MCASP4 | xmit_intr_pend | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 185 | J721E_DEV_MCASP4 | rec_intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 186 | J721E_DEV_MCASP5 | xmit_intr_pend | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 187 | J721E_DEV_MCASP5 | rec_intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 188 | J721E_DEV_MCASP6 | xmit_intr_pend | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 189 | J721E_DEV_MCASP6 | rec_intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 190 | J721E_DEV_MCASP7 | xmit_intr_pend | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 191 | J721E_DEV_MCASP7 | rec_intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 192 | J721E_DEV_MCASP8 | xmit_intr_pend | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 193 | J721E_DEV_MCASP8 | rec_intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 194 | J721E_DEV_MCASP9 | xmit_intr_pend | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 195 | J721E_DEV_MCASP9 | rec_intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 196 | J721E_DEV_MCASP10 | xmit_intr_pend | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 197 | J721E_DEV_MCASP10 | rec_intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 198 | J721E_DEV_MCASP11 | xmit_intr_pend | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 199 | J721E_DEV_MCASP11 | rec_intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 200 | J721E_DEV_AASRC0 | infifo_level | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 201 | J721E_DEV_AASRC0 | ingroup_level | 2 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 202 | J721E_DEV_AASRC0 | outfifo_level | 3 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 203 | J721E_DEV_AASRC0 | outgroup_level | 4 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 204 | J721E_DEV_AASRC0 | err_level | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 205 | J721E_DEV_MLB0 | mlbss_mlb_int | 2 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 206 | J721E_DEV_MLB0 | mlbss_mlb_ahb_int | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 207 | J721E_DEV_MLB0 | mlbss_mlb_ahb_int | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 208 | J721E_DEV_DCC8 | intr_done_level | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 209 | J721E_DEV_DCC9 | intr_done_level | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 210 | J721E_DEV_DCC10 | intr_done_level | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 211 | J721E_DEV_DCC11 | intr_done_level | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 212 | J721E_DEV_DCC12 | intr_done_level | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 213 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 214 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 215 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 216 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 217 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 218 | J721E_DEV_UFS0 | ufs_intr | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 219 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 220 | J721E_DEV_I3C0 | i3c__int | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 221 | J721E_DEV_CPSW0 | stat_pend | 6 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 222 | J721E_DEV_CPSW0 | mdio_pend | 5 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 223 | J721E_DEV_CPSW0 | evnt_pend | 4 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 224 | J721E_DEV_DSS_DSI0 | dsi_0_func_intr | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 225 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 226 | J721E_DEV_DSS0 | dss_inst0_dispc_func_irq_proc0 | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 227 | J721E_DEV_DSS0 | dss_inst0_dispc_func_irq_proc1 | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 228 | J721E_DEV_DSS0 | dss_inst0_dispc_secure_irq_proc0 | 4 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 229 | J721E_DEV_DSS0 | dss_inst0_dispc_secure_irq_proc1 | 5 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 230 | J721E_DEV_DSS0 | dss_inst0_dispc_safety_error_irq_proc0 | 2 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 231 | J721E_DEV_DSS0 | dss_inst0_dispc_safety_error_irq_proc1 | 3 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 232 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 233 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 234 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 235 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 236 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 237 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 238 | J721E_DEV_DSS_EDP0 | intr | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 239 | J721E_DEV_DSS_EDP0 | intr | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 240 | J721E_DEV_DSS_EDP0 | intr | 2 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 241 | J721E_DEV_DSS_EDP0 | intr | 3 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 242 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 243 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 244 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 245 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 246 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 247 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 248 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 249 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 250 | J721E_DEV_CSI_TX_IF0 | csi_interrupt | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 251 | J721E_DEV_CSI_TX_IF0 | csi_level | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 252 | J721E_DEV_DECODER0 | irq | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 253 | J721E_DEV_ENCODER0 | irq | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 254 | J721E_DEV_CSI_RX_IF0 | csi_irq | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 255 | J721E_DEV_CSI_RX_IF0 | csi_err_irq | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 256 | J721E_DEV_CSI_RX_IF0 | csi_level | 2 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 257 | J721E_DEV_CSI_RX_IF1 | csi_irq | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 258 | J721E_DEV_CSI_RX_IF1 | csi_err_irq | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 259 | J721E_DEV_CSI_RX_IF1 | csi_level | 2 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 260 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 261 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 262 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 263 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 264 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 265 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 266 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 267 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 268 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 269 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 270 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 271 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 272 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 273 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 274 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 275 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 276 | J721E_DEV_VPFE0 | ccdc_intr_pend | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 277 | J721E_DEV_VPFE0 | rat_exp_intr | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 278 | J721E_DEV_MCAN4 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 279 | J721E_DEV_MCAN4 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 280 | J721E_DEV_MCAN4 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 281 | J721E_DEV_MCAN5 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 282 | J721E_DEV_MCAN5 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 283 | J721E_DEV_MCAN5 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 284 | J721E_DEV_MCAN6 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 285 | J721E_DEV_MCAN6 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 286 | J721E_DEV_MCAN6 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 287 | J721E_DEV_MCAN7 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 288 | J721E_DEV_MCAN7 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 289 | J721E_DEV_MCAN7 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 290 | J721E_DEV_MCAN8 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 291 | J721E_DEV_MCAN8 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 292 | J721E_DEV_MCAN8 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 293 | J721E_DEV_MCAN9 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 294 | J721E_DEV_MCAN9 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 295 | J721E_DEV_MCAN9 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 296 | J721E_DEV_MCAN10 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 297 | J721E_DEV_MCAN10 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 298 | J721E_DEV_MCAN10 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 299 | J721E_DEV_MCAN11 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 300 | J721E_DEV_MCAN11 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 301 | J721E_DEV_MCAN11 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 302 | J721E_DEV_MCAN12 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 303 | J721E_DEV_MCAN12 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 304 | J721E_DEV_MCAN12 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 305 | J721E_DEV_MCAN13 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 306 | J721E_DEV_MCAN13 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 307 | J721E_DEV_MCAN13 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 308 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 309 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 310 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 311 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 312 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 313 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 314 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 315 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 316 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 317 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 318 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 319 | Use TRM - Not managed by TISCI |
MAIN2MCU_LVL_INTRTR0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 0 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 160 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 160 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 1 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 161 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 161 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 2 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 162 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 162 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 3 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 163 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 163 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 4 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 164 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 164 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 5 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 165 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 165 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 6 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 166 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 166 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 7 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 167 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 167 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 8 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 168 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 168 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 9 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 169 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 169 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 10 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 170 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 170 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 11 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 171 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 171 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 12 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 172 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 172 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 13 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 173 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 173 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 14 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 174 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 174 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 15 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 175 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 175 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 16 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 176 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 176 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 17 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 177 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 177 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 18 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 178 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 178 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 19 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 179 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 179 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 20 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 180 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 180 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 21 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 181 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 181 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 22 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 182 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 182 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 23 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 183 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 183 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 24 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 184 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 184 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 25 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 185 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 185 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 26 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 186 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 186 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 27 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 187 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 187 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 28 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 188 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 188 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 29 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 189 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 189 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 30 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 190 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 190 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 31 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 191 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 191 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 32 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 192 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 192 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 33 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 193 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 193 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 34 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 194 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 194 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 35 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 195 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 195 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 36 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 196 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 196 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 37 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 197 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 197 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 38 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 198 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 198 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 39 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 199 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 199 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 40 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 200 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 200 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 41 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 201 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 201 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 42 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 202 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 202 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 43 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 203 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 203 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 44 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 204 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 204 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 45 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 205 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 205 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 46 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 206 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 206 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 47 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 207 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 207 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 48 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 208 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 208 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 49 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 209 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 209 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 50 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 210 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 210 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 51 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 211 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 211 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 52 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 212 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 212 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 53 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 213 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 213 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 54 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 214 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 214 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 55 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 215 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 215 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 56 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 216 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 216 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 57 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 217 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 217 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 58 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 218 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 218 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 59 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 219 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 219 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 60 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 220 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 220 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 61 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 221 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 221 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 62 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 222 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 222 | |||
| J721E_DEV_MAIN2MCU_LVL_INTRTR0 | 128 | 63 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 223 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 223 |
MAIN2MCU_PLS_INTRTR0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 0 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 1 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 2 | J721E_DEV_EHRPWM0 | epwm_etint | 0 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 3 | J721E_DEV_EHRPWM1 | epwm_etint | 0 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 4 | J721E_DEV_EHRPWM2 | epwm_etint | 0 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 5 | J721E_DEV_EHRPWM3 | epwm_etint | 0 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 6 | J721E_DEV_EHRPWM4 | epwm_etint | 0 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 7 | J721E_DEV_EHRPWM5 | epwm_etint | 0 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 8 | J721E_DEV_EHRPWM0 | epwm_tripzint | 1 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 9 | J721E_DEV_EHRPWM1 | epwm_tripzint | 1 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 10 | J721E_DEV_EHRPWM2 | epwm_tripzint | 1 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 11 | J721E_DEV_EHRPWM3 | epwm_tripzint | 1 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 12 | J721E_DEV_EHRPWM4 | epwm_tripzint | 1 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 13 | J721E_DEV_EHRPWM5 | epwm_tripzint | 1 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 14 | J721E_DEV_EQEP0 | eqep_int | 0 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 15 | J721E_DEV_EQEP1 | eqep_int | 0 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 16 | J721E_DEV_EQEP2 | eqep_int | 0 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 17 | J721E_DEV_ECAP0 | ecap_int | 0 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 18 | J721E_DEV_ECAP1 | ecap_int | 0 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 19 | J721E_DEV_ECAP2 | ecap_int | 0 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 20 | J721E_DEV_PRU_ICSSG0 | pr1_tx_sof_intr_req | 54 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 21 | J721E_DEV_PRU_ICSSG0 | pr1_tx_sof_intr_req | 55 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 22 | J721E_DEV_PRU_ICSSG0 | pr1_rx_sof_intr_req | 52 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 23 | J721E_DEV_PRU_ICSSG0 | pr1_rx_sof_intr_req | 53 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 24 | J721E_DEV_PRU_ICSSG1 | pr1_tx_sof_intr_req | 54 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 25 | J721E_DEV_PRU_ICSSG1 | pr1_tx_sof_intr_req | 55 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 26 | J721E_DEV_PRU_ICSSG1 | pr1_rx_sof_intr_req | 52 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 27 | J721E_DEV_PRU_ICSSG1 | pr1_rx_sof_intr_req | 53 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 28 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 29 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 30 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 31 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 32 | J721E_DEV_PCIE0 | pcie_legacy_pulse | 5 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 33 | J721E_DEV_PCIE0 | pcie_downstream_pulse | 1 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 34 | J721E_DEV_PCIE0 | pcie_flr_pulse | 3 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 35 | J721E_DEV_PCIE0 | pcie_error_pulse | 2 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 36 | J721E_DEV_PCIE0 | pcie_link_state_pulse | 6 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 37 | J721E_DEV_PCIE0 | pcie_pwr_state_pulse | 10 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 38 | J721E_DEV_PCIE0 | pcie_ptm_valid_pulse | 9 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 39 | J721E_DEV_PCIE0 | pcie_hot_reset_pulse | 4 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 40 | J721E_DEV_PCIE1 | pcie_legacy_pulse | 5 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 41 | J721E_DEV_PCIE1 | pcie_downstream_pulse | 1 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 42 | J721E_DEV_PCIE1 | pcie_flr_pulse | 3 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 43 | J721E_DEV_PCIE1 | pcie_error_pulse | 2 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 44 | J721E_DEV_PCIE1 | pcie_link_state_pulse | 6 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 45 | J721E_DEV_PCIE1 | pcie_pwr_state_pulse | 10 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 46 | J721E_DEV_PCIE1 | pcie_ptm_valid_pulse | 9 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 47 | J721E_DEV_PCIE1 | pcie_hot_reset_pulse | 4 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 48 | J721E_DEV_PCIE2 | pcie_legacy_pulse | 5 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 49 | J721E_DEV_PCIE2 | pcie_downstream_pulse | 1 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 50 | J721E_DEV_PCIE2 | pcie_flr_pulse | 3 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 51 | J721E_DEV_PCIE2 | pcie_error_pulse | 2 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 52 | J721E_DEV_PCIE2 | pcie_link_state_pulse | 6 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 53 | J721E_DEV_PCIE2 | pcie_pwr_state_pulse | 10 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 54 | J721E_DEV_PCIE2 | pcie_ptm_valid_pulse | 9 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 55 | J721E_DEV_PCIE2 | pcie_hot_reset_pulse | 4 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 56 | J721E_DEV_PCIE3 | pcie_legacy_pulse | 5 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 57 | J721E_DEV_PCIE3 | pcie_downstream_pulse | 1 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 58 | J721E_DEV_PCIE3 | pcie_flr_pulse | 3 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 59 | J721E_DEV_PCIE3 | pcie_error_pulse | 2 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 60 | J721E_DEV_PCIE3 | pcie_link_state_pulse | 6 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 61 | J721E_DEV_PCIE3 | pcie_pwr_state_pulse | 10 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 62 | J721E_DEV_PCIE3 | pcie_ptm_valid_pulse | 9 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 63 | J721E_DEV_PCIE3 | pcie_hot_reset_pulse | 4 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 64 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 0 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 65 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 1 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 66 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 2 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 67 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 3 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 68 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 4 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 69 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 5 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 70 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 6 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 71 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 7 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 72 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 8 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 73 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 9 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 74 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 10 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 75 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 11 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 76 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 12 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 77 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 13 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 78 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 14 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 79 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 15 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 80 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 16 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 81 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 17 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 82 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 18 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 83 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 19 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 84 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 20 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 85 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 21 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 86 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 22 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 87 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 23 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 88 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 24 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 89 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 25 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 90 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 26 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 91 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 27 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 92 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 28 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 93 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 29 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 94 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 30 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 95 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 31 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 96 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 16 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 97 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 17 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 98 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 18 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 99 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 19 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 100 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 20 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 101 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 21 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 102 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 22 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 103 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 23 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 104 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 105 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 106 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 107 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 108 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 109 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 110 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 111 | Use TRM - Not managed by TISCI |
MAIN2MCU_PLS_INTRTR0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 0 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 224 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 224 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 1 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 225 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 225 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 2 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 226 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 226 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 3 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 227 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 227 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 4 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 228 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 228 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 5 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 229 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 229 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 6 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 230 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 230 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 7 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 231 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 231 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 8 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 232 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 232 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 9 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 233 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 233 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 10 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 234 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 234 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 11 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 235 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 235 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 12 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 236 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 236 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 13 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 237 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 237 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 14 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 238 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 238 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 15 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 239 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 239 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 16 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 240 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 240 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 17 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 241 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 241 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 18 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 242 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 242 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 19 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 243 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 243 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 20 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 244 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 244 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 21 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 245 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 245 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 22 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 246 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 246 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 23 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 247 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 247 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 24 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 248 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 248 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 25 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 249 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 249 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 26 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 250 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 250 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 27 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 251 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 251 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 28 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 252 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 252 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 29 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 253 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 253 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 30 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 254 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 254 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 31 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 255 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 255 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 32 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 256 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 256 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 33 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 257 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 257 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 34 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 258 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 258 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 35 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 259 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 259 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 36 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 260 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 260 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 37 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 261 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 261 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 38 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 262 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 262 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 39 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 263 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 263 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 40 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 264 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 264 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 41 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 265 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 265 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 42 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 266 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 266 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 43 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 267 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 267 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 44 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 268 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 268 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 45 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 269 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 269 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 46 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 270 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 270 | |||
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | 130 | 47 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 271 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 271 |
GPIOMUX_INTRTR0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 0 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 1 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 2 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 3 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 4 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 5 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 6 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 7 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 8 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 9 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 10 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 11 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 12 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 13 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 14 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 15 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 16 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 17 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 18 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 19 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 20 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 21 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 22 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 23 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 24 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 25 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 26 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 27 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 28 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 29 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 30 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 31 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 32 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 33 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 34 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 35 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 36 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 37 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 38 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 39 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 40 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 41 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 42 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 43 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 44 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 45 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 46 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 47 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 48 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 49 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 50 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 51 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 52 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 53 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 54 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 55 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 56 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 57 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 58 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 59 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 60 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 61 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 62 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 63 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 64 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 65 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 66 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 67 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 68 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 69 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 70 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 71 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 72 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 73 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 74 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 75 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 76 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 77 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 78 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 79 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 80 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 81 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 82 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 83 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 84 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 85 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 86 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 87 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 88 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 89 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 90 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 91 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 92 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 93 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 94 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 95 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 96 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 97 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 98 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 99 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 100 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 101 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 102 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 103 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 104 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 105 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 106 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 107 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 108 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 109 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 110 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 111 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 112 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 113 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 114 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 115 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 116 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 117 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 118 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 119 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 120 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 121 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 122 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 123 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 124 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 125 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 126 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 127 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 128 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 129 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 130 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 131 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 132 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 133 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 134 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 135 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 136 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 137 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 138 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 139 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 140 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 141 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 142 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 143 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 144 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 145 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 146 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 147 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 148 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 149 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 150 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 151 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 152 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 153 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 154 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 155 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 156 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 157 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 158 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 159 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 160 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 161 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 162 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 163 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 164 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 165 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 166 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 167 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 168 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 169 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 170 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 171 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 172 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 173 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 174 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 175 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 176 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 177 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 178 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 179 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 180 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 181 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 182 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 183 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 184 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 185 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 186 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 187 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 188 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 189 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 190 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 191 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 192 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 193 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 194 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 195 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 196 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 197 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 198 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 199 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 200 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 201 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 202 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 203 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 204 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 205 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 206 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 207 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 208 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 209 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 210 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 211 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 212 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 213 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 214 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 215 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 216 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 217 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 218 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 219 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 220 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 221 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 222 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 223 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 224 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 225 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 226 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 227 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 228 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 229 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 230 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 231 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 232 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 233 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 234 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 235 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 236 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 237 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 238 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 239 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 240 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 241 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 242 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 243 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 244 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 245 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 246 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 247 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 248 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 249 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 250 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 251 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 252 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 253 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 254 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 255 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 256 | J721E_DEV_GPIO0 | gpio_bank | 0 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 257 | J721E_DEV_GPIO0 | gpio_bank | 1 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 258 | J721E_DEV_GPIO0 | gpio_bank | 2 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 259 | J721E_DEV_GPIO0 | gpio_bank | 3 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 260 | J721E_DEV_GPIO0 | gpio_bank | 4 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 261 | J721E_DEV_GPIO0 | gpio_bank | 5 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 262 | J721E_DEV_GPIO0 | gpio_bank | 6 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 263 | J721E_DEV_GPIO0 | gpio_bank | 7 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 264 | J721E_DEV_GPIO2 | gpio_bank | 0 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 265 | J721E_DEV_GPIO2 | gpio_bank | 1 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 266 | J721E_DEV_GPIO2 | gpio_bank | 2 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 267 | J721E_DEV_GPIO2 | gpio_bank | 3 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 268 | J721E_DEV_GPIO2 | gpio_bank | 4 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 269 | J721E_DEV_GPIO2 | gpio_bank | 5 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 270 | J721E_DEV_GPIO2 | gpio_bank | 6 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 271 | J721E_DEV_GPIO2 | gpio_bank | 7 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 272 | J721E_DEV_GPIO4 | gpio_bank | 0 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 273 | J721E_DEV_GPIO4 | gpio_bank | 1 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 274 | J721E_DEV_GPIO4 | gpio_bank | 2 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 275 | J721E_DEV_GPIO4 | gpio_bank | 3 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 276 | J721E_DEV_GPIO4 | gpio_bank | 4 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 277 | J721E_DEV_GPIO4 | gpio_bank | 5 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 278 | J721E_DEV_GPIO4 | gpio_bank | 6 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 279 | J721E_DEV_GPIO4 | gpio_bank | 7 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 280 | J721E_DEV_GPIO6 | gpio_bank | 0 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 281 | J721E_DEV_GPIO6 | gpio_bank | 1 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 282 | J721E_DEV_GPIO6 | gpio_bank | 2 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 283 | J721E_DEV_GPIO6 | gpio_bank | 3 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 284 | J721E_DEV_GPIO6 | gpio_bank | 4 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 285 | J721E_DEV_GPIO6 | gpio_bank | 5 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 286 | J721E_DEV_GPIO6 | gpio_bank | 6 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 287 | J721E_DEV_GPIO6 | gpio_bank | 7 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 288 | J721E_DEV_GPIO1 | gpio_bank | 0 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 289 | J721E_DEV_GPIO1 | gpio_bank | 1 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 290 | J721E_DEV_GPIO1 | gpio_bank | 2 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 291 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 292 | J721E_DEV_GPIO3 | gpio_bank | 0 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 293 | J721E_DEV_GPIO3 | gpio_bank | 1 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 294 | J721E_DEV_GPIO3 | gpio_bank | 2 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 295 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 296 | J721E_DEV_GPIO5 | gpio_bank | 0 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 297 | J721E_DEV_GPIO5 | gpio_bank | 1 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 298 | J721E_DEV_GPIO5 | gpio_bank | 2 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 299 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 300 | J721E_DEV_GPIO7 | gpio_bank | 0 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 301 | J721E_DEV_GPIO7 | gpio_bank | 1 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 302 | J721E_DEV_GPIO7 | gpio_bank | 2 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 303 | Use TRM - Not managed by TISCI |
GPIOMUX_INTRTR0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 0 | J721E_DEV_ESM0 | esm_pls_event0 | 632 |
| J721E_DEV_ESM0 | esm_pls_event1 | 640 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 0 | J721E_DEV_ESM0 | esm_pls_event2 | 648 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 64 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 0 | J721E_DEV_R5FSS0_INTROUTER0 | in | 68 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 68 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 1 | J721E_DEV_ESM0 | esm_pls_event0 | 633 |
| J721E_DEV_ESM0 | esm_pls_event1 | 641 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 1 | J721E_DEV_ESM0 | esm_pls_event2 | 649 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 65 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 1 | J721E_DEV_R5FSS0_INTROUTER0 | in | 69 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 69 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 2 | J721E_DEV_ESM0 | esm_pls_event0 | 634 |
| J721E_DEV_ESM0 | esm_pls_event1 | 642 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 2 | J721E_DEV_ESM0 | esm_pls_event2 | 650 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 66 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 2 | J721E_DEV_R5FSS0_INTROUTER0 | in | 70 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 70 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 3 | J721E_DEV_ESM0 | esm_pls_event0 | 635 |
| J721E_DEV_ESM0 | esm_pls_event1 | 643 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 3 | J721E_DEV_ESM0 | esm_pls_event2 | 651 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 67 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 3 | J721E_DEV_R5FSS0_INTROUTER0 | in | 71 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 71 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 4 | J721E_DEV_ESM0 | esm_pls_event0 | 636 |
| J721E_DEV_ESM0 | esm_pls_event1 | 644 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 4 | J721E_DEV_ESM0 | esm_pls_event2 | 652 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 68 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 4 | J721E_DEV_R5FSS0_INTROUTER0 | in | 72 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 72 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 5 | J721E_DEV_ESM0 | esm_pls_event0 | 637 |
| J721E_DEV_ESM0 | esm_pls_event1 | 645 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 5 | J721E_DEV_ESM0 | esm_pls_event2 | 653 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 69 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 5 | J721E_DEV_R5FSS0_INTROUTER0 | in | 73 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 73 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 6 | J721E_DEV_ESM0 | esm_pls_event0 | 638 |
| J721E_DEV_ESM0 | esm_pls_event1 | 646 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 6 | J721E_DEV_ESM0 | esm_pls_event2 | 654 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 70 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 6 | J721E_DEV_R5FSS0_INTROUTER0 | in | 74 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 74 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 7 | J721E_DEV_ESM0 | esm_pls_event0 | 639 |
| J721E_DEV_ESM0 | esm_pls_event1 | 647 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 7 | J721E_DEV_ESM0 | esm_pls_event2 | 655 |
| J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 71 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 7 | J721E_DEV_R5FSS0_INTROUTER0 | in | 75 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 75 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 8 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 392 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 392 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 8 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 72 |
| J721E_DEV_R5FSS0_INTROUTER0 | in | 76 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 8 | J721E_DEV_R5FSS1_INTROUTER0 | in | 76 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 9 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 393 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 393 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 9 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 73 |
| J721E_DEV_R5FSS0_INTROUTER0 | in | 77 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 9 | J721E_DEV_R5FSS1_INTROUTER0 | in | 77 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 10 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 394 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 394 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 10 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 74 |
| J721E_DEV_R5FSS0_INTROUTER0 | in | 78 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 10 | J721E_DEV_R5FSS1_INTROUTER0 | in | 78 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 11 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 395 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 395 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 11 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 75 |
| J721E_DEV_R5FSS0_INTROUTER0 | in | 79 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 11 | J721E_DEV_R5FSS1_INTROUTER0 | in | 79 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 12 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 396 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 396 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 12 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 76 |
| J721E_DEV_R5FSS0_INTROUTER0 | in | 80 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 12 | J721E_DEV_R5FSS1_INTROUTER0 | in | 80 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 13 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 397 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 397 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 13 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 77 |
| J721E_DEV_R5FSS0_INTROUTER0 | in | 81 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 13 | J721E_DEV_R5FSS1_INTROUTER0 | in | 81 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 14 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 398 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 398 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 14 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 78 |
| J721E_DEV_R5FSS0_INTROUTER0 | in | 82 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 14 | J721E_DEV_R5FSS1_INTROUTER0 | in | 82 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 15 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 399 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 399 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 15 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 79 |
| J721E_DEV_R5FSS0_INTROUTER0 | in | 83 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 15 | J721E_DEV_R5FSS1_INTROUTER0 | in | 83 |
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 16 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 400 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 400 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 16 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 80 |
| J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 68 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 16 | J721E_DEV_R5FSS0_CORE0 | intr | 176 |
| J721E_DEV_R5FSS0_CORE1 | intr | 176 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 16 | J721E_DEV_R5FSS1_CORE0 | intr | 176 |
| J721E_DEV_R5FSS1_CORE1 | intr | 176 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 17 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 401 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 401 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 17 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 81 |
| J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 69 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 17 | J721E_DEV_R5FSS0_CORE0 | intr | 177 |
| J721E_DEV_R5FSS0_CORE1 | intr | 177 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 17 | J721E_DEV_R5FSS1_CORE0 | intr | 177 |
| J721E_DEV_R5FSS1_CORE1 | intr | 177 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 18 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 402 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 402 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 18 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 82 |
| J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 70 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 18 | J721E_DEV_R5FSS0_CORE0 | intr | 178 |
| J721E_DEV_R5FSS0_CORE1 | intr | 178 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 18 | J721E_DEV_R5FSS1_CORE0 | intr | 178 |
| J721E_DEV_R5FSS1_CORE1 | intr | 178 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 19 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 403 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 403 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 19 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 83 |
| J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 71 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 19 | J721E_DEV_R5FSS0_CORE0 | intr | 179 |
| J721E_DEV_R5FSS0_CORE1 | intr | 179 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 19 | J721E_DEV_R5FSS1_CORE0 | intr | 179 |
| J721E_DEV_R5FSS1_CORE1 | intr | 179 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 20 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 404 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 404 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 20 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 84 |
| J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 72 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 20 | J721E_DEV_R5FSS0_CORE0 | intr | 180 |
| J721E_DEV_R5FSS0_CORE1 | intr | 180 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 20 | J721E_DEV_R5FSS1_CORE0 | intr | 180 |
| J721E_DEV_R5FSS1_CORE1 | intr | 180 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 21 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 405 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 405 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 21 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 85 |
| J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 73 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 21 | J721E_DEV_R5FSS0_CORE0 | intr | 181 |
| J721E_DEV_R5FSS0_CORE1 | intr | 181 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 21 | J721E_DEV_R5FSS1_CORE0 | intr | 181 |
| J721E_DEV_R5FSS1_CORE1 | intr | 181 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 22 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 406 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 406 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 22 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 86 |
| J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 74 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 22 | J721E_DEV_R5FSS0_CORE0 | intr | 182 |
| J721E_DEV_R5FSS0_CORE1 | intr | 182 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 22 | J721E_DEV_R5FSS1_CORE0 | intr | 182 |
| J721E_DEV_R5FSS1_CORE1 | intr | 182 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 23 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 407 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 407 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 23 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 87 |
| J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 75 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 23 | J721E_DEV_R5FSS0_CORE0 | intr | 183 |
| J721E_DEV_R5FSS0_CORE1 | intr | 183 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 23 | J721E_DEV_R5FSS1_CORE0 | intr | 183 |
| J721E_DEV_R5FSS1_CORE1 | intr | 183 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 24 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 408 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 408 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 24 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 88 |
| J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 76 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 24 | J721E_DEV_R5FSS0_CORE0 | intr | 184 |
| J721E_DEV_R5FSS0_CORE1 | intr | 184 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 24 | J721E_DEV_R5FSS1_CORE0 | intr | 184 |
| J721E_DEV_R5FSS1_CORE1 | intr | 184 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 25 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 409 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 409 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 25 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 89 |
| J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 77 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 25 | J721E_DEV_R5FSS0_CORE0 | intr | 185 |
| J721E_DEV_R5FSS0_CORE1 | intr | 185 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 25 | J721E_DEV_R5FSS1_CORE0 | intr | 185 |
| J721E_DEV_R5FSS1_CORE1 | intr | 185 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 26 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 410 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 410 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 26 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 90 |
| J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 78 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 26 | J721E_DEV_R5FSS0_CORE0 | intr | 186 |
| J721E_DEV_R5FSS0_CORE1 | intr | 186 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 26 | J721E_DEV_R5FSS1_CORE0 | intr | 186 |
| J721E_DEV_R5FSS1_CORE1 | intr | 186 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 27 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 411 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 411 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 27 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 91 |
| J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 79 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 27 | J721E_DEV_R5FSS0_CORE0 | intr | 187 |
| J721E_DEV_R5FSS0_CORE1 | intr | 187 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 27 | J721E_DEV_R5FSS1_CORE0 | intr | 187 |
| J721E_DEV_R5FSS1_CORE1 | intr | 187 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 28 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 412 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 412 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 28 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 92 |
| J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 80 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 28 | J721E_DEV_R5FSS0_CORE0 | intr | 188 |
| J721E_DEV_R5FSS0_CORE1 | intr | 188 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 28 | J721E_DEV_R5FSS1_CORE0 | intr | 188 |
| J721E_DEV_R5FSS1_CORE1 | intr | 188 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 29 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 413 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 413 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 29 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 93 |
| J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 81 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 29 | J721E_DEV_R5FSS0_CORE0 | intr | 189 |
| J721E_DEV_R5FSS0_CORE1 | intr | 189 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 29 | J721E_DEV_R5FSS1_CORE0 | intr | 189 |
| J721E_DEV_R5FSS1_CORE1 | intr | 189 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 30 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 414 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 414 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 30 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 94 |
| J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 82 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 30 | J721E_DEV_R5FSS0_CORE0 | intr | 190 |
| J721E_DEV_R5FSS0_CORE1 | intr | 190 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 30 | J721E_DEV_R5FSS1_CORE0 | intr | 190 |
| J721E_DEV_R5FSS1_CORE1 | intr | 190 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 31 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 415 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 415 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 31 | J721E_DEV_MAIN2MCU_PLS_INTRTR0 | in | 95 |
| J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 83 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 31 | J721E_DEV_R5FSS0_CORE0 | intr | 191 |
| J721E_DEV_R5FSS0_CORE1 | intr | 191 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 31 | J721E_DEV_R5FSS1_CORE0 | intr | 191 |
| J721E_DEV_R5FSS1_CORE1 | intr | 191 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 32 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 416 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 416 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 32 | J721E_DEV_C66SS0_INTROUTER0 | in | 391 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 391 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 33 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 417 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 417 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 33 | J721E_DEV_C66SS0_INTROUTER0 | in | 392 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 392 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 34 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 418 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 418 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 34 | J721E_DEV_C66SS0_INTROUTER0 | in | 393 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 393 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 35 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 419 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 419 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 35 | J721E_DEV_C66SS0_INTROUTER0 | in | 394 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 394 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 36 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 420 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 420 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 36 | J721E_DEV_C66SS0_INTROUTER0 | in | 395 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 395 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 37 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 421 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 421 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 37 | J721E_DEV_C66SS0_INTROUTER0 | in | 396 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 396 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 38 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 422 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 422 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 38 | J721E_DEV_C66SS0_INTROUTER0 | in | 397 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 397 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 39 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 423 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 423 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 39 | J721E_DEV_C66SS0_INTROUTER0 | in | 398 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 398 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 40 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 424 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 424 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 40 | J721E_DEV_C66SS0_INTROUTER0 | in | 128 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 128 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 41 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 425 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 425 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 41 | J721E_DEV_C66SS0_INTROUTER0 | in | 129 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 129 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 42 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 426 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 426 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 42 | J721E_DEV_C66SS0_INTROUTER0 | in | 130 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 130 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 43 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 427 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 427 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 43 | J721E_DEV_C66SS0_INTROUTER0 | in | 131 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 131 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 44 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 428 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 428 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 44 | J721E_DEV_C66SS0_INTROUTER0 | in | 132 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 132 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 45 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 429 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 429 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 45 | J721E_DEV_C66SS0_INTROUTER0 | in | 133 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 133 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 46 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 430 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 430 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 46 | J721E_DEV_C66SS0_INTROUTER0 | in | 134 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 134 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 47 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 431 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 431 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 47 | J721E_DEV_C66SS0_INTROUTER0 | in | 135 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 135 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 48 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 432 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 432 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 48 | J721E_DEV_C66SS0_INTROUTER0 | in | 136 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 136 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 49 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 433 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 433 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 49 | J721E_DEV_C66SS0_INTROUTER0 | in | 137 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 137 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 50 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 434 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 434 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 50 | J721E_DEV_C66SS0_INTROUTER0 | in | 138 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 138 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 51 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 435 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 435 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 51 | J721E_DEV_C66SS0_INTROUTER0 | in | 139 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 139 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 52 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 436 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 436 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 52 | J721E_DEV_PRU_ICSSG0 | pr1_iep0_cap_intr_req | 4 |
| J721E_DEV_PRU_ICSSG1 | pr1_iep0_cap_intr_req | 4 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 52 | J721E_DEV_C66SS0_INTROUTER0 | in | 140 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 140 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 53 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 437 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 437 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 53 | J721E_DEV_PRU_ICSSG0 | pr1_iep0_cap_intr_req | 5 |
| J721E_DEV_PRU_ICSSG1 | pr1_iep0_cap_intr_req | 5 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 53 | J721E_DEV_C66SS0_INTROUTER0 | in | 141 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 141 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 54 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 438 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 438 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 54 | J721E_DEV_PRU_ICSSG0 | pr1_iep0_cap_intr_req | 6 |
| J721E_DEV_PRU_ICSSG1 | pr1_iep0_cap_intr_req | 6 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 54 | J721E_DEV_C66SS0_INTROUTER0 | in | 142 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 142 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 55 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 439 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 439 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 55 | J721E_DEV_PRU_ICSSG0 | pr1_iep0_cap_intr_req | 7 |
| J721E_DEV_PRU_ICSSG1 | pr1_iep0_cap_intr_req | 7 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 55 | J721E_DEV_C66SS0_INTROUTER0 | in | 143 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 143 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 56 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 440 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 440 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 56 | J721E_DEV_PRU_ICSSG0 | pr1_iep0_cap_intr_req | 8 |
| J721E_DEV_PRU_ICSSG1 | pr1_iep0_cap_intr_req | 8 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 56 | J721E_DEV_C66SS0_INTROUTER0 | in | 144 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 144 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 57 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 441 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 441 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 57 | J721E_DEV_PRU_ICSSG0 | pr1_iep0_cap_intr_req | 9 |
| J721E_DEV_PRU_ICSSG1 | pr1_iep0_cap_intr_req | 9 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 57 | J721E_DEV_C66SS0_INTROUTER0 | in | 145 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 145 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 58 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 442 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 442 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 58 | J721E_DEV_PRU_ICSSG0 | pr1_iep1_cap_intr_req | 10 |
| J721E_DEV_PRU_ICSSG1 | pr1_iep1_cap_intr_req | 10 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 58 | J721E_DEV_C66SS0_INTROUTER0 | in | 146 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 146 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 59 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 443 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 443 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 59 | J721E_DEV_PRU_ICSSG0 | pr1_iep1_cap_intr_req | 11 |
| J721E_DEV_PRU_ICSSG1 | pr1_iep1_cap_intr_req | 11 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 59 | J721E_DEV_C66SS0_INTROUTER0 | in | 147 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 147 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 60 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 444 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 444 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 60 | J721E_DEV_PRU_ICSSG0 | pr1_iep1_cap_intr_req | 12 |
| J721E_DEV_PRU_ICSSG1 | pr1_iep1_cap_intr_req | 12 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 60 | J721E_DEV_C66SS0_INTROUTER0 | in | 148 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 148 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 61 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 445 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 445 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 61 | J721E_DEV_PRU_ICSSG0 | pr1_iep1_cap_intr_req | 13 |
| J721E_DEV_PRU_ICSSG1 | pr1_iep1_cap_intr_req | 13 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 61 | J721E_DEV_C66SS0_INTROUTER0 | in | 149 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 149 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 62 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 446 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 446 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 62 | J721E_DEV_PRU_ICSSG0 | pr1_iep1_cap_intr_req | 14 |
| J721E_DEV_PRU_ICSSG1 | pr1_iep1_cap_intr_req | 14 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 62 | J721E_DEV_C66SS0_INTROUTER0 | in | 150 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 150 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 63 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 447 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 447 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 63 | J721E_DEV_PRU_ICSSG0 | pr1_iep1_cap_intr_req | 15 |
| J721E_DEV_PRU_ICSSG1 | pr1_iep1_cap_intr_req | 15 | |||
| J721E_DEV_GPIOMUX_INTRTR0 | 131 | 63 | J721E_DEV_C66SS0_INTROUTER0 | in | 151 |
| J721E_DEV_C66SS1_INTROUTER0 | in | 151 |
R5FSS0_INTROUTER0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 0 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 1 | J721E_DEV_USB1 | otgirq | 9 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 2 | J721E_DEV_USB1 | irq | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 3 | J721E_DEV_USB1 | irq | 2 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 4 | J721E_DEV_USB1 | irq | 3 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 5 | J721E_DEV_USB1 | irq | 4 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 6 | J721E_DEV_USB1 | irq | 5 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 7 | J721E_DEV_USB1 | irq | 6 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 8 | J721E_DEV_USB1 | irq | 7 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 9 | J721E_DEV_USB1 | irq | 8 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 10 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 11 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 12 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 13 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 14 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 15 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 16 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 17 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 18 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 19 | J721E_DEV_PCIE2 | pcie_legacy_pulse | 5 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 20 | J721E_DEV_PCIE2 | pcie_downstream_pulse | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 21 | J721E_DEV_PCIE2 | pcie_flr_pulse | 3 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 22 | J721E_DEV_PCIE2 | pcie_phy_level | 8 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 23 | J721E_DEV_PCIE2 | pcie_local_level | 7 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 24 | J721E_DEV_PCIE2 | pcie_error_pulse | 2 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 25 | J721E_DEV_PCIE2 | pcie_link_state_pulse | 6 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 26 | J721E_DEV_PCIE2 | pcie_pwr_state_pulse | 10 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 27 | J721E_DEV_PCIE2 | pcie_ptm_valid_pulse | 9 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 28 | J721E_DEV_PCIE2 | pcie_hot_reset_pulse | 4 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 29 | J721E_DEV_PCIE2 | pcie_cpts_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 30 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 4 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 31 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 5 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 32 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 6 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 33 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 7 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 34 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 8 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 35 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 9 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 36 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 10 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 37 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 11 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 38 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 4 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 39 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 5 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 40 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 6 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 41 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 7 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 42 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 8 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 43 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 9 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 44 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 10 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 45 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 11 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 46 | J721E_DEV_PRU_ICSSG0 | pr1_tx_sof_intr_req | 54 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 47 | J721E_DEV_PRU_ICSSG0 | pr1_tx_sof_intr_req | 55 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 48 | J721E_DEV_PRU_ICSSG0 | pr1_rx_sof_intr_req | 52 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 49 | J721E_DEV_PRU_ICSSG0 | pr1_rx_sof_intr_req | 53 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 50 | J721E_DEV_PRU_ICSSG1 | pr1_tx_sof_intr_req | 54 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 51 | J721E_DEV_PRU_ICSSG1 | pr1_tx_sof_intr_req | 55 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 52 | J721E_DEV_PRU_ICSSG1 | pr1_rx_sof_intr_req | 52 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 53 | J721E_DEV_PRU_ICSSG1 | pr1_rx_sof_intr_req | 53 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 54 | J721E_DEV_PCIE3 | pcie_legacy_pulse | 5 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 55 | J721E_DEV_PCIE3 | pcie_downstream_pulse | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 56 | J721E_DEV_PCIE3 | pcie_flr_pulse | 3 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 57 | J721E_DEV_PCIE3 | pcie_phy_level | 8 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 58 | J721E_DEV_PCIE3 | pcie_local_level | 7 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 59 | J721E_DEV_PCIE3 | pcie_error_pulse | 2 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 60 | J721E_DEV_PCIE3 | pcie_link_state_pulse | 6 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 61 | J721E_DEV_PCIE3 | pcie_pwr_state_pulse | 10 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 62 | J721E_DEV_PCIE3 | pcie_ptm_valid_pulse | 9 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 63 | J721E_DEV_PCIE3 | pcie_hot_reset_pulse | 4 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 64 | J721E_DEV_PCIE3 | pcie_cpts_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 65 | J721E_DEV_USB1 | host_system_error | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 66 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 67 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 68 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 69 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 70 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 2 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 71 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 3 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 72 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 4 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 73 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 5 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 74 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 6 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 75 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 7 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 76 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 8 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 77 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 9 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 78 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 10 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 79 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 11 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 80 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 12 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 81 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 13 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 82 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 14 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 83 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 15 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 84 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 85 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 86 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 2 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 87 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 3 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 88 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 4 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 89 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 5 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 90 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 6 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 91 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 7 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 92 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 8 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 93 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 9 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 94 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 10 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 95 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 11 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 96 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 12 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 97 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 13 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 98 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 14 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 99 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 15 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 100 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 16 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 101 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 17 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 102 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 18 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 103 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 19 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 104 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 20 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 105 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 21 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 106 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 22 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 107 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 23 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 108 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 24 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 109 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 25 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 110 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 26 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 111 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 27 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 112 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 28 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 113 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 29 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 114 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 30 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 115 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 31 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 116 | J721E_DEV_MCU_ADC12_16FFC0 | gen_level | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 117 | J721E_DEV_MCU_ADC12_16FFC1 | gen_level | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 118 | J721E_DEV_MCU_CPSW0 | stat_pend | 6 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 119 | J721E_DEV_MCU_CPSW0 | mdio_pend | 5 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 120 | J721E_DEV_MCU_CPSW0 | evnt_pend | 4 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 121 | J721E_DEV_MCU_DCC0 | intr_done_level | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 122 | J721E_DEV_MCU_DCC1 | intr_done_level | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 123 | J721E_DEV_MCU_DCC2 | intr_done_level | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 124 | J721E_DEV_MCU_TIMER0 | intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 125 | J721E_DEV_MCU_TIMER1 | intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 126 | J721E_DEV_MCU_TIMER2 | intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 127 | J721E_DEV_MCU_TIMER3 | intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 128 | J721E_DEV_MCU_TIMER4 | intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 129 | J721E_DEV_MCU_TIMER5 | intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 130 | J721E_DEV_MCU_TIMER6 | intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 131 | J721E_DEV_MCU_TIMER7 | intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 132 | J721E_DEV_MCU_TIMER8 | intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 133 | J721E_DEV_MCU_TIMER9 | intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 134 | J721E_DEV_MCU_I2C0 | pointrpend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 135 | J721E_DEV_MCU_I2C1 | pointrpend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 136 | J721E_DEV_MCU_MCSPI0 | intr_spi | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 137 | J721E_DEV_MCU_MCSPI1 | intr_spi | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 138 | J721E_DEV_MCU_MCSPI2 | intr_spi | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 139 | J721E_DEV_MCU_UART0 | usart_irq | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 140 | J721E_DEV_MCU_I3C0 | i3c__int | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 141 | J721E_DEV_MCU_I3C1 | i3c__int | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 142 | J721E_DEV_MCU_FSS0_OSPI_0 | ospi_lvl_intr | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 143 | J721E_DEV_MCU_FSS0_OSPI_1 | ospi_lvl_intr | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 144 | J721E_DEV_MCU_FSS0_HYPERBUS1P0_0 | hpb_intr | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 145 | J721E_DEV_MCU_FSS0_FSAS_0 | otfa_intr_err_pend | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 146 | J721E_DEV_MCU_FSS0_FSAS_0 | ecc_intr_err_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 147 | J721E_DEV_MCU_SA2_UL0 | sa_ul_pka | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 148 | J721E_DEV_MCU_SA2_UL0 | sa_ul_trng | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 149 | J721E_DEV_MCU_ESM0 | esm_int_low_lvl | 2 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 150 | J721E_DEV_MCU_ESM0 | esm_int_hi_lvl | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 151 | J721E_DEV_MCU_ESM0 | esm_int_cfg_lvl | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 152 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 153 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 154 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 155 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 156 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 157 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 158 | J721E_DEV_WKUP_I2C0 | pointrpend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 159 | J721E_DEV_WKUP_UART0 | usart_irq | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 160 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 16 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 161 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 17 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 162 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 18 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 163 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 19 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 164 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 20 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 165 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 21 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 166 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 22 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 167 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 23 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 168 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 24 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 169 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 25 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 170 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 26 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 171 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 27 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 172 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 28 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 173 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 29 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 174 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 30 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 175 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 31 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 176 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 177 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 178 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 179 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 180 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 181 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 182 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 183 | J721E_DEV_I2C2 | pointrpend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 184 | J721E_DEV_I2C3 | pointrpend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 185 | J721E_DEV_I2C4 | pointrpend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 186 | J721E_DEV_I2C5 | pointrpend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 187 | J721E_DEV_I2C6 | pointrpend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 188 | J721E_DEV_UART3 | usart_irq | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 189 | J721E_DEV_UART4 | usart_irq | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 190 | J721E_DEV_UART5 | usart_irq | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 191 | J721E_DEV_UART6 | usart_irq | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 192 | J721E_DEV_UART7 | usart_irq | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 193 | J721E_DEV_UART8 | usart_irq | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 194 | J721E_DEV_UART9 | usart_irq | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 195 | J721E_DEV_MCSPI2 | intr_spi | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 196 | J721E_DEV_MCSPI3 | intr_spi | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 197 | J721E_DEV_MCSPI4 | intr_spi | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 198 | J721E_DEV_MCSPI5 | intr_spi | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 199 | J721E_DEV_MCSPI6 | intr_spi | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 200 | J721E_DEV_MCSPI7 | intr_spi | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 201 | J721E_DEV_I3C0 | i3c__int | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 202 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 203 | J721E_DEV_AASRC0 | err_level | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 204 | J721E_DEV_AASRC0 | infifo_level | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 205 | J721E_DEV_AASRC0 | ingroup_level | 2 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 206 | J721E_DEV_AASRC0 | outfifo_level | 3 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 207 | J721E_DEV_AASRC0 | outgroup_level | 4 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 208 | J721E_DEV_MCASP2 | xmit_intr_pend | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 209 | J721E_DEV_MCASP2 | rec_intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 210 | J721E_DEV_MCASP3 | xmit_intr_pend | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 211 | J721E_DEV_MCASP3 | rec_intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 212 | J721E_DEV_MCASP4 | xmit_intr_pend | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 213 | J721E_DEV_MCASP4 | rec_intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 214 | J721E_DEV_MCASP5 | xmit_intr_pend | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 215 | J721E_DEV_MCASP5 | rec_intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 216 | J721E_DEV_MCASP6 | xmit_intr_pend | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 217 | J721E_DEV_MCASP6 | rec_intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 218 | J721E_DEV_MCASP7 | xmit_intr_pend | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 219 | J721E_DEV_MCASP7 | rec_intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 220 | J721E_DEV_MCASP8 | xmit_intr_pend | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 221 | J721E_DEV_MCASP8 | rec_intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 222 | J721E_DEV_MCASP9 | xmit_intr_pend | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 223 | J721E_DEV_MCASP9 | rec_intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 224 | J721E_DEV_MCASP10 | xmit_intr_pend | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 225 | J721E_DEV_MCASP10 | rec_intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 226 | J721E_DEV_MCASP11 | xmit_intr_pend | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 227 | J721E_DEV_MCASP11 | rec_intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 228 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 229 | J721E_DEV_GPMC0 | gpmc_sinterrupt | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 230 | J721E_DEV_ELM0 | elm_porocpsinterrupt_lvl | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 231 | J721E_DEV_USB0 | otgirq | 9 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 232 | J721E_DEV_USB0 | irq | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 233 | J721E_DEV_USB0 | irq | 2 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 234 | J721E_DEV_USB0 | irq | 3 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 235 | J721E_DEV_USB0 | irq | 4 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 236 | J721E_DEV_USB0 | irq | 5 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 237 | J721E_DEV_USB0 | irq | 6 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 238 | J721E_DEV_USB0 | irq | 7 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 239 | J721E_DEV_USB0 | irq | 8 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 240 | J721E_DEV_TIMER0 | intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 241 | J721E_DEV_TIMER1 | intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 242 | J721E_DEV_TIMER2 | intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 243 | J721E_DEV_TIMER3 | intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 244 | J721E_DEV_TIMER4 | intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 245 | J721E_DEV_TIMER5 | intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 246 | J721E_DEV_TIMER6 | intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 247 | J721E_DEV_TIMER7 | intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 248 | J721E_DEV_TIMER8 | intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 249 | J721E_DEV_TIMER9 | intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 250 | J721E_DEV_TIMER10 | intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 251 | J721E_DEV_TIMER11 | intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 252 | J721E_DEV_PCIE1 | pcie_legacy_pulse | 5 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 253 | J721E_DEV_PCIE1 | pcie_downstream_pulse | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 254 | J721E_DEV_PCIE1 | pcie_flr_pulse | 3 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 255 | J721E_DEV_PCIE1 | pcie_phy_level | 8 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 256 | J721E_DEV_PCIE1 | pcie_local_level | 7 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 257 | J721E_DEV_PCIE1 | pcie_error_pulse | 2 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 258 | J721E_DEV_PCIE1 | pcie_link_state_pulse | 6 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 259 | J721E_DEV_PCIE1 | pcie_pwr_state_pulse | 10 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 260 | J721E_DEV_PCIE1 | pcie_ptm_valid_pulse | 9 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 261 | J721E_DEV_PCIE1 | pcie_hot_reset_pulse | 4 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 262 | J721E_DEV_PCIE1 | pcie_cpts_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 263 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 264 | J721E_DEV_DDR0 | ddrss_controller | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 265 | J721E_DEV_DDR0 | ddrss_v2a_other_err_lvl | 3 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 266 | J721E_DEV_DDR0 | ddrss_hs_phy_global_error | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 267 | J721E_DEV_DDR0 | ddrss_pll_freq_change_req | 2 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 268 | J721E_DEV_CSI_TX_IF0 | csi_interrupt | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 269 | J721E_DEV_CSI_TX_IF0 | csi_level | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 270 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 271 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 272 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 273 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 274 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 275 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 276 | J721E_DEV_VPFE0 | ccdc_intr_pend | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 277 | J721E_DEV_VPFE0 | rat_exp_intr | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 278 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 279 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 280 | J721E_DEV_DCC0 | intr_done_level | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 281 | J721E_DEV_DCC1 | intr_done_level | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 282 | J721E_DEV_DCC2 | intr_done_level | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 283 | J721E_DEV_DCC3 | intr_done_level | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 284 | J721E_DEV_DCC4 | intr_done_level | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 285 | J721E_DEV_DCC5 | intr_done_level | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 286 | J721E_DEV_DCC6 | intr_done_level | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 287 | J721E_DEV_DCC7 | intr_done_level | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 288 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 289 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 290 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 2 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 291 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 3 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 292 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 4 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 293 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 5 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 294 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 6 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 295 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 7 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 296 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 8 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 297 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 9 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 298 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 10 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 299 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 11 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 300 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 12 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 301 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 13 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 302 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 14 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 303 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 15 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 304 | J721E_DEV_DCC8 | intr_done_level | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 305 | J721E_DEV_DCC9 | intr_done_level | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 306 | J721E_DEV_DCC10 | intr_done_level | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 307 | J721E_DEV_DCC11 | intr_done_level | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 308 | J721E_DEV_DCC12 | intr_done_level | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 309 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 310 | J721E_DEV_MMCSD1 | emmcsdss_intr | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 311 | J721E_DEV_MMCSD2 | emmcsdss_intr | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 312 | J721E_DEV_UFS0 | ufs_intr | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 313 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 314 | J721E_DEV_SA2_UL0 | sa_ul_pka | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 315 | J721E_DEV_SA2_UL0 | sa_ul_trng | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 316 | J721E_DEV_ECAP0 | ecap_int | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 317 | J721E_DEV_ECAP1 | ecap_int | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 318 | J721E_DEV_ECAP2 | ecap_int | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 319 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 320 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 321 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 322 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 323 | J721E_DEV_USB0 | host_system_error | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 324 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 325 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 326 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 327 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 328 | J721E_DEV_WKUP_VTM0 | therm_lvl_gt_th1_intr | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 329 | J721E_DEV_WKUP_VTM0 | therm_lvl_gt_th2_intr | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 330 | J721E_DEV_WKUP_VTM0 | therm_lvl_lt_th0_intr | 2 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 331 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 332 | J721E_DEV_COMPUTE_CLUSTER0 | gic_output_waker_gic_pwr0_wake_request | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 333 | J721E_DEV_COMPUTE_CLUSTER0 | gic_output_waker_gic_pwr0_wake_request | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 334 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 335 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 336 | J721E_DEV_MCU_MCAN0 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 337 | J721E_DEV_MCU_MCAN0 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 338 | J721E_DEV_MCU_MCAN0 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 339 | J721E_DEV_MCU_MCAN1 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 340 | J721E_DEV_MCU_MCAN1 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 341 | J721E_DEV_MCU_MCAN1 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 342 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 343 | Use TRM - Not managed by TISCI |
R5FSS0_INTROUTER0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 0 | J721E_DEV_R5FSS0_CORE0 | intr | 256 |
| J721E_DEV_R5FSS0_CORE1 | intr | 256 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 1 | J721E_DEV_R5FSS0_CORE0 | intr | 257 |
| J721E_DEV_R5FSS0_CORE1 | intr | 257 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 2 | J721E_DEV_R5FSS0_CORE0 | intr | 258 |
| J721E_DEV_R5FSS0_CORE1 | intr | 258 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 3 | J721E_DEV_R5FSS0_CORE0 | intr | 259 |
| J721E_DEV_R5FSS0_CORE1 | intr | 259 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 4 | J721E_DEV_R5FSS0_CORE0 | intr | 260 |
| J721E_DEV_R5FSS0_CORE1 | intr | 260 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 5 | J721E_DEV_R5FSS0_CORE0 | intr | 261 |
| J721E_DEV_R5FSS0_CORE1 | intr | 261 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 6 | J721E_DEV_R5FSS0_CORE0 | intr | 262 |
| J721E_DEV_R5FSS0_CORE1 | intr | 262 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 7 | J721E_DEV_R5FSS0_CORE0 | intr | 263 |
| J721E_DEV_R5FSS0_CORE1 | intr | 263 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 8 | J721E_DEV_R5FSS0_CORE0 | intr | 264 |
| J721E_DEV_R5FSS0_CORE1 | intr | 264 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 9 | J721E_DEV_R5FSS0_CORE0 | intr | 265 |
| J721E_DEV_R5FSS0_CORE1 | intr | 265 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 10 | J721E_DEV_R5FSS0_CORE0 | intr | 266 |
| J721E_DEV_R5FSS0_CORE1 | intr | 266 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 11 | J721E_DEV_R5FSS0_CORE0 | intr | 267 |
| J721E_DEV_R5FSS0_CORE1 | intr | 267 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 12 | J721E_DEV_R5FSS0_CORE0 | intr | 268 |
| J721E_DEV_R5FSS0_CORE1 | intr | 268 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 13 | J721E_DEV_R5FSS0_CORE0 | intr | 269 |
| J721E_DEV_R5FSS0_CORE1 | intr | 269 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 14 | J721E_DEV_R5FSS0_CORE0 | intr | 270 |
| J721E_DEV_R5FSS0_CORE1 | intr | 270 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 15 | J721E_DEV_R5FSS0_CORE0 | intr | 271 |
| J721E_DEV_R5FSS0_CORE1 | intr | 271 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 16 | J721E_DEV_R5FSS0_CORE0 | intr | 272 |
| J721E_DEV_R5FSS0_CORE1 | intr | 272 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 17 | J721E_DEV_R5FSS0_CORE0 | intr | 273 |
| J721E_DEV_R5FSS0_CORE1 | intr | 273 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 18 | J721E_DEV_R5FSS0_CORE0 | intr | 274 |
| J721E_DEV_R5FSS0_CORE1 | intr | 274 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 19 | J721E_DEV_R5FSS0_CORE0 | intr | 275 |
| J721E_DEV_R5FSS0_CORE1 | intr | 275 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 20 | J721E_DEV_R5FSS0_CORE0 | intr | 276 |
| J721E_DEV_R5FSS0_CORE1 | intr | 276 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 21 | J721E_DEV_R5FSS0_CORE0 | intr | 277 |
| J721E_DEV_R5FSS0_CORE1 | intr | 277 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 22 | J721E_DEV_R5FSS0_CORE0 | intr | 278 |
| J721E_DEV_R5FSS0_CORE1 | intr | 278 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 23 | J721E_DEV_R5FSS0_CORE0 | intr | 279 |
| J721E_DEV_R5FSS0_CORE1 | intr | 279 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 24 | J721E_DEV_R5FSS0_CORE0 | intr | 280 |
| J721E_DEV_R5FSS0_CORE1 | intr | 280 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 25 | J721E_DEV_R5FSS0_CORE0 | intr | 281 |
| J721E_DEV_R5FSS0_CORE1 | intr | 281 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 26 | J721E_DEV_R5FSS0_CORE0 | intr | 282 |
| J721E_DEV_R5FSS0_CORE1 | intr | 282 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 27 | J721E_DEV_R5FSS0_CORE0 | intr | 283 |
| J721E_DEV_R5FSS0_CORE1 | intr | 283 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 28 | J721E_DEV_R5FSS0_CORE0 | intr | 284 |
| J721E_DEV_R5FSS0_CORE1 | intr | 284 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 29 | J721E_DEV_R5FSS0_CORE0 | intr | 285 |
| J721E_DEV_R5FSS0_CORE1 | intr | 285 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 30 | J721E_DEV_R5FSS0_CORE0 | intr | 286 |
| J721E_DEV_R5FSS0_CORE1 | intr | 286 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 31 | J721E_DEV_R5FSS0_CORE0 | intr | 287 |
| J721E_DEV_R5FSS0_CORE1 | intr | 287 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 32 | J721E_DEV_R5FSS0_CORE0 | intr | 288 |
| J721E_DEV_R5FSS0_CORE1 | intr | 288 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 33 | J721E_DEV_R5FSS0_CORE0 | intr | 289 |
| J721E_DEV_R5FSS0_CORE1 | intr | 289 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 34 | J721E_DEV_R5FSS0_CORE0 | intr | 290 |
| J721E_DEV_R5FSS0_CORE1 | intr | 290 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 35 | J721E_DEV_R5FSS0_CORE0 | intr | 291 |
| J721E_DEV_R5FSS0_CORE1 | intr | 291 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 36 | J721E_DEV_R5FSS0_CORE0 | intr | 292 |
| J721E_DEV_R5FSS0_CORE1 | intr | 292 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 37 | J721E_DEV_R5FSS0_CORE0 | intr | 293 |
| J721E_DEV_R5FSS0_CORE1 | intr | 293 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 38 | J721E_DEV_R5FSS0_CORE0 | intr | 294 |
| J721E_DEV_R5FSS0_CORE1 | intr | 294 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 39 | J721E_DEV_R5FSS0_CORE0 | intr | 295 |
| J721E_DEV_R5FSS0_CORE1 | intr | 295 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 40 | J721E_DEV_R5FSS0_CORE0 | intr | 296 |
| J721E_DEV_R5FSS0_CORE1 | intr | 296 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 41 | J721E_DEV_R5FSS0_CORE0 | intr | 297 |
| J721E_DEV_R5FSS0_CORE1 | intr | 297 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 42 | J721E_DEV_R5FSS0_CORE0 | intr | 298 |
| J721E_DEV_R5FSS0_CORE1 | intr | 298 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 43 | J721E_DEV_R5FSS0_CORE0 | intr | 299 |
| J721E_DEV_R5FSS0_CORE1 | intr | 299 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 44 | J721E_DEV_R5FSS0_CORE0 | intr | 300 |
| J721E_DEV_R5FSS0_CORE1 | intr | 300 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 45 | J721E_DEV_R5FSS0_CORE0 | intr | 301 |
| J721E_DEV_R5FSS0_CORE1 | intr | 301 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 46 | J721E_DEV_R5FSS0_CORE0 | intr | 302 |
| J721E_DEV_R5FSS0_CORE1 | intr | 302 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 47 | J721E_DEV_R5FSS0_CORE0 | intr | 303 |
| J721E_DEV_R5FSS0_CORE1 | intr | 303 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 48 | J721E_DEV_R5FSS0_CORE0 | intr | 304 |
| J721E_DEV_R5FSS0_CORE1 | intr | 304 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 49 | J721E_DEV_R5FSS0_CORE0 | intr | 305 |
| J721E_DEV_R5FSS0_CORE1 | intr | 305 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 50 | J721E_DEV_R5FSS0_CORE0 | intr | 306 |
| J721E_DEV_R5FSS0_CORE1 | intr | 306 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 51 | J721E_DEV_R5FSS0_CORE0 | intr | 307 |
| J721E_DEV_R5FSS0_CORE1 | intr | 307 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 52 | J721E_DEV_R5FSS0_CORE0 | intr | 308 |
| J721E_DEV_R5FSS0_CORE1 | intr | 308 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 53 | J721E_DEV_R5FSS0_CORE0 | intr | 309 |
| J721E_DEV_R5FSS0_CORE1 | intr | 309 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 54 | J721E_DEV_R5FSS0_CORE0 | intr | 310 |
| J721E_DEV_R5FSS0_CORE1 | intr | 310 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 55 | J721E_DEV_R5FSS0_CORE0 | intr | 311 |
| J721E_DEV_R5FSS0_CORE1 | intr | 311 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 56 | J721E_DEV_R5FSS0_CORE0 | intr | 312 |
| J721E_DEV_R5FSS0_CORE1 | intr | 312 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 57 | J721E_DEV_R5FSS0_CORE0 | intr | 313 |
| J721E_DEV_R5FSS0_CORE1 | intr | 313 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 58 | J721E_DEV_R5FSS0_CORE0 | intr | 314 |
| J721E_DEV_R5FSS0_CORE1 | intr | 314 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 59 | J721E_DEV_R5FSS0_CORE0 | intr | 315 |
| J721E_DEV_R5FSS0_CORE1 | intr | 315 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 60 | J721E_DEV_R5FSS0_CORE0 | intr | 316 |
| J721E_DEV_R5FSS0_CORE1 | intr | 316 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 61 | J721E_DEV_R5FSS0_CORE0 | intr | 317 |
| J721E_DEV_R5FSS0_CORE1 | intr | 317 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 62 | J721E_DEV_R5FSS0_CORE0 | intr | 318 |
| J721E_DEV_R5FSS0_CORE1 | intr | 318 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 63 | J721E_DEV_R5FSS0_CORE0 | intr | 319 |
| J721E_DEV_R5FSS0_CORE1 | intr | 319 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 64 | J721E_DEV_R5FSS0_CORE0 | intr | 320 |
| J721E_DEV_R5FSS0_CORE1 | intr | 320 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 65 | J721E_DEV_R5FSS0_CORE0 | intr | 321 |
| J721E_DEV_R5FSS0_CORE1 | intr | 321 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 66 | J721E_DEV_R5FSS0_CORE0 | intr | 322 |
| J721E_DEV_R5FSS0_CORE1 | intr | 322 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 67 | J721E_DEV_R5FSS0_CORE0 | intr | 323 |
| J721E_DEV_R5FSS0_CORE1 | intr | 323 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 68 | J721E_DEV_R5FSS0_CORE0 | intr | 324 |
| J721E_DEV_R5FSS0_CORE1 | intr | 324 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 69 | J721E_DEV_R5FSS0_CORE0 | intr | 325 |
| J721E_DEV_R5FSS0_CORE1 | intr | 325 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 70 | J721E_DEV_R5FSS0_CORE0 | intr | 326 |
| J721E_DEV_R5FSS0_CORE1 | intr | 326 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 71 | J721E_DEV_R5FSS0_CORE0 | intr | 327 |
| J721E_DEV_R5FSS0_CORE1 | intr | 327 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 72 | J721E_DEV_R5FSS0_CORE0 | intr | 328 |
| J721E_DEV_R5FSS0_CORE1 | intr | 328 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 73 | J721E_DEV_R5FSS0_CORE0 | intr | 329 |
| J721E_DEV_R5FSS0_CORE1 | intr | 329 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 74 | J721E_DEV_R5FSS0_CORE0 | intr | 330 |
| J721E_DEV_R5FSS0_CORE1 | intr | 330 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 75 | J721E_DEV_R5FSS0_CORE0 | intr | 331 |
| J721E_DEV_R5FSS0_CORE1 | intr | 331 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 76 | J721E_DEV_R5FSS0_CORE0 | intr | 332 |
| J721E_DEV_R5FSS0_CORE1 | intr | 332 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 77 | J721E_DEV_R5FSS0_CORE0 | intr | 333 |
| J721E_DEV_R5FSS0_CORE1 | intr | 333 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 78 | J721E_DEV_R5FSS0_CORE0 | intr | 334 |
| J721E_DEV_R5FSS0_CORE1 | intr | 334 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 79 | J721E_DEV_R5FSS0_CORE0 | intr | 335 |
| J721E_DEV_R5FSS0_CORE1 | intr | 335 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 80 | J721E_DEV_R5FSS0_CORE0 | intr | 336 |
| J721E_DEV_R5FSS0_CORE1 | intr | 336 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 81 | J721E_DEV_R5FSS0_CORE0 | intr | 337 |
| J721E_DEV_R5FSS0_CORE1 | intr | 337 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 82 | J721E_DEV_R5FSS0_CORE0 | intr | 338 |
| J721E_DEV_R5FSS0_CORE1 | intr | 338 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 83 | J721E_DEV_R5FSS0_CORE0 | intr | 339 |
| J721E_DEV_R5FSS0_CORE1 | intr | 339 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 84 | J721E_DEV_R5FSS0_CORE0 | intr | 340 |
| J721E_DEV_R5FSS0_CORE1 | intr | 340 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 85 | J721E_DEV_R5FSS0_CORE0 | intr | 341 |
| J721E_DEV_R5FSS0_CORE1 | intr | 341 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 86 | J721E_DEV_R5FSS0_CORE0 | intr | 342 |
| J721E_DEV_R5FSS0_CORE1 | intr | 342 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 87 | J721E_DEV_R5FSS0_CORE0 | intr | 343 |
| J721E_DEV_R5FSS0_CORE1 | intr | 343 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 88 | J721E_DEV_R5FSS0_CORE0 | intr | 344 |
| J721E_DEV_R5FSS0_CORE1 | intr | 344 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 89 | J721E_DEV_R5FSS0_CORE0 | intr | 345 |
| J721E_DEV_R5FSS0_CORE1 | intr | 345 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 90 | J721E_DEV_R5FSS0_CORE0 | intr | 346 |
| J721E_DEV_R5FSS0_CORE1 | intr | 346 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 91 | J721E_DEV_R5FSS0_CORE0 | intr | 347 |
| J721E_DEV_R5FSS0_CORE1 | intr | 347 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 92 | J721E_DEV_R5FSS0_CORE0 | intr | 348 |
| J721E_DEV_R5FSS0_CORE1 | intr | 348 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 93 | J721E_DEV_R5FSS0_CORE0 | intr | 349 |
| J721E_DEV_R5FSS0_CORE1 | intr | 349 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 94 | J721E_DEV_R5FSS0_CORE0 | intr | 350 |
| J721E_DEV_R5FSS0_CORE1 | intr | 350 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 95 | J721E_DEV_R5FSS0_CORE0 | intr | 351 |
| J721E_DEV_R5FSS0_CORE1 | intr | 351 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 96 | J721E_DEV_R5FSS0_CORE0 | intr | 352 |
| J721E_DEV_R5FSS0_CORE1 | intr | 352 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 97 | J721E_DEV_R5FSS0_CORE0 | intr | 353 |
| J721E_DEV_R5FSS0_CORE1 | intr | 353 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 98 | J721E_DEV_R5FSS0_CORE0 | intr | 354 |
| J721E_DEV_R5FSS0_CORE1 | intr | 354 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 99 | J721E_DEV_R5FSS0_CORE0 | intr | 355 |
| J721E_DEV_R5FSS0_CORE1 | intr | 355 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 100 | J721E_DEV_R5FSS0_CORE0 | intr | 356 |
| J721E_DEV_R5FSS0_CORE1 | intr | 356 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 101 | J721E_DEV_R5FSS0_CORE0 | intr | 357 |
| J721E_DEV_R5FSS0_CORE1 | intr | 357 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 102 | J721E_DEV_R5FSS0_CORE0 | intr | 358 |
| J721E_DEV_R5FSS0_CORE1 | intr | 358 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 103 | J721E_DEV_R5FSS0_CORE0 | intr | 359 |
| J721E_DEV_R5FSS0_CORE1 | intr | 359 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 104 | J721E_DEV_R5FSS0_CORE0 | intr | 360 |
| J721E_DEV_R5FSS0_CORE1 | intr | 360 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 105 | J721E_DEV_R5FSS0_CORE0 | intr | 361 |
| J721E_DEV_R5FSS0_CORE1 | intr | 361 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 106 | J721E_DEV_R5FSS0_CORE0 | intr | 362 |
| J721E_DEV_R5FSS0_CORE1 | intr | 362 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 107 | J721E_DEV_R5FSS0_CORE0 | intr | 363 |
| J721E_DEV_R5FSS0_CORE1 | intr | 363 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 108 | J721E_DEV_R5FSS0_CORE0 | intr | 364 |
| J721E_DEV_R5FSS0_CORE1 | intr | 364 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 109 | J721E_DEV_R5FSS0_CORE0 | intr | 365 |
| J721E_DEV_R5FSS0_CORE1 | intr | 365 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 110 | J721E_DEV_R5FSS0_CORE0 | intr | 366 |
| J721E_DEV_R5FSS0_CORE1 | intr | 366 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 111 | J721E_DEV_R5FSS0_CORE0 | intr | 367 |
| J721E_DEV_R5FSS0_CORE1 | intr | 367 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 112 | J721E_DEV_R5FSS0_CORE0 | intr | 368 |
| J721E_DEV_R5FSS0_CORE1 | intr | 368 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 113 | J721E_DEV_R5FSS0_CORE0 | intr | 369 |
| J721E_DEV_R5FSS0_CORE1 | intr | 369 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 114 | J721E_DEV_R5FSS0_CORE0 | intr | 370 |
| J721E_DEV_R5FSS0_CORE1 | intr | 370 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 115 | J721E_DEV_R5FSS0_CORE0 | intr | 371 |
| J721E_DEV_R5FSS0_CORE1 | intr | 371 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 116 | J721E_DEV_R5FSS0_CORE0 | intr | 372 |
| J721E_DEV_R5FSS0_CORE1 | intr | 372 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 117 | J721E_DEV_R5FSS0_CORE0 | intr | 373 |
| J721E_DEV_R5FSS0_CORE1 | intr | 373 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 118 | J721E_DEV_R5FSS0_CORE0 | intr | 374 |
| J721E_DEV_R5FSS0_CORE1 | intr | 374 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 119 | J721E_DEV_R5FSS0_CORE0 | intr | 375 |
| J721E_DEV_R5FSS0_CORE1 | intr | 375 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 120 | J721E_DEV_R5FSS0_CORE0 | intr | 376 |
| J721E_DEV_R5FSS0_CORE1 | intr | 376 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 121 | J721E_DEV_R5FSS0_CORE0 | intr | 377 |
| J721E_DEV_R5FSS0_CORE1 | intr | 377 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 122 | J721E_DEV_R5FSS0_CORE0 | intr | 378 |
| J721E_DEV_R5FSS0_CORE1 | intr | 378 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 123 | J721E_DEV_R5FSS0_CORE0 | intr | 379 |
| J721E_DEV_R5FSS0_CORE1 | intr | 379 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 124 | J721E_DEV_R5FSS0_CORE0 | intr | 380 |
| J721E_DEV_R5FSS0_CORE1 | intr | 380 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 125 | J721E_DEV_R5FSS0_CORE0 | intr | 381 |
| J721E_DEV_R5FSS0_CORE1 | intr | 381 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 126 | J721E_DEV_R5FSS0_CORE0 | intr | 382 |
| J721E_DEV_R5FSS0_CORE1 | intr | 382 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 127 | J721E_DEV_R5FSS0_CORE0 | intr | 383 |
| J721E_DEV_R5FSS0_CORE1 | intr | 383 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 128 | J721E_DEV_R5FSS0_CORE0 | intr | 384 |
| J721E_DEV_R5FSS0_CORE1 | intr | 384 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 129 | J721E_DEV_R5FSS0_CORE0 | intr | 385 |
| J721E_DEV_R5FSS0_CORE1 | intr | 385 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 130 | J721E_DEV_R5FSS0_CORE0 | intr | 386 |
| J721E_DEV_R5FSS0_CORE1 | intr | 386 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 131 | J721E_DEV_R5FSS0_CORE0 | intr | 387 |
| J721E_DEV_R5FSS0_CORE1 | intr | 387 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 132 | J721E_DEV_R5FSS0_CORE0 | intr | 388 |
| J721E_DEV_R5FSS0_CORE1 | intr | 388 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 133 | J721E_DEV_R5FSS0_CORE0 | intr | 389 |
| J721E_DEV_R5FSS0_CORE1 | intr | 389 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 134 | J721E_DEV_R5FSS0_CORE0 | intr | 390 |
| J721E_DEV_R5FSS0_CORE1 | intr | 390 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 135 | J721E_DEV_R5FSS0_CORE0 | intr | 391 |
| J721E_DEV_R5FSS0_CORE1 | intr | 391 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 136 | J721E_DEV_R5FSS0_CORE0 | intr | 392 |
| J721E_DEV_R5FSS0_CORE1 | intr | 392 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 137 | J721E_DEV_R5FSS0_CORE0 | intr | 393 |
| J721E_DEV_R5FSS0_CORE1 | intr | 393 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 138 | J721E_DEV_R5FSS0_CORE0 | intr | 394 |
| J721E_DEV_R5FSS0_CORE1 | intr | 394 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 139 | J721E_DEV_R5FSS0_CORE0 | intr | 395 |
| J721E_DEV_R5FSS0_CORE1 | intr | 395 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 140 | J721E_DEV_R5FSS0_CORE0 | intr | 396 |
| J721E_DEV_R5FSS0_CORE1 | intr | 396 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 141 | J721E_DEV_R5FSS0_CORE0 | intr | 397 |
| J721E_DEV_R5FSS0_CORE1 | intr | 397 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 142 | J721E_DEV_R5FSS0_CORE0 | intr | 398 |
| J721E_DEV_R5FSS0_CORE1 | intr | 398 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 143 | J721E_DEV_R5FSS0_CORE0 | intr | 399 |
| J721E_DEV_R5FSS0_CORE1 | intr | 399 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 144 | J721E_DEV_R5FSS0_CORE0 | intr | 400 |
| J721E_DEV_R5FSS0_CORE1 | intr | 400 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 145 | J721E_DEV_R5FSS0_CORE0 | intr | 401 |
| J721E_DEV_R5FSS0_CORE1 | intr | 401 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 146 | J721E_DEV_R5FSS0_CORE0 | intr | 402 |
| J721E_DEV_R5FSS0_CORE1 | intr | 402 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 147 | J721E_DEV_R5FSS0_CORE0 | intr | 403 |
| J721E_DEV_R5FSS0_CORE1 | intr | 403 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 148 | J721E_DEV_R5FSS0_CORE0 | intr | 404 |
| J721E_DEV_R5FSS0_CORE1 | intr | 404 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 149 | J721E_DEV_R5FSS0_CORE0 | intr | 405 |
| J721E_DEV_R5FSS0_CORE1 | intr | 405 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 150 | J721E_DEV_R5FSS0_CORE0 | intr | 406 |
| J721E_DEV_R5FSS0_CORE1 | intr | 406 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 151 | J721E_DEV_R5FSS0_CORE0 | intr | 407 |
| J721E_DEV_R5FSS0_CORE1 | intr | 407 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 152 | J721E_DEV_R5FSS0_CORE0 | intr | 408 |
| J721E_DEV_R5FSS0_CORE1 | intr | 408 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 153 | J721E_DEV_R5FSS0_CORE0 | intr | 409 |
| J721E_DEV_R5FSS0_CORE1 | intr | 409 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 154 | J721E_DEV_R5FSS0_CORE0 | intr | 410 |
| J721E_DEV_R5FSS0_CORE1 | intr | 410 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 155 | J721E_DEV_R5FSS0_CORE0 | intr | 411 |
| J721E_DEV_R5FSS0_CORE1 | intr | 411 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 156 | J721E_DEV_R5FSS0_CORE0 | intr | 412 |
| J721E_DEV_R5FSS0_CORE1 | intr | 412 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 157 | J721E_DEV_R5FSS0_CORE0 | intr | 413 |
| J721E_DEV_R5FSS0_CORE1 | intr | 413 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 158 | J721E_DEV_R5FSS0_CORE0 | intr | 414 |
| J721E_DEV_R5FSS0_CORE1 | intr | 414 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 159 | J721E_DEV_R5FSS0_CORE0 | intr | 415 |
| J721E_DEV_R5FSS0_CORE1 | intr | 415 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 160 | J721E_DEV_R5FSS0_CORE0 | intr | 416 |
| J721E_DEV_R5FSS0_CORE1 | intr | 416 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 161 | J721E_DEV_R5FSS0_CORE0 | intr | 417 |
| J721E_DEV_R5FSS0_CORE1 | intr | 417 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 162 | J721E_DEV_R5FSS0_CORE0 | intr | 418 |
| J721E_DEV_R5FSS0_CORE1 | intr | 418 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 163 | J721E_DEV_R5FSS0_CORE0 | intr | 419 |
| J721E_DEV_R5FSS0_CORE1 | intr | 419 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 164 | J721E_DEV_R5FSS0_CORE0 | intr | 420 |
| J721E_DEV_R5FSS0_CORE1 | intr | 420 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 165 | J721E_DEV_R5FSS0_CORE0 | intr | 421 |
| J721E_DEV_R5FSS0_CORE1 | intr | 421 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 166 | J721E_DEV_R5FSS0_CORE0 | intr | 422 |
| J721E_DEV_R5FSS0_CORE1 | intr | 422 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 167 | J721E_DEV_R5FSS0_CORE0 | intr | 423 |
| J721E_DEV_R5FSS0_CORE1 | intr | 423 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 168 | J721E_DEV_R5FSS0_CORE0 | intr | 424 |
| J721E_DEV_R5FSS0_CORE1 | intr | 424 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 169 | J721E_DEV_R5FSS0_CORE0 | intr | 425 |
| J721E_DEV_R5FSS0_CORE1 | intr | 425 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 170 | J721E_DEV_R5FSS0_CORE0 | intr | 426 |
| J721E_DEV_R5FSS0_CORE1 | intr | 426 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 171 | J721E_DEV_R5FSS0_CORE0 | intr | 427 |
| J721E_DEV_R5FSS0_CORE1 | intr | 427 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 172 | J721E_DEV_R5FSS0_CORE0 | intr | 428 |
| J721E_DEV_R5FSS0_CORE1 | intr | 428 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 173 | J721E_DEV_R5FSS0_CORE0 | intr | 429 |
| J721E_DEV_R5FSS0_CORE1 | intr | 429 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 174 | J721E_DEV_R5FSS0_CORE0 | intr | 430 |
| J721E_DEV_R5FSS0_CORE1 | intr | 430 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 175 | J721E_DEV_R5FSS0_CORE0 | intr | 431 |
| J721E_DEV_R5FSS0_CORE1 | intr | 431 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 176 | J721E_DEV_R5FSS0_CORE0 | intr | 432 |
| J721E_DEV_R5FSS0_CORE1 | intr | 432 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 177 | J721E_DEV_R5FSS0_CORE0 | intr | 433 |
| J721E_DEV_R5FSS0_CORE1 | intr | 433 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 178 | J721E_DEV_R5FSS0_CORE0 | intr | 434 |
| J721E_DEV_R5FSS0_CORE1 | intr | 434 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 179 | J721E_DEV_R5FSS0_CORE0 | intr | 435 |
| J721E_DEV_R5FSS0_CORE1 | intr | 435 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 180 | J721E_DEV_R5FSS0_CORE0 | intr | 436 |
| J721E_DEV_R5FSS0_CORE1 | intr | 436 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 181 | J721E_DEV_R5FSS0_CORE0 | intr | 437 |
| J721E_DEV_R5FSS0_CORE1 | intr | 437 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 182 | J721E_DEV_R5FSS0_CORE0 | intr | 438 |
| J721E_DEV_R5FSS0_CORE1 | intr | 438 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 183 | J721E_DEV_R5FSS0_CORE0 | intr | 439 |
| J721E_DEV_R5FSS0_CORE1 | intr | 439 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 184 | J721E_DEV_R5FSS0_CORE0 | intr | 440 |
| J721E_DEV_R5FSS0_CORE1 | intr | 440 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 185 | J721E_DEV_R5FSS0_CORE0 | intr | 441 |
| J721E_DEV_R5FSS0_CORE1 | intr | 441 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 186 | J721E_DEV_R5FSS0_CORE0 | intr | 442 |
| J721E_DEV_R5FSS0_CORE1 | intr | 442 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 187 | J721E_DEV_R5FSS0_CORE0 | intr | 443 |
| J721E_DEV_R5FSS0_CORE1 | intr | 443 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 188 | J721E_DEV_R5FSS0_CORE0 | intr | 444 |
| J721E_DEV_R5FSS0_CORE1 | intr | 444 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 189 | J721E_DEV_R5FSS0_CORE0 | intr | 445 |
| J721E_DEV_R5FSS0_CORE1 | intr | 445 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 190 | J721E_DEV_R5FSS0_CORE0 | intr | 446 |
| J721E_DEV_R5FSS0_CORE1 | intr | 446 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 191 | J721E_DEV_R5FSS0_CORE0 | intr | 447 |
| J721E_DEV_R5FSS0_CORE1 | intr | 447 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 192 | J721E_DEV_R5FSS0_CORE0 | intr | 448 |
| J721E_DEV_R5FSS0_CORE1 | intr | 448 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 193 | J721E_DEV_R5FSS0_CORE0 | intr | 449 |
| J721E_DEV_R5FSS0_CORE1 | intr | 449 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 194 | J721E_DEV_R5FSS0_CORE0 | intr | 450 |
| J721E_DEV_R5FSS0_CORE1 | intr | 450 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 195 | J721E_DEV_R5FSS0_CORE0 | intr | 451 |
| J721E_DEV_R5FSS0_CORE1 | intr | 451 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 196 | J721E_DEV_R5FSS0_CORE0 | intr | 452 |
| J721E_DEV_R5FSS0_CORE1 | intr | 452 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 197 | J721E_DEV_R5FSS0_CORE0 | intr | 453 |
| J721E_DEV_R5FSS0_CORE1 | intr | 453 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 198 | J721E_DEV_R5FSS0_CORE0 | intr | 454 |
| J721E_DEV_R5FSS0_CORE1 | intr | 454 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 199 | J721E_DEV_R5FSS0_CORE0 | intr | 455 |
| J721E_DEV_R5FSS0_CORE1 | intr | 455 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 200 | J721E_DEV_R5FSS0_CORE0 | intr | 456 |
| J721E_DEV_R5FSS0_CORE1 | intr | 456 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 201 | J721E_DEV_R5FSS0_CORE0 | intr | 457 |
| J721E_DEV_R5FSS0_CORE1 | intr | 457 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 202 | J721E_DEV_R5FSS0_CORE0 | intr | 458 |
| J721E_DEV_R5FSS0_CORE1 | intr | 458 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 203 | J721E_DEV_R5FSS0_CORE0 | intr | 459 |
| J721E_DEV_R5FSS0_CORE1 | intr | 459 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 204 | J721E_DEV_R5FSS0_CORE0 | intr | 460 |
| J721E_DEV_R5FSS0_CORE1 | intr | 460 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 205 | J721E_DEV_R5FSS0_CORE0 | intr | 461 |
| J721E_DEV_R5FSS0_CORE1 | intr | 461 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 206 | J721E_DEV_R5FSS0_CORE0 | intr | 462 |
| J721E_DEV_R5FSS0_CORE1 | intr | 462 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 207 | J721E_DEV_R5FSS0_CORE0 | intr | 463 |
| J721E_DEV_R5FSS0_CORE1 | intr | 463 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 208 | J721E_DEV_R5FSS0_CORE0 | intr | 464 |
| J721E_DEV_R5FSS0_CORE1 | intr | 464 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 209 | J721E_DEV_R5FSS0_CORE0 | intr | 465 |
| J721E_DEV_R5FSS0_CORE1 | intr | 465 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 210 | J721E_DEV_R5FSS0_CORE0 | intr | 466 |
| J721E_DEV_R5FSS0_CORE1 | intr | 466 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 211 | J721E_DEV_R5FSS0_CORE0 | intr | 467 |
| J721E_DEV_R5FSS0_CORE1 | intr | 467 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 212 | J721E_DEV_R5FSS0_CORE0 | intr | 468 |
| J721E_DEV_R5FSS0_CORE1 | intr | 468 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 213 | J721E_DEV_R5FSS0_CORE0 | intr | 469 |
| J721E_DEV_R5FSS0_CORE1 | intr | 469 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 214 | J721E_DEV_R5FSS0_CORE0 | intr | 470 |
| J721E_DEV_R5FSS0_CORE1 | intr | 470 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 215 | J721E_DEV_R5FSS0_CORE0 | intr | 471 |
| J721E_DEV_R5FSS0_CORE1 | intr | 471 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 216 | J721E_DEV_R5FSS0_CORE0 | intr | 472 |
| J721E_DEV_R5FSS0_CORE1 | intr | 472 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 217 | J721E_DEV_R5FSS0_CORE0 | intr | 473 |
| J721E_DEV_R5FSS0_CORE1 | intr | 473 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 218 | J721E_DEV_R5FSS0_CORE0 | intr | 474 |
| J721E_DEV_R5FSS0_CORE1 | intr | 474 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 219 | J721E_DEV_R5FSS0_CORE0 | intr | 475 |
| J721E_DEV_R5FSS0_CORE1 | intr | 475 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 220 | J721E_DEV_R5FSS0_CORE0 | intr | 476 |
| J721E_DEV_R5FSS0_CORE1 | intr | 476 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 221 | J721E_DEV_R5FSS0_CORE0 | intr | 477 |
| J721E_DEV_R5FSS0_CORE1 | intr | 477 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 222 | J721E_DEV_R5FSS0_CORE0 | intr | 478 |
| J721E_DEV_R5FSS0_CORE1 | intr | 478 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 223 | J721E_DEV_R5FSS0_CORE0 | intr | 479 |
| J721E_DEV_R5FSS0_CORE1 | intr | 479 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 224 | J721E_DEV_R5FSS0_CORE0 | intr | 480 |
| J721E_DEV_R5FSS0_CORE1 | intr | 480 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 225 | J721E_DEV_R5FSS0_CORE0 | intr | 481 |
| J721E_DEV_R5FSS0_CORE1 | intr | 481 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 226 | J721E_DEV_R5FSS0_CORE0 | intr | 482 |
| J721E_DEV_R5FSS0_CORE1 | intr | 482 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 227 | J721E_DEV_R5FSS0_CORE0 | intr | 483 |
| J721E_DEV_R5FSS0_CORE1 | intr | 483 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 228 | J721E_DEV_R5FSS0_CORE0 | intr | 484 |
| J721E_DEV_R5FSS0_CORE1 | intr | 484 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 229 | J721E_DEV_R5FSS0_CORE0 | intr | 485 |
| J721E_DEV_R5FSS0_CORE1 | intr | 485 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 230 | J721E_DEV_R5FSS0_CORE0 | intr | 486 |
| J721E_DEV_R5FSS0_CORE1 | intr | 486 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 231 | J721E_DEV_R5FSS0_CORE0 | intr | 487 |
| J721E_DEV_R5FSS0_CORE1 | intr | 487 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 232 | J721E_DEV_R5FSS0_CORE0 | intr | 488 |
| J721E_DEV_R5FSS0_CORE1 | intr | 488 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 233 | J721E_DEV_R5FSS0_CORE0 | intr | 489 |
| J721E_DEV_R5FSS0_CORE1 | intr | 489 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 234 | J721E_DEV_R5FSS0_CORE0 | intr | 490 |
| J721E_DEV_R5FSS0_CORE1 | intr | 490 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 235 | J721E_DEV_R5FSS0_CORE0 | intr | 491 |
| J721E_DEV_R5FSS0_CORE1 | intr | 491 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 236 | J721E_DEV_R5FSS0_CORE0 | intr | 492 |
| J721E_DEV_R5FSS0_CORE1 | intr | 492 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 237 | J721E_DEV_R5FSS0_CORE0 | intr | 493 |
| J721E_DEV_R5FSS0_CORE1 | intr | 493 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 238 | J721E_DEV_R5FSS0_CORE0 | intr | 494 |
| J721E_DEV_R5FSS0_CORE1 | intr | 494 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 239 | J721E_DEV_R5FSS0_CORE0 | intr | 495 |
| J721E_DEV_R5FSS0_CORE1 | intr | 495 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 240 | J721E_DEV_R5FSS0_CORE0 | intr | 496 |
| J721E_DEV_R5FSS0_CORE1 | intr | 496 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 241 | J721E_DEV_R5FSS0_CORE0 | intr | 497 |
| J721E_DEV_R5FSS0_CORE1 | intr | 497 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 242 | J721E_DEV_R5FSS0_CORE0 | intr | 498 |
| J721E_DEV_R5FSS0_CORE1 | intr | 498 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 243 | J721E_DEV_R5FSS0_CORE0 | intr | 499 |
| J721E_DEV_R5FSS0_CORE1 | intr | 499 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 244 | J721E_DEV_R5FSS0_CORE0 | intr | 500 |
| J721E_DEV_R5FSS0_CORE1 | intr | 500 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 245 | J721E_DEV_R5FSS0_CORE0 | intr | 501 |
| J721E_DEV_R5FSS0_CORE1 | intr | 501 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 246 | J721E_DEV_R5FSS0_CORE0 | intr | 502 |
| J721E_DEV_R5FSS0_CORE1 | intr | 502 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 247 | J721E_DEV_R5FSS0_CORE0 | intr | 503 |
| J721E_DEV_R5FSS0_CORE1 | intr | 503 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 248 | J721E_DEV_R5FSS0_CORE0 | intr | 504 |
| J721E_DEV_R5FSS0_CORE1 | intr | 504 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 249 | J721E_DEV_R5FSS0_CORE0 | intr | 505 |
| J721E_DEV_R5FSS0_CORE1 | intr | 505 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 250 | J721E_DEV_R5FSS0_CORE0 | intr | 506 |
| J721E_DEV_R5FSS0_CORE1 | intr | 506 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 251 | J721E_DEV_R5FSS0_CORE0 | intr | 507 |
| J721E_DEV_R5FSS0_CORE1 | intr | 507 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 252 | J721E_DEV_R5FSS0_CORE0 | intr | 508 |
| J721E_DEV_R5FSS0_CORE1 | intr | 508 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 253 | J721E_DEV_R5FSS0_CORE0 | intr | 509 |
| J721E_DEV_R5FSS0_CORE1 | intr | 509 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 254 | J721E_DEV_R5FSS0_CORE0 | intr | 510 |
| J721E_DEV_R5FSS0_CORE1 | intr | 510 | |||
| J721E_DEV_R5FSS0_INTROUTER0 | 134 | 255 | J721E_DEV_R5FSS0_CORE0 | intr | 511 |
| J721E_DEV_R5FSS0_CORE1 | intr | 511 |
R5FSS1_INTROUTER0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 0 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 1 | J721E_DEV_USB1 | otgirq | 9 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 2 | J721E_DEV_USB1 | irq | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 3 | J721E_DEV_USB1 | irq | 2 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 4 | J721E_DEV_USB1 | irq | 3 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 5 | J721E_DEV_USB1 | irq | 4 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 6 | J721E_DEV_USB1 | irq | 5 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 7 | J721E_DEV_USB1 | irq | 6 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 8 | J721E_DEV_USB1 | irq | 7 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 9 | J721E_DEV_USB1 | irq | 8 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 10 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 11 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 12 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 13 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 14 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 15 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 16 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 17 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 18 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 19 | J721E_DEV_PCIE2 | pcie_legacy_pulse | 5 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 20 | J721E_DEV_PCIE2 | pcie_downstream_pulse | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 21 | J721E_DEV_PCIE2 | pcie_flr_pulse | 3 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 22 | J721E_DEV_PCIE2 | pcie_phy_level | 8 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 23 | J721E_DEV_PCIE2 | pcie_local_level | 7 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 24 | J721E_DEV_PCIE2 | pcie_error_pulse | 2 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 25 | J721E_DEV_PCIE2 | pcie_link_state_pulse | 6 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 26 | J721E_DEV_PCIE2 | pcie_pwr_state_pulse | 10 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 27 | J721E_DEV_PCIE2 | pcie_ptm_valid_pulse | 9 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 28 | J721E_DEV_PCIE2 | pcie_hot_reset_pulse | 4 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 29 | J721E_DEV_PCIE2 | pcie_cpts_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 30 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 4 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 31 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 5 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 32 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 6 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 33 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 7 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 34 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 8 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 35 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 9 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 36 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 10 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 37 | J721E_DEV_PRU_ICSSG0 | pr1_host_intr_pend | 11 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 38 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 4 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 39 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 5 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 40 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 6 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 41 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 7 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 42 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 8 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 43 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 9 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 44 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 10 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 45 | J721E_DEV_PRU_ICSSG1 | pr1_host_intr_pend | 11 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 46 | J721E_DEV_PRU_ICSSG0 | pr1_tx_sof_intr_req | 54 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 47 | J721E_DEV_PRU_ICSSG0 | pr1_tx_sof_intr_req | 55 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 48 | J721E_DEV_PRU_ICSSG0 | pr1_rx_sof_intr_req | 52 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 49 | J721E_DEV_PRU_ICSSG0 | pr1_rx_sof_intr_req | 53 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 50 | J721E_DEV_PRU_ICSSG1 | pr1_tx_sof_intr_req | 54 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 51 | J721E_DEV_PRU_ICSSG1 | pr1_tx_sof_intr_req | 55 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 52 | J721E_DEV_PRU_ICSSG1 | pr1_rx_sof_intr_req | 52 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 53 | J721E_DEV_PRU_ICSSG1 | pr1_rx_sof_intr_req | 53 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 54 | J721E_DEV_PCIE3 | pcie_legacy_pulse | 5 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 55 | J721E_DEV_PCIE3 | pcie_downstream_pulse | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 56 | J721E_DEV_PCIE3 | pcie_flr_pulse | 3 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 57 | J721E_DEV_PCIE3 | pcie_phy_level | 8 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 58 | J721E_DEV_PCIE3 | pcie_local_level | 7 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 59 | J721E_DEV_PCIE3 | pcie_error_pulse | 2 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 60 | J721E_DEV_PCIE3 | pcie_link_state_pulse | 6 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 61 | J721E_DEV_PCIE3 | pcie_pwr_state_pulse | 10 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 62 | J721E_DEV_PCIE3 | pcie_ptm_valid_pulse | 9 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 63 | J721E_DEV_PCIE3 | pcie_hot_reset_pulse | 4 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 64 | J721E_DEV_PCIE3 | pcie_cpts_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 65 | J721E_DEV_USB1 | host_system_error | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 66 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 67 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 68 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 69 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 70 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 2 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 71 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 3 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 72 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 4 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 73 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 5 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 74 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 6 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 75 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 7 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 76 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 8 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 77 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 9 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 78 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 10 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 79 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 11 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 80 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 12 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 81 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 13 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 82 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 14 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 83 | J721E_DEV_GPIOMUX_INTRTR0 | outp | 15 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 84 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 85 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 86 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 2 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 87 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 3 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 88 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 4 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 89 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 5 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 90 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 6 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 91 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 7 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 92 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 8 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 93 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 9 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 94 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 10 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 95 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 11 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 96 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 12 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 97 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 13 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 98 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 14 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 99 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_out_level | 15 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 100 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 16 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 101 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 17 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 102 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 18 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 103 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 19 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 104 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 20 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 105 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 21 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 106 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 22 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 107 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 23 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 108 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 24 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 109 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 25 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 110 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 26 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 111 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 27 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 112 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 28 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 113 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 29 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 114 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 30 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 115 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 31 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 116 | J721E_DEV_MCU_ADC12_16FFC0 | gen_level | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 117 | J721E_DEV_MCU_ADC12_16FFC1 | gen_level | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 118 | J721E_DEV_MCU_CPSW0 | stat_pend | 6 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 119 | J721E_DEV_MCU_CPSW0 | mdio_pend | 5 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 120 | J721E_DEV_MCU_CPSW0 | evnt_pend | 4 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 121 | J721E_DEV_MCU_DCC0 | intr_done_level | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 122 | J721E_DEV_MCU_DCC1 | intr_done_level | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 123 | J721E_DEV_MCU_DCC2 | intr_done_level | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 124 | J721E_DEV_MCU_TIMER0 | intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 125 | J721E_DEV_MCU_TIMER1 | intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 126 | J721E_DEV_MCU_TIMER2 | intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 127 | J721E_DEV_MCU_TIMER3 | intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 128 | J721E_DEV_MCU_TIMER4 | intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 129 | J721E_DEV_MCU_TIMER5 | intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 130 | J721E_DEV_MCU_TIMER6 | intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 131 | J721E_DEV_MCU_TIMER7 | intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 132 | J721E_DEV_MCU_TIMER8 | intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 133 | J721E_DEV_MCU_TIMER9 | intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 134 | J721E_DEV_MCU_I2C0 | pointrpend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 135 | J721E_DEV_MCU_I2C1 | pointrpend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 136 | J721E_DEV_MCU_MCSPI0 | intr_spi | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 137 | J721E_DEV_MCU_MCSPI1 | intr_spi | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 138 | J721E_DEV_MCU_MCSPI2 | intr_spi | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 139 | J721E_DEV_MCU_UART0 | usart_irq | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 140 | J721E_DEV_MCU_I3C0 | i3c__int | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 141 | J721E_DEV_MCU_I3C1 | i3c__int | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 142 | J721E_DEV_MCU_FSS0_OSPI_0 | ospi_lvl_intr | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 143 | J721E_DEV_MCU_FSS0_OSPI_1 | ospi_lvl_intr | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 144 | J721E_DEV_MCU_FSS0_HYPERBUS1P0_0 | hpb_intr | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 145 | J721E_DEV_MCU_FSS0_FSAS_0 | otfa_intr_err_pend | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 146 | J721E_DEV_MCU_FSS0_FSAS_0 | ecc_intr_err_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 147 | J721E_DEV_MCU_SA2_UL0 | sa_ul_pka | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 148 | J721E_DEV_MCU_SA2_UL0 | sa_ul_trng | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 149 | J721E_DEV_MCU_ESM0 | esm_int_low_lvl | 2 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 150 | J721E_DEV_MCU_ESM0 | esm_int_hi_lvl | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 151 | J721E_DEV_MCU_ESM0 | esm_int_cfg_lvl | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 152 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 153 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 154 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 155 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 156 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 157 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 158 | J721E_DEV_WKUP_I2C0 | pointrpend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 159 | J721E_DEV_WKUP_UART0 | usart_irq | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 160 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 16 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 161 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 17 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 162 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 18 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 163 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 19 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 164 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 20 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 165 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 21 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 166 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 22 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 167 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 23 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 168 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 24 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 169 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 25 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 170 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 26 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 171 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 27 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 172 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 28 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 173 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 29 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 174 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 30 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 175 | J721E_DEV_WKUP_GPIOMUX_INTRTR0 | outp | 31 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 176 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 177 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 178 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 179 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 180 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 181 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 182 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 183 | J721E_DEV_I2C2 | pointrpend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 184 | J721E_DEV_I2C3 | pointrpend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 185 | J721E_DEV_I2C4 | pointrpend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 186 | J721E_DEV_I2C5 | pointrpend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 187 | J721E_DEV_I2C6 | pointrpend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 188 | J721E_DEV_UART3 | usart_irq | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 189 | J721E_DEV_UART4 | usart_irq | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 190 | J721E_DEV_UART5 | usart_irq | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 191 | J721E_DEV_UART6 | usart_irq | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 192 | J721E_DEV_UART7 | usart_irq | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 193 | J721E_DEV_UART8 | usart_irq | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 194 | J721E_DEV_UART9 | usart_irq | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 195 | J721E_DEV_MCSPI2 | intr_spi | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 196 | J721E_DEV_MCSPI3 | intr_spi | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 197 | J721E_DEV_MCSPI4 | intr_spi | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 198 | J721E_DEV_MCSPI5 | intr_spi | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 199 | J721E_DEV_MCSPI6 | intr_spi | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 200 | J721E_DEV_MCSPI7 | intr_spi | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 201 | J721E_DEV_I3C0 | i3c__int | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 202 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 203 | J721E_DEV_AASRC0 | err_level | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 204 | J721E_DEV_AASRC0 | infifo_level | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 205 | J721E_DEV_AASRC0 | ingroup_level | 2 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 206 | J721E_DEV_AASRC0 | outfifo_level | 3 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 207 | J721E_DEV_AASRC0 | outgroup_level | 4 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 208 | J721E_DEV_MCASP2 | xmit_intr_pend | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 209 | J721E_DEV_MCASP2 | rec_intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 210 | J721E_DEV_MCASP3 | xmit_intr_pend | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 211 | J721E_DEV_MCASP3 | rec_intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 212 | J721E_DEV_MCASP4 | xmit_intr_pend | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 213 | J721E_DEV_MCASP4 | rec_intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 214 | J721E_DEV_MCASP5 | xmit_intr_pend | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 215 | J721E_DEV_MCASP5 | rec_intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 216 | J721E_DEV_MCASP6 | xmit_intr_pend | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 217 | J721E_DEV_MCASP6 | rec_intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 218 | J721E_DEV_MCASP7 | xmit_intr_pend | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 219 | J721E_DEV_MCASP7 | rec_intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 220 | J721E_DEV_MCASP8 | xmit_intr_pend | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 221 | J721E_DEV_MCASP8 | rec_intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 222 | J721E_DEV_MCASP9 | xmit_intr_pend | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 223 | J721E_DEV_MCASP9 | rec_intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 224 | J721E_DEV_MCASP10 | xmit_intr_pend | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 225 | J721E_DEV_MCASP10 | rec_intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 226 | J721E_DEV_MCASP11 | xmit_intr_pend | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 227 | J721E_DEV_MCASP11 | rec_intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 228 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 229 | J721E_DEV_GPMC0 | gpmc_sinterrupt | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 230 | J721E_DEV_ELM0 | elm_porocpsinterrupt_lvl | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 231 | J721E_DEV_USB0 | otgirq | 9 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 232 | J721E_DEV_USB0 | irq | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 233 | J721E_DEV_USB0 | irq | 2 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 234 | J721E_DEV_USB0 | irq | 3 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 235 | J721E_DEV_USB0 | irq | 4 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 236 | J721E_DEV_USB0 | irq | 5 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 237 | J721E_DEV_USB0 | irq | 6 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 238 | J721E_DEV_USB0 | irq | 7 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 239 | J721E_DEV_USB0 | irq | 8 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 240 | J721E_DEV_TIMER0 | intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 241 | J721E_DEV_TIMER1 | intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 242 | J721E_DEV_TIMER2 | intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 243 | J721E_DEV_TIMER3 | intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 244 | J721E_DEV_TIMER4 | intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 245 | J721E_DEV_TIMER5 | intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 246 | J721E_DEV_TIMER6 | intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 247 | J721E_DEV_TIMER7 | intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 248 | J721E_DEV_TIMER8 | intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 249 | J721E_DEV_TIMER9 | intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 250 | J721E_DEV_TIMER10 | intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 251 | J721E_DEV_TIMER11 | intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 252 | J721E_DEV_PCIE1 | pcie_legacy_pulse | 5 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 253 | J721E_DEV_PCIE1 | pcie_downstream_pulse | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 254 | J721E_DEV_PCIE1 | pcie_flr_pulse | 3 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 255 | J721E_DEV_PCIE1 | pcie_phy_level | 8 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 256 | J721E_DEV_PCIE1 | pcie_local_level | 7 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 257 | J721E_DEV_PCIE1 | pcie_error_pulse | 2 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 258 | J721E_DEV_PCIE1 | pcie_link_state_pulse | 6 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 259 | J721E_DEV_PCIE1 | pcie_pwr_state_pulse | 10 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 260 | J721E_DEV_PCIE1 | pcie_ptm_valid_pulse | 9 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 261 | J721E_DEV_PCIE1 | pcie_hot_reset_pulse | 4 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 262 | J721E_DEV_PCIE1 | pcie_cpts_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 263 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 264 | J721E_DEV_DDR0 | ddrss_controller | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 265 | J721E_DEV_DDR0 | ddrss_v2a_other_err_lvl | 3 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 266 | J721E_DEV_DDR0 | ddrss_hs_phy_global_error | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 267 | J721E_DEV_DDR0 | ddrss_pll_freq_change_req | 2 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 268 | J721E_DEV_CSI_TX_IF0 | csi_interrupt | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 269 | J721E_DEV_CSI_TX_IF0 | csi_level | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 270 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 271 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 272 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 273 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 274 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 275 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 276 | J721E_DEV_VPFE0 | ccdc_intr_pend | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 277 | J721E_DEV_VPFE0 | rat_exp_intr | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 278 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 279 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 280 | J721E_DEV_DCC0 | intr_done_level | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 281 | J721E_DEV_DCC1 | intr_done_level | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 282 | J721E_DEV_DCC2 | intr_done_level | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 283 | J721E_DEV_DCC3 | intr_done_level | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 284 | J721E_DEV_DCC4 | intr_done_level | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 285 | J721E_DEV_DCC5 | intr_done_level | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 286 | J721E_DEV_DCC6 | intr_done_level | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 287 | J721E_DEV_DCC7 | intr_done_level | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 288 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 289 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 290 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 2 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 291 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 3 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 292 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 4 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 293 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 5 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 294 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 6 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 295 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 7 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 296 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 8 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 297 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 9 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 298 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 10 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 299 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 11 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 300 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 12 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 301 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 13 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 302 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 14 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 303 | J721E_DEV_CMPEVENT_INTRTR0 | outp | 15 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 304 | J721E_DEV_DCC8 | intr_done_level | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 305 | J721E_DEV_DCC9 | intr_done_level | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 306 | J721E_DEV_DCC10 | intr_done_level | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 307 | J721E_DEV_DCC11 | intr_done_level | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 308 | J721E_DEV_DCC12 | intr_done_level | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 309 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 310 | J721E_DEV_MMCSD1 | emmcsdss_intr | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 311 | J721E_DEV_MMCSD2 | emmcsdss_intr | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 312 | J721E_DEV_UFS0 | ufs_intr | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 313 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 314 | J721E_DEV_SA2_UL0 | sa_ul_pka | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 315 | J721E_DEV_SA2_UL0 | sa_ul_trng | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 316 | J721E_DEV_ECAP0 | ecap_int | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 317 | J721E_DEV_ECAP1 | ecap_int | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 318 | J721E_DEV_ECAP2 | ecap_int | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 319 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 320 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 321 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 322 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 323 | J721E_DEV_USB0 | host_system_error | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 324 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 325 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 326 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 327 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 328 | J721E_DEV_WKUP_VTM0 | therm_lvl_gt_th1_intr | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 329 | J721E_DEV_WKUP_VTM0 | therm_lvl_gt_th2_intr | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 330 | J721E_DEV_WKUP_VTM0 | therm_lvl_lt_th0_intr | 2 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 331 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 332 | J721E_DEV_COMPUTE_CLUSTER0 | gic_output_waker_gic_pwr0_wake_request | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 333 | J721E_DEV_COMPUTE_CLUSTER0 | gic_output_waker_gic_pwr0_wake_request | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 334 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 335 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 336 | J721E_DEV_MCU_MCAN0 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 337 | J721E_DEV_MCU_MCAN0 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 338 | J721E_DEV_MCU_MCAN0 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 339 | J721E_DEV_MCU_MCAN1 | mcanss_mcan_lvl_int | 1 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 340 | J721E_DEV_MCU_MCAN1 | mcanss_mcan_lvl_int | 2 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 341 | J721E_DEV_MCU_MCAN1 | mcanss_ext_ts_rollover_lvl_int | 0 |
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 342 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 343 | Use TRM - Not managed by TISCI |
R5FSS1_INTROUTER0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 0 | J721E_DEV_R5FSS1_CORE0 | intr | 256 |
| J721E_DEV_R5FSS1_CORE1 | intr | 256 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 1 | J721E_DEV_R5FSS1_CORE0 | intr | 257 |
| J721E_DEV_R5FSS1_CORE1 | intr | 257 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 2 | J721E_DEV_R5FSS1_CORE0 | intr | 258 |
| J721E_DEV_R5FSS1_CORE1 | intr | 258 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 3 | J721E_DEV_R5FSS1_CORE0 | intr | 259 |
| J721E_DEV_R5FSS1_CORE1 | intr | 259 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 4 | J721E_DEV_R5FSS1_CORE0 | intr | 260 |
| J721E_DEV_R5FSS1_CORE1 | intr | 260 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 5 | J721E_DEV_R5FSS1_CORE0 | intr | 261 |
| J721E_DEV_R5FSS1_CORE1 | intr | 261 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 6 | J721E_DEV_R5FSS1_CORE0 | intr | 262 |
| J721E_DEV_R5FSS1_CORE1 | intr | 262 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 7 | J721E_DEV_R5FSS1_CORE0 | intr | 263 |
| J721E_DEV_R5FSS1_CORE1 | intr | 263 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 8 | J721E_DEV_R5FSS1_CORE0 | intr | 264 |
| J721E_DEV_R5FSS1_CORE1 | intr | 264 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 9 | J721E_DEV_R5FSS1_CORE0 | intr | 265 |
| J721E_DEV_R5FSS1_CORE1 | intr | 265 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 10 | J721E_DEV_R5FSS1_CORE0 | intr | 266 |
| J721E_DEV_R5FSS1_CORE1 | intr | 266 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 11 | J721E_DEV_R5FSS1_CORE0 | intr | 267 |
| J721E_DEV_R5FSS1_CORE1 | intr | 267 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 12 | J721E_DEV_R5FSS1_CORE0 | intr | 268 |
| J721E_DEV_R5FSS1_CORE1 | intr | 268 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 13 | J721E_DEV_R5FSS1_CORE0 | intr | 269 |
| J721E_DEV_R5FSS1_CORE1 | intr | 269 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 14 | J721E_DEV_R5FSS1_CORE0 | intr | 270 |
| J721E_DEV_R5FSS1_CORE1 | intr | 270 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 15 | J721E_DEV_R5FSS1_CORE0 | intr | 271 |
| J721E_DEV_R5FSS1_CORE1 | intr | 271 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 16 | J721E_DEV_R5FSS1_CORE0 | intr | 272 |
| J721E_DEV_R5FSS1_CORE1 | intr | 272 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 17 | J721E_DEV_R5FSS1_CORE0 | intr | 273 |
| J721E_DEV_R5FSS1_CORE1 | intr | 273 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 18 | J721E_DEV_R5FSS1_CORE0 | intr | 274 |
| J721E_DEV_R5FSS1_CORE1 | intr | 274 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 19 | J721E_DEV_R5FSS1_CORE0 | intr | 275 |
| J721E_DEV_R5FSS1_CORE1 | intr | 275 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 20 | J721E_DEV_R5FSS1_CORE0 | intr | 276 |
| J721E_DEV_R5FSS1_CORE1 | intr | 276 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 21 | J721E_DEV_R5FSS1_CORE0 | intr | 277 |
| J721E_DEV_R5FSS1_CORE1 | intr | 277 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 22 | J721E_DEV_R5FSS1_CORE0 | intr | 278 |
| J721E_DEV_R5FSS1_CORE1 | intr | 278 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 23 | J721E_DEV_R5FSS1_CORE0 | intr | 279 |
| J721E_DEV_R5FSS1_CORE1 | intr | 279 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 24 | J721E_DEV_R5FSS1_CORE0 | intr | 280 |
| J721E_DEV_R5FSS1_CORE1 | intr | 280 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 25 | J721E_DEV_R5FSS1_CORE0 | intr | 281 |
| J721E_DEV_R5FSS1_CORE1 | intr | 281 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 26 | J721E_DEV_R5FSS1_CORE0 | intr | 282 |
| J721E_DEV_R5FSS1_CORE1 | intr | 282 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 27 | J721E_DEV_R5FSS1_CORE0 | intr | 283 |
| J721E_DEV_R5FSS1_CORE1 | intr | 283 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 28 | J721E_DEV_R5FSS1_CORE0 | intr | 284 |
| J721E_DEV_R5FSS1_CORE1 | intr | 284 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 29 | J721E_DEV_R5FSS1_CORE0 | intr | 285 |
| J721E_DEV_R5FSS1_CORE1 | intr | 285 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 30 | J721E_DEV_R5FSS1_CORE0 | intr | 286 |
| J721E_DEV_R5FSS1_CORE1 | intr | 286 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 31 | J721E_DEV_R5FSS1_CORE0 | intr | 287 |
| J721E_DEV_R5FSS1_CORE1 | intr | 287 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 32 | J721E_DEV_R5FSS1_CORE0 | intr | 288 |
| J721E_DEV_R5FSS1_CORE1 | intr | 288 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 33 | J721E_DEV_R5FSS1_CORE0 | intr | 289 |
| J721E_DEV_R5FSS1_CORE1 | intr | 289 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 34 | J721E_DEV_R5FSS1_CORE0 | intr | 290 |
| J721E_DEV_R5FSS1_CORE1 | intr | 290 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 35 | J721E_DEV_R5FSS1_CORE0 | intr | 291 |
| J721E_DEV_R5FSS1_CORE1 | intr | 291 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 36 | J721E_DEV_R5FSS1_CORE0 | intr | 292 |
| J721E_DEV_R5FSS1_CORE1 | intr | 292 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 37 | J721E_DEV_R5FSS1_CORE0 | intr | 293 |
| J721E_DEV_R5FSS1_CORE1 | intr | 293 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 38 | J721E_DEV_R5FSS1_CORE0 | intr | 294 |
| J721E_DEV_R5FSS1_CORE1 | intr | 294 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 39 | J721E_DEV_R5FSS1_CORE0 | intr | 295 |
| J721E_DEV_R5FSS1_CORE1 | intr | 295 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 40 | J721E_DEV_R5FSS1_CORE0 | intr | 296 |
| J721E_DEV_R5FSS1_CORE1 | intr | 296 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 41 | J721E_DEV_R5FSS1_CORE0 | intr | 297 |
| J721E_DEV_R5FSS1_CORE1 | intr | 297 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 42 | J721E_DEV_R5FSS1_CORE0 | intr | 298 |
| J721E_DEV_R5FSS1_CORE1 | intr | 298 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 43 | J721E_DEV_R5FSS1_CORE0 | intr | 299 |
| J721E_DEV_R5FSS1_CORE1 | intr | 299 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 44 | J721E_DEV_R5FSS1_CORE0 | intr | 300 |
| J721E_DEV_R5FSS1_CORE1 | intr | 300 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 45 | J721E_DEV_R5FSS1_CORE0 | intr | 301 |
| J721E_DEV_R5FSS1_CORE1 | intr | 301 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 46 | J721E_DEV_R5FSS1_CORE0 | intr | 302 |
| J721E_DEV_R5FSS1_CORE1 | intr | 302 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 47 | J721E_DEV_R5FSS1_CORE0 | intr | 303 |
| J721E_DEV_R5FSS1_CORE1 | intr | 303 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 48 | J721E_DEV_R5FSS1_CORE0 | intr | 304 |
| J721E_DEV_R5FSS1_CORE1 | intr | 304 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 49 | J721E_DEV_R5FSS1_CORE0 | intr | 305 |
| J721E_DEV_R5FSS1_CORE1 | intr | 305 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 50 | J721E_DEV_R5FSS1_CORE0 | intr | 306 |
| J721E_DEV_R5FSS1_CORE1 | intr | 306 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 51 | J721E_DEV_R5FSS1_CORE0 | intr | 307 |
| J721E_DEV_R5FSS1_CORE1 | intr | 307 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 52 | J721E_DEV_R5FSS1_CORE0 | intr | 308 |
| J721E_DEV_R5FSS1_CORE1 | intr | 308 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 53 | J721E_DEV_R5FSS1_CORE0 | intr | 309 |
| J721E_DEV_R5FSS1_CORE1 | intr | 309 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 54 | J721E_DEV_R5FSS1_CORE0 | intr | 310 |
| J721E_DEV_R5FSS1_CORE1 | intr | 310 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 55 | J721E_DEV_R5FSS1_CORE0 | intr | 311 |
| J721E_DEV_R5FSS1_CORE1 | intr | 311 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 56 | J721E_DEV_R5FSS1_CORE0 | intr | 312 |
| J721E_DEV_R5FSS1_CORE1 | intr | 312 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 57 | J721E_DEV_R5FSS1_CORE0 | intr | 313 |
| J721E_DEV_R5FSS1_CORE1 | intr | 313 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 58 | J721E_DEV_R5FSS1_CORE0 | intr | 314 |
| J721E_DEV_R5FSS1_CORE1 | intr | 314 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 59 | J721E_DEV_R5FSS1_CORE0 | intr | 315 |
| J721E_DEV_R5FSS1_CORE1 | intr | 315 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 60 | J721E_DEV_R5FSS1_CORE0 | intr | 316 |
| J721E_DEV_R5FSS1_CORE1 | intr | 316 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 61 | J721E_DEV_R5FSS1_CORE0 | intr | 317 |
| J721E_DEV_R5FSS1_CORE1 | intr | 317 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 62 | J721E_DEV_R5FSS1_CORE0 | intr | 318 |
| J721E_DEV_R5FSS1_CORE1 | intr | 318 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 63 | J721E_DEV_R5FSS1_CORE0 | intr | 319 |
| J721E_DEV_R5FSS1_CORE1 | intr | 319 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 64 | J721E_DEV_R5FSS1_CORE0 | intr | 320 |
| J721E_DEV_R5FSS1_CORE1 | intr | 320 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 65 | J721E_DEV_R5FSS1_CORE0 | intr | 321 |
| J721E_DEV_R5FSS1_CORE1 | intr | 321 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 66 | J721E_DEV_R5FSS1_CORE0 | intr | 322 |
| J721E_DEV_R5FSS1_CORE1 | intr | 322 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 67 | J721E_DEV_R5FSS1_CORE0 | intr | 323 |
| J721E_DEV_R5FSS1_CORE1 | intr | 323 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 68 | J721E_DEV_R5FSS1_CORE0 | intr | 324 |
| J721E_DEV_R5FSS1_CORE1 | intr | 324 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 69 | J721E_DEV_R5FSS1_CORE0 | intr | 325 |
| J721E_DEV_R5FSS1_CORE1 | intr | 325 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 70 | J721E_DEV_R5FSS1_CORE0 | intr | 326 |
| J721E_DEV_R5FSS1_CORE1 | intr | 326 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 71 | J721E_DEV_R5FSS1_CORE0 | intr | 327 |
| J721E_DEV_R5FSS1_CORE1 | intr | 327 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 72 | J721E_DEV_R5FSS1_CORE0 | intr | 328 |
| J721E_DEV_R5FSS1_CORE1 | intr | 328 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 73 | J721E_DEV_R5FSS1_CORE0 | intr | 329 |
| J721E_DEV_R5FSS1_CORE1 | intr | 329 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 74 | J721E_DEV_R5FSS1_CORE0 | intr | 330 |
| J721E_DEV_R5FSS1_CORE1 | intr | 330 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 75 | J721E_DEV_R5FSS1_CORE0 | intr | 331 |
| J721E_DEV_R5FSS1_CORE1 | intr | 331 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 76 | J721E_DEV_R5FSS1_CORE0 | intr | 332 |
| J721E_DEV_R5FSS1_CORE1 | intr | 332 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 77 | J721E_DEV_R5FSS1_CORE0 | intr | 333 |
| J721E_DEV_R5FSS1_CORE1 | intr | 333 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 78 | J721E_DEV_R5FSS1_CORE0 | intr | 334 |
| J721E_DEV_R5FSS1_CORE1 | intr | 334 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 79 | J721E_DEV_R5FSS1_CORE0 | intr | 335 |
| J721E_DEV_R5FSS1_CORE1 | intr | 335 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 80 | J721E_DEV_R5FSS1_CORE0 | intr | 336 |
| J721E_DEV_R5FSS1_CORE1 | intr | 336 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 81 | J721E_DEV_R5FSS1_CORE0 | intr | 337 |
| J721E_DEV_R5FSS1_CORE1 | intr | 337 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 82 | J721E_DEV_R5FSS1_CORE0 | intr | 338 |
| J721E_DEV_R5FSS1_CORE1 | intr | 338 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 83 | J721E_DEV_R5FSS1_CORE0 | intr | 339 |
| J721E_DEV_R5FSS1_CORE1 | intr | 339 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 84 | J721E_DEV_R5FSS1_CORE0 | intr | 340 |
| J721E_DEV_R5FSS1_CORE1 | intr | 340 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 85 | J721E_DEV_R5FSS1_CORE0 | intr | 341 |
| J721E_DEV_R5FSS1_CORE1 | intr | 341 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 86 | J721E_DEV_R5FSS1_CORE0 | intr | 342 |
| J721E_DEV_R5FSS1_CORE1 | intr | 342 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 87 | J721E_DEV_R5FSS1_CORE0 | intr | 343 |
| J721E_DEV_R5FSS1_CORE1 | intr | 343 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 88 | J721E_DEV_R5FSS1_CORE0 | intr | 344 |
| J721E_DEV_R5FSS1_CORE1 | intr | 344 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 89 | J721E_DEV_R5FSS1_CORE0 | intr | 345 |
| J721E_DEV_R5FSS1_CORE1 | intr | 345 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 90 | J721E_DEV_R5FSS1_CORE0 | intr | 346 |
| J721E_DEV_R5FSS1_CORE1 | intr | 346 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 91 | J721E_DEV_R5FSS1_CORE0 | intr | 347 |
| J721E_DEV_R5FSS1_CORE1 | intr | 347 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 92 | J721E_DEV_R5FSS1_CORE0 | intr | 348 |
| J721E_DEV_R5FSS1_CORE1 | intr | 348 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 93 | J721E_DEV_R5FSS1_CORE0 | intr | 349 |
| J721E_DEV_R5FSS1_CORE1 | intr | 349 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 94 | J721E_DEV_R5FSS1_CORE0 | intr | 350 |
| J721E_DEV_R5FSS1_CORE1 | intr | 350 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 95 | J721E_DEV_R5FSS1_CORE0 | intr | 351 |
| J721E_DEV_R5FSS1_CORE1 | intr | 351 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 96 | J721E_DEV_R5FSS1_CORE0 | intr | 352 |
| J721E_DEV_R5FSS1_CORE1 | intr | 352 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 97 | J721E_DEV_R5FSS1_CORE0 | intr | 353 |
| J721E_DEV_R5FSS1_CORE1 | intr | 353 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 98 | J721E_DEV_R5FSS1_CORE0 | intr | 354 |
| J721E_DEV_R5FSS1_CORE1 | intr | 354 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 99 | J721E_DEV_R5FSS1_CORE0 | intr | 355 |
| J721E_DEV_R5FSS1_CORE1 | intr | 355 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 100 | J721E_DEV_R5FSS1_CORE0 | intr | 356 |
| J721E_DEV_R5FSS1_CORE1 | intr | 356 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 101 | J721E_DEV_R5FSS1_CORE0 | intr | 357 |
| J721E_DEV_R5FSS1_CORE1 | intr | 357 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 102 | J721E_DEV_R5FSS1_CORE0 | intr | 358 |
| J721E_DEV_R5FSS1_CORE1 | intr | 358 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 103 | J721E_DEV_R5FSS1_CORE0 | intr | 359 |
| J721E_DEV_R5FSS1_CORE1 | intr | 359 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 104 | J721E_DEV_R5FSS1_CORE0 | intr | 360 |
| J721E_DEV_R5FSS1_CORE1 | intr | 360 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 105 | J721E_DEV_R5FSS1_CORE0 | intr | 361 |
| J721E_DEV_R5FSS1_CORE1 | intr | 361 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 106 | J721E_DEV_R5FSS1_CORE0 | intr | 362 |
| J721E_DEV_R5FSS1_CORE1 | intr | 362 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 107 | J721E_DEV_R5FSS1_CORE0 | intr | 363 |
| J721E_DEV_R5FSS1_CORE1 | intr | 363 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 108 | J721E_DEV_R5FSS1_CORE0 | intr | 364 |
| J721E_DEV_R5FSS1_CORE1 | intr | 364 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 109 | J721E_DEV_R5FSS1_CORE0 | intr | 365 |
| J721E_DEV_R5FSS1_CORE1 | intr | 365 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 110 | J721E_DEV_R5FSS1_CORE0 | intr | 366 |
| J721E_DEV_R5FSS1_CORE1 | intr | 366 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 111 | J721E_DEV_R5FSS1_CORE0 | intr | 367 |
| J721E_DEV_R5FSS1_CORE1 | intr | 367 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 112 | J721E_DEV_R5FSS1_CORE0 | intr | 368 |
| J721E_DEV_R5FSS1_CORE1 | intr | 368 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 113 | J721E_DEV_R5FSS1_CORE0 | intr | 369 |
| J721E_DEV_R5FSS1_CORE1 | intr | 369 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 114 | J721E_DEV_R5FSS1_CORE0 | intr | 370 |
| J721E_DEV_R5FSS1_CORE1 | intr | 370 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 115 | J721E_DEV_R5FSS1_CORE0 | intr | 371 |
| J721E_DEV_R5FSS1_CORE1 | intr | 371 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 116 | J721E_DEV_R5FSS1_CORE0 | intr | 372 |
| J721E_DEV_R5FSS1_CORE1 | intr | 372 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 117 | J721E_DEV_R5FSS1_CORE0 | intr | 373 |
| J721E_DEV_R5FSS1_CORE1 | intr | 373 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 118 | J721E_DEV_R5FSS1_CORE0 | intr | 374 |
| J721E_DEV_R5FSS1_CORE1 | intr | 374 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 119 | J721E_DEV_R5FSS1_CORE0 | intr | 375 |
| J721E_DEV_R5FSS1_CORE1 | intr | 375 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 120 | J721E_DEV_R5FSS1_CORE0 | intr | 376 |
| J721E_DEV_R5FSS1_CORE1 | intr | 376 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 121 | J721E_DEV_R5FSS1_CORE0 | intr | 377 |
| J721E_DEV_R5FSS1_CORE1 | intr | 377 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 122 | J721E_DEV_R5FSS1_CORE0 | intr | 378 |
| J721E_DEV_R5FSS1_CORE1 | intr | 378 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 123 | J721E_DEV_R5FSS1_CORE0 | intr | 379 |
| J721E_DEV_R5FSS1_CORE1 | intr | 379 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 124 | J721E_DEV_R5FSS1_CORE0 | intr | 380 |
| J721E_DEV_R5FSS1_CORE1 | intr | 380 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 125 | J721E_DEV_R5FSS1_CORE0 | intr | 381 |
| J721E_DEV_R5FSS1_CORE1 | intr | 381 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 126 | J721E_DEV_R5FSS1_CORE0 | intr | 382 |
| J721E_DEV_R5FSS1_CORE1 | intr | 382 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 127 | J721E_DEV_R5FSS1_CORE0 | intr | 383 |
| J721E_DEV_R5FSS1_CORE1 | intr | 383 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 128 | J721E_DEV_R5FSS1_CORE0 | intr | 384 |
| J721E_DEV_R5FSS1_CORE1 | intr | 384 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 129 | J721E_DEV_R5FSS1_CORE0 | intr | 385 |
| J721E_DEV_R5FSS1_CORE1 | intr | 385 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 130 | J721E_DEV_R5FSS1_CORE0 | intr | 386 |
| J721E_DEV_R5FSS1_CORE1 | intr | 386 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 131 | J721E_DEV_R5FSS1_CORE0 | intr | 387 |
| J721E_DEV_R5FSS1_CORE1 | intr | 387 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 132 | J721E_DEV_R5FSS1_CORE0 | intr | 388 |
| J721E_DEV_R5FSS1_CORE1 | intr | 388 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 133 | J721E_DEV_R5FSS1_CORE0 | intr | 389 |
| J721E_DEV_R5FSS1_CORE1 | intr | 389 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 134 | J721E_DEV_R5FSS1_CORE0 | intr | 390 |
| J721E_DEV_R5FSS1_CORE1 | intr | 390 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 135 | J721E_DEV_R5FSS1_CORE0 | intr | 391 |
| J721E_DEV_R5FSS1_CORE1 | intr | 391 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 136 | J721E_DEV_R5FSS1_CORE0 | intr | 392 |
| J721E_DEV_R5FSS1_CORE1 | intr | 392 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 137 | J721E_DEV_R5FSS1_CORE0 | intr | 393 |
| J721E_DEV_R5FSS1_CORE1 | intr | 393 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 138 | J721E_DEV_R5FSS1_CORE0 | intr | 394 |
| J721E_DEV_R5FSS1_CORE1 | intr | 394 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 139 | J721E_DEV_R5FSS1_CORE0 | intr | 395 |
| J721E_DEV_R5FSS1_CORE1 | intr | 395 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 140 | J721E_DEV_R5FSS1_CORE0 | intr | 396 |
| J721E_DEV_R5FSS1_CORE1 | intr | 396 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 141 | J721E_DEV_R5FSS1_CORE0 | intr | 397 |
| J721E_DEV_R5FSS1_CORE1 | intr | 397 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 142 | J721E_DEV_R5FSS1_CORE0 | intr | 398 |
| J721E_DEV_R5FSS1_CORE1 | intr | 398 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 143 | J721E_DEV_R5FSS1_CORE0 | intr | 399 |
| J721E_DEV_R5FSS1_CORE1 | intr | 399 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 144 | J721E_DEV_R5FSS1_CORE0 | intr | 400 |
| J721E_DEV_R5FSS1_CORE1 | intr | 400 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 145 | J721E_DEV_R5FSS1_CORE0 | intr | 401 |
| J721E_DEV_R5FSS1_CORE1 | intr | 401 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 146 | J721E_DEV_R5FSS1_CORE0 | intr | 402 |
| J721E_DEV_R5FSS1_CORE1 | intr | 402 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 147 | J721E_DEV_R5FSS1_CORE0 | intr | 403 |
| J721E_DEV_R5FSS1_CORE1 | intr | 403 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 148 | J721E_DEV_R5FSS1_CORE0 | intr | 404 |
| J721E_DEV_R5FSS1_CORE1 | intr | 404 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 149 | J721E_DEV_R5FSS1_CORE0 | intr | 405 |
| J721E_DEV_R5FSS1_CORE1 | intr | 405 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 150 | J721E_DEV_R5FSS1_CORE0 | intr | 406 |
| J721E_DEV_R5FSS1_CORE1 | intr | 406 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 151 | J721E_DEV_R5FSS1_CORE0 | intr | 407 |
| J721E_DEV_R5FSS1_CORE1 | intr | 407 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 152 | J721E_DEV_R5FSS1_CORE0 | intr | 408 |
| J721E_DEV_R5FSS1_CORE1 | intr | 408 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 153 | J721E_DEV_R5FSS1_CORE0 | intr | 409 |
| J721E_DEV_R5FSS1_CORE1 | intr | 409 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 154 | J721E_DEV_R5FSS1_CORE0 | intr | 410 |
| J721E_DEV_R5FSS1_CORE1 | intr | 410 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 155 | J721E_DEV_R5FSS1_CORE0 | intr | 411 |
| J721E_DEV_R5FSS1_CORE1 | intr | 411 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 156 | J721E_DEV_R5FSS1_CORE0 | intr | 412 |
| J721E_DEV_R5FSS1_CORE1 | intr | 412 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 157 | J721E_DEV_R5FSS1_CORE0 | intr | 413 |
| J721E_DEV_R5FSS1_CORE1 | intr | 413 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 158 | J721E_DEV_R5FSS1_CORE0 | intr | 414 |
| J721E_DEV_R5FSS1_CORE1 | intr | 414 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 159 | J721E_DEV_R5FSS1_CORE0 | intr | 415 |
| J721E_DEV_R5FSS1_CORE1 | intr | 415 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 160 | J721E_DEV_R5FSS1_CORE0 | intr | 416 |
| J721E_DEV_R5FSS1_CORE1 | intr | 416 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 161 | J721E_DEV_R5FSS1_CORE0 | intr | 417 |
| J721E_DEV_R5FSS1_CORE1 | intr | 417 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 162 | J721E_DEV_R5FSS1_CORE0 | intr | 418 |
| J721E_DEV_R5FSS1_CORE1 | intr | 418 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 163 | J721E_DEV_R5FSS1_CORE0 | intr | 419 |
| J721E_DEV_R5FSS1_CORE1 | intr | 419 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 164 | J721E_DEV_R5FSS1_CORE0 | intr | 420 |
| J721E_DEV_R5FSS1_CORE1 | intr | 420 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 165 | J721E_DEV_R5FSS1_CORE0 | intr | 421 |
| J721E_DEV_R5FSS1_CORE1 | intr | 421 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 166 | J721E_DEV_R5FSS1_CORE0 | intr | 422 |
| J721E_DEV_R5FSS1_CORE1 | intr | 422 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 167 | J721E_DEV_R5FSS1_CORE0 | intr | 423 |
| J721E_DEV_R5FSS1_CORE1 | intr | 423 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 168 | J721E_DEV_R5FSS1_CORE0 | intr | 424 |
| J721E_DEV_R5FSS1_CORE1 | intr | 424 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 169 | J721E_DEV_R5FSS1_CORE0 | intr | 425 |
| J721E_DEV_R5FSS1_CORE1 | intr | 425 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 170 | J721E_DEV_R5FSS1_CORE0 | intr | 426 |
| J721E_DEV_R5FSS1_CORE1 | intr | 426 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 171 | J721E_DEV_R5FSS1_CORE0 | intr | 427 |
| J721E_DEV_R5FSS1_CORE1 | intr | 427 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 172 | J721E_DEV_R5FSS1_CORE0 | intr | 428 |
| J721E_DEV_R5FSS1_CORE1 | intr | 428 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 173 | J721E_DEV_R5FSS1_CORE0 | intr | 429 |
| J721E_DEV_R5FSS1_CORE1 | intr | 429 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 174 | J721E_DEV_R5FSS1_CORE0 | intr | 430 |
| J721E_DEV_R5FSS1_CORE1 | intr | 430 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 175 | J721E_DEV_R5FSS1_CORE0 | intr | 431 |
| J721E_DEV_R5FSS1_CORE1 | intr | 431 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 176 | J721E_DEV_R5FSS1_CORE0 | intr | 432 |
| J721E_DEV_R5FSS1_CORE1 | intr | 432 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 177 | J721E_DEV_R5FSS1_CORE0 | intr | 433 |
| J721E_DEV_R5FSS1_CORE1 | intr | 433 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 178 | J721E_DEV_R5FSS1_CORE0 | intr | 434 |
| J721E_DEV_R5FSS1_CORE1 | intr | 434 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 179 | J721E_DEV_R5FSS1_CORE0 | intr | 435 |
| J721E_DEV_R5FSS1_CORE1 | intr | 435 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 180 | J721E_DEV_R5FSS1_CORE0 | intr | 436 |
| J721E_DEV_R5FSS1_CORE1 | intr | 436 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 181 | J721E_DEV_R5FSS1_CORE0 | intr | 437 |
| J721E_DEV_R5FSS1_CORE1 | intr | 437 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 182 | J721E_DEV_R5FSS1_CORE0 | intr | 438 |
| J721E_DEV_R5FSS1_CORE1 | intr | 438 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 183 | J721E_DEV_R5FSS1_CORE0 | intr | 439 |
| J721E_DEV_R5FSS1_CORE1 | intr | 439 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 184 | J721E_DEV_R5FSS1_CORE0 | intr | 440 |
| J721E_DEV_R5FSS1_CORE1 | intr | 440 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 185 | J721E_DEV_R5FSS1_CORE0 | intr | 441 |
| J721E_DEV_R5FSS1_CORE1 | intr | 441 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 186 | J721E_DEV_R5FSS1_CORE0 | intr | 442 |
| J721E_DEV_R5FSS1_CORE1 | intr | 442 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 187 | J721E_DEV_R5FSS1_CORE0 | intr | 443 |
| J721E_DEV_R5FSS1_CORE1 | intr | 443 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 188 | J721E_DEV_R5FSS1_CORE0 | intr | 444 |
| J721E_DEV_R5FSS1_CORE1 | intr | 444 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 189 | J721E_DEV_R5FSS1_CORE0 | intr | 445 |
| J721E_DEV_R5FSS1_CORE1 | intr | 445 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 190 | J721E_DEV_R5FSS1_CORE0 | intr | 446 |
| J721E_DEV_R5FSS1_CORE1 | intr | 446 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 191 | J721E_DEV_R5FSS1_CORE0 | intr | 447 |
| J721E_DEV_R5FSS1_CORE1 | intr | 447 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 192 | J721E_DEV_R5FSS1_CORE0 | intr | 448 |
| J721E_DEV_R5FSS1_CORE1 | intr | 448 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 193 | J721E_DEV_R5FSS1_CORE0 | intr | 449 |
| J721E_DEV_R5FSS1_CORE1 | intr | 449 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 194 | J721E_DEV_R5FSS1_CORE0 | intr | 450 |
| J721E_DEV_R5FSS1_CORE1 | intr | 450 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 195 | J721E_DEV_R5FSS1_CORE0 | intr | 451 |
| J721E_DEV_R5FSS1_CORE1 | intr | 451 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 196 | J721E_DEV_R5FSS1_CORE0 | intr | 452 |
| J721E_DEV_R5FSS1_CORE1 | intr | 452 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 197 | J721E_DEV_R5FSS1_CORE0 | intr | 453 |
| J721E_DEV_R5FSS1_CORE1 | intr | 453 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 198 | J721E_DEV_R5FSS1_CORE0 | intr | 454 |
| J721E_DEV_R5FSS1_CORE1 | intr | 454 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 199 | J721E_DEV_R5FSS1_CORE0 | intr | 455 |
| J721E_DEV_R5FSS1_CORE1 | intr | 455 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 200 | J721E_DEV_R5FSS1_CORE0 | intr | 456 |
| J721E_DEV_R5FSS1_CORE1 | intr | 456 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 201 | J721E_DEV_R5FSS1_CORE0 | intr | 457 |
| J721E_DEV_R5FSS1_CORE1 | intr | 457 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 202 | J721E_DEV_R5FSS1_CORE0 | intr | 458 |
| J721E_DEV_R5FSS1_CORE1 | intr | 458 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 203 | J721E_DEV_R5FSS1_CORE0 | intr | 459 |
| J721E_DEV_R5FSS1_CORE1 | intr | 459 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 204 | J721E_DEV_R5FSS1_CORE0 | intr | 460 |
| J721E_DEV_R5FSS1_CORE1 | intr | 460 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 205 | J721E_DEV_R5FSS1_CORE0 | intr | 461 |
| J721E_DEV_R5FSS1_CORE1 | intr | 461 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 206 | J721E_DEV_R5FSS1_CORE0 | intr | 462 |
| J721E_DEV_R5FSS1_CORE1 | intr | 462 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 207 | J721E_DEV_R5FSS1_CORE0 | intr | 463 |
| J721E_DEV_R5FSS1_CORE1 | intr | 463 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 208 | J721E_DEV_R5FSS1_CORE0 | intr | 464 |
| J721E_DEV_R5FSS1_CORE1 | intr | 464 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 209 | J721E_DEV_R5FSS1_CORE0 | intr | 465 |
| J721E_DEV_R5FSS1_CORE1 | intr | 465 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 210 | J721E_DEV_R5FSS1_CORE0 | intr | 466 |
| J721E_DEV_R5FSS1_CORE1 | intr | 466 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 211 | J721E_DEV_R5FSS1_CORE0 | intr | 467 |
| J721E_DEV_R5FSS1_CORE1 | intr | 467 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 212 | J721E_DEV_R5FSS1_CORE0 | intr | 468 |
| J721E_DEV_R5FSS1_CORE1 | intr | 468 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 213 | J721E_DEV_R5FSS1_CORE0 | intr | 469 |
| J721E_DEV_R5FSS1_CORE1 | intr | 469 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 214 | J721E_DEV_R5FSS1_CORE0 | intr | 470 |
| J721E_DEV_R5FSS1_CORE1 | intr | 470 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 215 | J721E_DEV_R5FSS1_CORE0 | intr | 471 |
| J721E_DEV_R5FSS1_CORE1 | intr | 471 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 216 | J721E_DEV_R5FSS1_CORE0 | intr | 472 |
| J721E_DEV_R5FSS1_CORE1 | intr | 472 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 217 | J721E_DEV_R5FSS1_CORE0 | intr | 473 |
| J721E_DEV_R5FSS1_CORE1 | intr | 473 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 218 | J721E_DEV_R5FSS1_CORE0 | intr | 474 |
| J721E_DEV_R5FSS1_CORE1 | intr | 474 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 219 | J721E_DEV_R5FSS1_CORE0 | intr | 475 |
| J721E_DEV_R5FSS1_CORE1 | intr | 475 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 220 | J721E_DEV_R5FSS1_CORE0 | intr | 476 |
| J721E_DEV_R5FSS1_CORE1 | intr | 476 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 221 | J721E_DEV_R5FSS1_CORE0 | intr | 477 |
| J721E_DEV_R5FSS1_CORE1 | intr | 477 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 222 | J721E_DEV_R5FSS1_CORE0 | intr | 478 |
| J721E_DEV_R5FSS1_CORE1 | intr | 478 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 223 | J721E_DEV_R5FSS1_CORE0 | intr | 479 |
| J721E_DEV_R5FSS1_CORE1 | intr | 479 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 224 | J721E_DEV_R5FSS1_CORE0 | intr | 480 |
| J721E_DEV_R5FSS1_CORE1 | intr | 480 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 225 | J721E_DEV_R5FSS1_CORE0 | intr | 481 |
| J721E_DEV_R5FSS1_CORE1 | intr | 481 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 226 | J721E_DEV_R5FSS1_CORE0 | intr | 482 |
| J721E_DEV_R5FSS1_CORE1 | intr | 482 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 227 | J721E_DEV_R5FSS1_CORE0 | intr | 483 |
| J721E_DEV_R5FSS1_CORE1 | intr | 483 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 228 | J721E_DEV_R5FSS1_CORE0 | intr | 484 |
| J721E_DEV_R5FSS1_CORE1 | intr | 484 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 229 | J721E_DEV_R5FSS1_CORE0 | intr | 485 |
| J721E_DEV_R5FSS1_CORE1 | intr | 485 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 230 | J721E_DEV_R5FSS1_CORE0 | intr | 486 |
| J721E_DEV_R5FSS1_CORE1 | intr | 486 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 231 | J721E_DEV_R5FSS1_CORE0 | intr | 487 |
| J721E_DEV_R5FSS1_CORE1 | intr | 487 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 232 | J721E_DEV_R5FSS1_CORE0 | intr | 488 |
| J721E_DEV_R5FSS1_CORE1 | intr | 488 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 233 | J721E_DEV_R5FSS1_CORE0 | intr | 489 |
| J721E_DEV_R5FSS1_CORE1 | intr | 489 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 234 | J721E_DEV_R5FSS1_CORE0 | intr | 490 |
| J721E_DEV_R5FSS1_CORE1 | intr | 490 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 235 | J721E_DEV_R5FSS1_CORE0 | intr | 491 |
| J721E_DEV_R5FSS1_CORE1 | intr | 491 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 236 | J721E_DEV_R5FSS1_CORE0 | intr | 492 |
| J721E_DEV_R5FSS1_CORE1 | intr | 492 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 237 | J721E_DEV_R5FSS1_CORE0 | intr | 493 |
| J721E_DEV_R5FSS1_CORE1 | intr | 493 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 238 | J721E_DEV_R5FSS1_CORE0 | intr | 494 |
| J721E_DEV_R5FSS1_CORE1 | intr | 494 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 239 | J721E_DEV_R5FSS1_CORE0 | intr | 495 |
| J721E_DEV_R5FSS1_CORE1 | intr | 495 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 240 | J721E_DEV_R5FSS1_CORE0 | intr | 496 |
| J721E_DEV_R5FSS1_CORE1 | intr | 496 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 241 | J721E_DEV_R5FSS1_CORE0 | intr | 497 |
| J721E_DEV_R5FSS1_CORE1 | intr | 497 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 242 | J721E_DEV_R5FSS1_CORE0 | intr | 498 |
| J721E_DEV_R5FSS1_CORE1 | intr | 498 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 243 | J721E_DEV_R5FSS1_CORE0 | intr | 499 |
| J721E_DEV_R5FSS1_CORE1 | intr | 499 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 244 | J721E_DEV_R5FSS1_CORE0 | intr | 500 |
| J721E_DEV_R5FSS1_CORE1 | intr | 500 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 245 | J721E_DEV_R5FSS1_CORE0 | intr | 501 |
| J721E_DEV_R5FSS1_CORE1 | intr | 501 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 246 | J721E_DEV_R5FSS1_CORE0 | intr | 502 |
| J721E_DEV_R5FSS1_CORE1 | intr | 502 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 247 | J721E_DEV_R5FSS1_CORE0 | intr | 503 |
| J721E_DEV_R5FSS1_CORE1 | intr | 503 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 248 | J721E_DEV_R5FSS1_CORE0 | intr | 504 |
| J721E_DEV_R5FSS1_CORE1 | intr | 504 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 249 | J721E_DEV_R5FSS1_CORE0 | intr | 505 |
| J721E_DEV_R5FSS1_CORE1 | intr | 505 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 250 | J721E_DEV_R5FSS1_CORE0 | intr | 506 |
| J721E_DEV_R5FSS1_CORE1 | intr | 506 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 251 | J721E_DEV_R5FSS1_CORE0 | intr | 507 |
| J721E_DEV_R5FSS1_CORE1 | intr | 507 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 252 | J721E_DEV_R5FSS1_CORE0 | intr | 508 |
| J721E_DEV_R5FSS1_CORE1 | intr | 508 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 253 | J721E_DEV_R5FSS1_CORE0 | intr | 509 |
| J721E_DEV_R5FSS1_CORE1 | intr | 509 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 254 | J721E_DEV_R5FSS1_CORE0 | intr | 510 |
| J721E_DEV_R5FSS1_CORE1 | intr | 510 | |||
| J721E_DEV_R5FSS1_INTROUTER0 | 135 | 255 | J721E_DEV_R5FSS1_CORE0 | intr | 511 |
| J721E_DEV_R5FSS1_CORE1 | intr | 511 |
TIMESYNC_INTRTR0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 0 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 1 | J721E_DEV_GTC0 | gtc_push_event | 0 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 2 | J721E_DEV_TIMER14 | timer_pwm | 1 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 3 | J721E_DEV_TIMER15 | timer_pwm | 1 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 4 | J721E_DEV_NAVSS0 | cpts0_genf0 | 1 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 5 | J721E_DEV_NAVSS0 | cpts0_genf1 | 2 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 6 | J721E_DEV_NAVSS0 | cpts0_genf2 | 3 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 7 | J721E_DEV_NAVSS0 | cpts0_genf3 | 4 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 8 | J721E_DEV_NAVSS0 | cpts0_genf4 | 5 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 9 | J721E_DEV_NAVSS0 | cpts0_genf5 | 6 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 10 | J721E_DEV_PCIE0 | pcie_cpts_genf0 | 12 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 11 | J721E_DEV_PCIE1 | pcie_cpts_genf0 | 12 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 12 | J721E_DEV_PCIE2 | pcie_cpts_genf0 | 12 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 13 | J721E_DEV_PCIE3 | pcie_cpts_genf0 | 12 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 14 | J721E_DEV_CPSW0 | cpts_genf0 | 1 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 15 | J721E_DEV_CPSW0 | cpts_genf1 | 2 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 16 | J721E_DEV_MCU_CPSW0 | cpts_genf0 | 1 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 17 | J721E_DEV_MCU_CPSW0 | cpts_genf1 | 2 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 18 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 19 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 20 | J721E_DEV_PCIE0 | pcie_cpts_hw1_push | 13 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 21 | J721E_DEV_PCIE1 | pcie_cpts_hw1_push | 13 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 22 | J721E_DEV_PCIE2 | pcie_cpts_hw1_push | 13 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 23 | J721E_DEV_PCIE3 | pcie_cpts_hw1_push | 13 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 24 | J721E_DEV_PRU_ICSSG0 | pr1_edc0_sync0_out | 0 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 25 | J721E_DEV_PRU_ICSSG0 | pr1_edc0_sync1_out | 1 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 26 | J721E_DEV_PRU_ICSSG0 | pr1_edc1_sync0_out | 2 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 27 | J721E_DEV_PRU_ICSSG0 | pr1_edc1_sync1_out | 3 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 28 | J721E_DEV_PRU_ICSSG1 | pr1_edc0_sync0_out | 0 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 29 | J721E_DEV_PRU_ICSSG1 | pr1_edc0_sync1_out | 1 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 30 | J721E_DEV_PRU_ICSSG1 | pr1_edc1_sync0_out | 2 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 31 | J721E_DEV_PRU_ICSSG1 | pr1_edc1_sync1_out | 3 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 32 | J721E_DEV_PCIE0 | pcie_cpts_sync | 14 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 33 | J721E_DEV_PCIE1 | pcie_cpts_sync | 14 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 34 | J721E_DEV_PCIE2 | pcie_cpts_sync | 14 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 35 | J721E_DEV_PCIE3 | pcie_cpts_sync | 14 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 36 | J721E_DEV_NAVSS0 | cpts0_sync | 7 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 37 | J721E_DEV_CPSW0 | cpts_sync | 3 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 38 | J721E_DEV_MCU_CPSW0 | cpts_sync | 3 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 39 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 40 | J721E_DEV_TIMER16 | timer_pwm | 1 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 41 | J721E_DEV_TIMER17 | timer_pwm | 1 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 42 | J721E_DEV_TIMER18 | timer_pwm | 1 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 43 | J721E_DEV_TIMER19 | timer_pwm | 1 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 44 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 45 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 46 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 47 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 48 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 49 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 50 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 51 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 52 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 53 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 54 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 55 | Use TRM - Not managed by TISCI |
TIMESYNC_INTRTR0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 0 | J721E_DEV_NAVSS0 | cpts0_hw1_push | 0 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 1 | J721E_DEV_NAVSS0 | cpts0_hw2_push | 1 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 2 | J721E_DEV_NAVSS0 | cpts0_hw3_push | 2 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 3 | J721E_DEV_NAVSS0 | cpts0_hw4_push | 3 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 4 | J721E_DEV_NAVSS0 | cpts0_hw5_push | 4 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 5 | J721E_DEV_NAVSS0 | cpts0_hw6_push | 5 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 6 | J721E_DEV_NAVSS0 | cpts0_hw7_push | 6 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 7 | J721E_DEV_NAVSS0 | cpts0_hw8_push | 7 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 8 | J721E_DEV_PRU_ICSSG0 | pr1_edc0_latch0_in | 0 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 9 | J721E_DEV_PRU_ICSSG0 | pr1_edc0_latch1_in | 1 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 10 | J721E_DEV_PRU_ICSSG0 | pr1_edc1_latch0_in | 2 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 11 | J721E_DEV_PRU_ICSSG0 | pr1_edc1_latch1_in | 3 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 12 | J721E_DEV_PRU_ICSSG1 | pr1_edc0_latch0_in | 0 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 13 | J721E_DEV_PRU_ICSSG1 | pr1_edc0_latch1_in | 1 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 14 | J721E_DEV_PRU_ICSSG1 | pr1_edc1_latch0_in | 2 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 15 | J721E_DEV_PRU_ICSSG1 | pr1_edc1_latch1_in | 3 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 16 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 17 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 18 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 19 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 20 | J721E_DEV_PCIE0 | pcie_cpts_hw2_push | 0 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 21 | J721E_DEV_PCIE1 | pcie_cpts_hw2_push | 0 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 22 | J721E_DEV_PCIE2 | pcie_cpts_hw2_push | 0 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 23 | J721E_DEV_PCIE3 | pcie_cpts_hw2_push | 0 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 24 | J721E_DEV_MCU_CPSW0 | cpts_hw3_push | 0 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 25 | J721E_DEV_MCU_CPSW0 | cpts_hw4_push | 1 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 26 | J721E_DEV_CPSW0 | cpts_hw1_push | 0 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 27 | J721E_DEV_CPSW0 | cpts_hw2_push | 1 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 28 | J721E_DEV_CPSW0 | cpts_hw3_push | 2 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 29 | J721E_DEV_CPSW0 | cpts_hw4_push | 3 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 30 | J721E_DEV_CPSW0 | cpts_hw5_push | 4 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 31 | J721E_DEV_CPSW0 | cpts_hw6_push | 5 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 32 | J721E_DEV_CPSW0 | cpts_hw7_push | 6 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 33 | J721E_DEV_CPSW0 | cpts_hw8_push | 7 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 34 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 35 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 36 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 37 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 38 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 39 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 40 | J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 52 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 41 | J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 53 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 42 | J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 54 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 43 | J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 55 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 44 | J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 56 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 45 | J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 57 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 46 | J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 58 |
| J721E_DEV_TIMESYNC_INTRTR0 | 136 | 47 | J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | intaggr_levi_pend | 59 |
WKUP_GPIOMUX_INTRTR0 Interrupt Router Input Sources¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Input Index | Source Name | Source Interface | Source Index |
|---|---|---|---|---|---|
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 0 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 1 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 2 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 3 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 4 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 5 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 6 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 7 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 8 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 9 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 10 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 11 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 12 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 13 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 14 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 15 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 16 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 17 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 18 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 19 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 20 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 21 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 22 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 23 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 24 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 25 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 26 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 27 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 28 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 29 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 30 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 31 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 32 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 33 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 34 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 35 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 36 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 37 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 38 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 39 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 40 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 41 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 42 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 43 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 44 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 45 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 46 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 47 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 48 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 49 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 50 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 51 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 52 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 53 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 54 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 55 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 56 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 57 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 58 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 59 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 60 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 61 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 62 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 63 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 64 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 65 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 66 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 67 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 68 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 69 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 70 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 71 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 72 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 73 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 74 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 75 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 76 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 77 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 78 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 79 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 80 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 81 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 82 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 83 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 84 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 85 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 86 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 87 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 88 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 89 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 90 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 91 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 92 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 93 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 94 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 95 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 96 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 97 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 98 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 99 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 100 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 101 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 102 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 103 | J721E_DEV_WKUP_GPIO0 | gpio_bank | 0 |
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 104 | J721E_DEV_WKUP_GPIO0 | gpio_bank | 1 |
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 105 | J721E_DEV_WKUP_GPIO0 | gpio_bank | 2 |
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 106 | J721E_DEV_WKUP_GPIO0 | gpio_bank | 3 |
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 107 | J721E_DEV_WKUP_GPIO0 | gpio_bank | 4 |
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 108 | J721E_DEV_WKUP_GPIO0 | gpio_bank | 5 |
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 109 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 110 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 111 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 112 | J721E_DEV_WKUP_GPIO1 | gpio_bank | 0 |
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 113 | J721E_DEV_WKUP_GPIO1 | gpio_bank | 1 |
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 114 | J721E_DEV_WKUP_GPIO1 | gpio_bank | 2 |
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 115 | J721E_DEV_WKUP_GPIO1 | gpio_bank | 3 |
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 116 | J721E_DEV_WKUP_GPIO1 | gpio_bank | 4 |
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 117 | J721E_DEV_WKUP_GPIO1 | gpio_bank | 5 |
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 118 | Use TRM - Not managed by TISCI | ||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 119 | Use TRM - Not managed by TISCI |
WKUP_GPIOMUX_INTRTR0 Interrupt Router Output Destinations¶
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| IR Name | IR Device ID | IR Output Index | Destination Name | Destination Interface | Destination Index |
|---|---|---|---|---|---|
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 0 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 124 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 124 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 1 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 125 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 125 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 2 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 126 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 126 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 3 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 127 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 127 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 4 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 128 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 128 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 5 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 129 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 129 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 6 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 130 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 130 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 7 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 131 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 131 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 8 | J721E_DEV_WKUP_ESM0 | esm_pls_event0 | 88 |
| J721E_DEV_WKUP_ESM0 | esm_pls_event1 | 96 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 8 | J721E_DEV_WKUP_ESM0 | esm_pls_event2 | 104 |
| J721E_DEV_MCU_R5FSS0_CORE0 | intr | 132 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 8 | J721E_DEV_MCU_R5FSS0_CORE1 | intr | 132 |
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 9 | J721E_DEV_WKUP_ESM0 | esm_pls_event0 | 89 |
| J721E_DEV_WKUP_ESM0 | esm_pls_event1 | 97 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 9 | J721E_DEV_WKUP_ESM0 | esm_pls_event2 | 105 |
| J721E_DEV_MCU_R5FSS0_CORE0 | intr | 133 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 9 | J721E_DEV_MCU_R5FSS0_CORE1 | intr | 133 |
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 10 | J721E_DEV_WKUP_ESM0 | esm_pls_event0 | 90 |
| J721E_DEV_WKUP_ESM0 | esm_pls_event1 | 98 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 10 | J721E_DEV_WKUP_ESM0 | esm_pls_event2 | 106 |
| J721E_DEV_MCU_R5FSS0_CORE0 | intr | 134 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 10 | J721E_DEV_MCU_R5FSS0_CORE1 | intr | 134 |
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 11 | J721E_DEV_WKUP_ESM0 | esm_pls_event0 | 91 |
| J721E_DEV_WKUP_ESM0 | esm_pls_event1 | 99 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 11 | J721E_DEV_WKUP_ESM0 | esm_pls_event2 | 107 |
| J721E_DEV_MCU_R5FSS0_CORE0 | intr | 135 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 11 | J721E_DEV_MCU_R5FSS0_CORE1 | intr | 135 |
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 12 | J721E_DEV_WKUP_ESM0 | esm_pls_event0 | 92 |
| J721E_DEV_WKUP_ESM0 | esm_pls_event1 | 100 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 12 | J721E_DEV_WKUP_ESM0 | esm_pls_event2 | 108 |
| J721E_DEV_MCU_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 4 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 12 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 136 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 136 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 13 | J721E_DEV_WKUP_ESM0 | esm_pls_event0 | 93 |
| J721E_DEV_WKUP_ESM0 | esm_pls_event1 | 101 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 13 | J721E_DEV_WKUP_ESM0 | esm_pls_event2 | 109 |
| J721E_DEV_MCU_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 5 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 13 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 137 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 137 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 14 | J721E_DEV_WKUP_ESM0 | esm_pls_event0 | 94 |
| J721E_DEV_WKUP_ESM0 | esm_pls_event1 | 102 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 14 | J721E_DEV_WKUP_ESM0 | esm_pls_event2 | 110 |
| J721E_DEV_MCU_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 6 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 14 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 138 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 138 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 15 | J721E_DEV_WKUP_ESM0 | esm_pls_event0 | 95 |
| J721E_DEV_WKUP_ESM0 | esm_pls_event1 | 103 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 15 | J721E_DEV_WKUP_ESM0 | esm_pls_event2 | 111 |
| J721E_DEV_MCU_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 7 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 15 | J721E_DEV_MCU_R5FSS0_CORE0 | intr | 139 |
| J721E_DEV_MCU_R5FSS0_CORE1 | intr | 139 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 16 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 960 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 960 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 16 | J721E_DEV_R5FSS0_INTROUTER0 | in | 160 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 160 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 16 | J721E_DEV_MCU_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 8 |
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 17 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 961 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 961 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 17 | J721E_DEV_R5FSS0_INTROUTER0 | in | 161 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 161 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 17 | J721E_DEV_MCU_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 9 |
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 18 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 962 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 962 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 18 | J721E_DEV_R5FSS0_INTROUTER0 | in | 162 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 162 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 18 | J721E_DEV_MCU_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 10 |
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 19 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 963 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 963 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 19 | J721E_DEV_R5FSS0_INTROUTER0 | in | 163 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 163 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 19 | J721E_DEV_MCU_NAVSS0_UDMASS_INTA_0 | intaggr_levi_pend | 11 |
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 20 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 964 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 964 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 20 | J721E_DEV_R5FSS0_INTROUTER0 | in | 164 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 164 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 21 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 965 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 965 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 21 | J721E_DEV_R5FSS0_INTROUTER0 | in | 165 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 165 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 22 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 966 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 966 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 22 | J721E_DEV_R5FSS0_INTROUTER0 | in | 166 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 166 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 23 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 967 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 967 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 23 | J721E_DEV_R5FSS0_INTROUTER0 | in | 167 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 167 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 24 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 968 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 968 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 24 | J721E_DEV_R5FSS0_INTROUTER0 | in | 168 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 168 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 25 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 969 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 969 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 25 | J721E_DEV_R5FSS0_INTROUTER0 | in | 169 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 169 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 26 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 970 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 970 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 26 | J721E_DEV_R5FSS0_INTROUTER0 | in | 170 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 170 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 27 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 971 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 971 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 27 | J721E_DEV_R5FSS0_INTROUTER0 | in | 171 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 171 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 28 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 972 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 972 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 28 | J721E_DEV_R5FSS0_INTROUTER0 | in | 172 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 172 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 29 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 973 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 973 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 29 | J721E_DEV_R5FSS0_INTROUTER0 | in | 173 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 173 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 30 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 974 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 974 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 30 | J721E_DEV_R5FSS0_INTROUTER0 | in | 174 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 174 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 31 | J721E_DEV_COMPUTE_CLUSTER0_CLEC | soc_events_in | 975 |
| J721E_DEV_COMPUTE_CLUSTER0_GIC500SS | spi | 975 | |||
| J721E_DEV_WKUP_GPIOMUX_INTRTR0 | 137 | 31 | J721E_DEV_R5FSS0_INTROUTER0 | in | 175 |
| J721E_DEV_R5FSS1_INTROUTER0 | in | 175 |
Interrupt Aggregator Device IDs¶
Some System Firmware TISCI message APIs require the Interrupt Aggregator device ID be provided as part of the request. Based on J721E Device IDs these are the valid Interrupt Aggregator device IDs.
| Interrupt Aggregator Device Name | Interrupt Aggregator Device ID |
|---|---|
| J721E_DEV_NAVSS0_MODSS_INTAGGR_0 | 207 |
| J721E_DEV_NAVSS0_MODSS_INTAGGR_1 | 208 |
| J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | 209 |
| J721E_DEV_MCU_NAVSS0_UDMASS_INTA_0 | 233 |
Interrupt Aggregator Virtual Interrupts¶
This section describes Interrupt Aggregator virtual interrupts. The virtual interrupts are used in interrupt management based TISCI messages.
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| Interrupt Aggregator Name | Virtual Interrupt Range |
|---|---|
| J721E_DEV_NAVSS0_MODSS_INTAGGR_0 | 0 to 63 |
| J721E_DEV_NAVSS0_MODSS_INTAGGR_1 | 0 to 63 |
| J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 (RESERVED BY SYSTEM FIRMWARE) | 0 to 37 |
| J721E_DEV_NAVSS0_UDMASS_INTAGGR_0 | 38 to 255 |
| J721E_DEV_MCU_NAVSS0_UDMASS_INTA_0 (RESERVED BY SYSTEM FIRMWARE) | 0 to 15 |
| J721E_DEV_MCU_NAVSS0_UDMASS_INTA_0 | 16 to 255 |
Global Events¶
This section describes J721E global events. The global events are used in interrupt management based TISCI messages.
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
| Global Event Name | Global Event Range |
|---|---|
| NAVSS0_UDMASS_INTAGGR_0 SEVT (RESERVED BY SYSTEM FIRMWARE) | 0 to 37 |
| NAVSS0_UDMASS_INTAGGR_0 SEVT | 38 to 4607 |
| MCU_NAVSS0_UDMASS_INTA_0 SEVT (RESERVED BY SYSTEM FIRMWARE) | 16384 to 16399 |
| MCU_NAVSS0_UDMASS_INTA_0 SEVT | 16400 to 17919 |
| NAVSS0_MODSS_INTAGGR_0 SEVT | 20480 to 21503 |
| NAVSS0_MODSS_INTAGGR_1 SEVT | 22528 to 23551 |
| NAVSS0_UDMASS_INTAGGR_0 MEVT | 32768 to 33279 |
| MCU_NAVSS0_UDMASS_INTA_0 MEVT | 34816 to 34943 |
| NAVSS0_UDMASS_INTAGGR_0 GEVT | 36864 to 37375 |
| MCU_NAVSS0_UDMASS_INTA_0 GEVT | 39936 to 40191 |
| NAVSS0_UDMAP_0 TRIGGER | 49152 to 50175 |
| MCU_NAVSS0_UDMAP_0 TRIGGER | 56320 to 56575 |
Event-Based Interrupt Source IDs¶
| Device Name | Device ID | Interrupt Source Name | Interrupt Source Index |
|---|---|---|---|
| J721E_DEV_NAVSS0_RINGACC_0 | 211 | Ring events | 0 to 973 |
| J721E_DEV_MCU_NAVSS0_RINGACC0 | 235 | Ring events | 0 to 255 |
| J721E_DEV_NAVSS0_RINGACC_0 | 211 | Ring monitor events | 1024 to 1055 |
| J721E_DEV_MCU_NAVSS0_RINGACC0 | 235 | Ring monitor events | 1024 to 1055 |
| J721E_DEV_NAVSS0_RINGACC_0 | 211 | Ring global error event | 2048 |
| J721E_DEV_MCU_NAVSS0_RINGACC0 | 235 | Ring global error event | 2048 |
| J721E_DEV_NAVSS0_UDMAP_0 | 212 | UDMA transmit channel OES events | 0 to 299 |
| J721E_DEV_NAVSS0_UDMAP_0 | 212 | UDMA transmit channel EOES events | 512 to 811 |
| J721E_DEV_NAVSS0_UDMAP_0 | 212 | UDMA receive channel OES events | 1024 to 1163 |
| J721E_DEV_NAVSS0_UDMAP_0 | 212 | UDMA receive channel EOES events | 1280 to 1419 |
| J721E_DEV_NAVSS0_UDMAP_0 | 212 | UDMA global configuration invalid flow event | 1536 |
| J721E_DEV_MCU_NAVSS0_UDMAP_0 | 236 | UDMA transmit channel OES events | 0 to 47 |
| J721E_DEV_MCU_NAVSS0_UDMAP_0 | 236 | UDMA transmit channel EOES events | 512 to 559 |
| J721E_DEV_MCU_NAVSS0_UDMAP_0 | 236 | UDMA receive channel OES events | 1024 to 1071 |
| J721E_DEV_MCU_NAVSS0_UDMAP_0 | 236 | UDMA receive channel EOES events | 1280 to 1327 |
| J721E_DEV_MCU_NAVSS0_UDMAP_0 | 236 | UDMA global configuration invalid flow event | 1536 |