J721E Clock Identifiers¶
Clock for J721E Device¶
This chapter provides information on clock IDs that identify clocks incoming and outgoing from devices identified via device IDs in J721E SoC.
TISCI message Power Management APIs define a device ID and clock ID as parameters allowing a user to specify granular control of clocks for a particular SoC subsystem.
Device wise clock ID list for J721E SoC¶
This is an enumerated list of clocks per device ID that can be controlled via the power management clock APIs
The following table describes functions implemented by clocks
| Function | Description |
|---|---|
| Input clock | Clock input to the SoC subsystem |
| Output clock | Clock output from the SoC subsystem |
| Input muxed clock | Clock input to the SoC subsystem, but can choose one of the parent clocks as a clock source |
| Parent input clock option to XYZ | One of the parent clocks that can be used as a source clock to a input muxed clock |
Also note: There are devices which do not have clock information. These do have chapters in this document associated with them, however, these would be marked as:
This device has no defined clocks.
The chapters corresponding to the devices are organized alphabetically per device name for ease of readability.
Clocks for A72SS0 Device¶
Device: J721E_DEV_A72SS0 (ID = 4)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_A72SS0_PLL_CTRL_CLK | Input clock |
| 1 | DEV_A72SS0_MSMC_CLK | Input clock |
| 2 | DEV_A72SS0_ARM_CLK_CLK | Input clock |
Clocks for A72SS0_CORE0 Device¶
Device: J721E_DEV_A72SS0_CORE0 (ID = 202)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 2 | DEV_A72SS0_CORE0_ARM_CLK_CLK | Input clock |
Clocks for A72SS0_CORE1 Device¶
Device: J721E_DEV_A72SS0_CORE1 (ID = 203)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_A72SS0_CORE1_ARM_CLK_CLK | Input clock |
Clocks for AASRC0 Device¶
Device: J721E_DEV_AASRC0 (ID = 139)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_AASRC0_SYS_CLK | Input clock |
| 1 | DEV_AASRC0_VBUSP_CLK | Input clock |
| 2 | DEV_AASRC0_RX0_SYNC | Input muxed clock |
| 3 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 4 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 5 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 6 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 7 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 8 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 9 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 10 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 11 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 12 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 13 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 14 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 15 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 16 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 17 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 18 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 19 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 20 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 21 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 22 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 23 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 24 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 25 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 26 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 27 | DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 28 | DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 29 | DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 30 | DEV_AASRC0_RX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 31 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 32 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 33 | DEV_AASRC0_RX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 34 | DEV_AASRC0_RX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 35 | DEV_AASRC0_RX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0 | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 36 | DEV_AASRC0_RX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1 | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 37 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 38 | DEV_AASRC0_RX0_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC0_RX0_SYNC |
| 39 | DEV_AASRC0_RX1_SYNC | Input muxed clock |
| 40 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 41 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 42 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 43 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 44 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 45 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 46 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 47 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 48 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 49 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 50 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 51 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 52 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 53 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 54 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 55 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 56 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 57 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 58 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 59 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 60 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 61 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 62 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 63 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 64 | DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 65 | DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 66 | DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 67 | DEV_AASRC0_RX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 68 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 69 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 70 | DEV_AASRC0_RX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 71 | DEV_AASRC0_RX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 72 | DEV_AASRC0_RX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0 | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 73 | DEV_AASRC0_RX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1 | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 74 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 75 | DEV_AASRC0_RX1_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC0_RX1_SYNC |
| 76 | DEV_AASRC0_RX2_SYNC | Input muxed clock |
| 77 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 78 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 79 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 80 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 81 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 82 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 83 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 84 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 85 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 86 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 87 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 88 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 89 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 90 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 91 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 92 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 93 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 94 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 95 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 96 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 97 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 98 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 99 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 100 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 101 | DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 102 | DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 103 | DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 104 | DEV_AASRC0_RX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 105 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 106 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 107 | DEV_AASRC0_RX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 108 | DEV_AASRC0_RX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 109 | DEV_AASRC0_RX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0 | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 110 | DEV_AASRC0_RX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1 | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 111 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 112 | DEV_AASRC0_RX2_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC0_RX2_SYNC |
| 113 | DEV_AASRC0_RX3_SYNC | Input muxed clock |
| 114 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP0_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 115 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP1_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 116 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP2_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 117 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP3_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 118 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP4_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 119 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP5_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 120 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP6_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 121 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP7_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 122 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP8_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 123 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP9_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 124 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP10_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 125 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP11_AFSR_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 126 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 127 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 128 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 129 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 130 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 131 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 132 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 133 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 134 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 135 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 136 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 137 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 138 | DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 139 | DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 140 | DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 141 | DEV_AASRC0_RX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 142 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 143 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 144 | DEV_AASRC0_RX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 145 | DEV_AASRC0_RX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 146 | DEV_AASRC0_RX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0 | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 147 | DEV_AASRC0_RX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1 | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 148 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 149 | DEV_AASRC0_RX3_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC0_RX3_SYNC |
| 150 | DEV_AASRC0_TX0_SYNC | Input muxed clock |
| 151 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 152 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 153 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 154 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 155 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 156 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 157 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 158 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 159 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 160 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 161 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 162 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 163 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 164 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 165 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 166 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 167 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 168 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 169 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 170 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 171 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 172 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 173 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 174 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 175 | DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 176 | DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 177 | DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 178 | DEV_AASRC0_TX0_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 179 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 180 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 181 | DEV_AASRC0_TX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 182 | DEV_AASRC0_TX0_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 183 | DEV_AASRC0_TX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0 | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 184 | DEV_AASRC0_TX0_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1 | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 185 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 186 | DEV_AASRC0_TX0_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC0_TX0_SYNC |
| 187 | DEV_AASRC0_TX1_SYNC | Input muxed clock |
| 188 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 189 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 190 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 191 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 192 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 193 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 194 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 195 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 196 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 197 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 198 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 199 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 200 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 201 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 202 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 203 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 204 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 205 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 206 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 207 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 208 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 209 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 210 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 211 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 212 | DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 213 | DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 214 | DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 215 | DEV_AASRC0_TX1_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 216 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 217 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 218 | DEV_AASRC0_TX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 219 | DEV_AASRC0_TX1_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 220 | DEV_AASRC0_TX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0 | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 221 | DEV_AASRC0_TX1_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1 | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 222 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 223 | DEV_AASRC0_TX1_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC0_TX1_SYNC |
| 224 | DEV_AASRC0_TX2_SYNC | Input muxed clock |
| 225 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 226 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 227 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 228 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 229 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 230 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 231 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 232 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 233 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 234 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 235 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 236 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 237 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 238 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 239 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 240 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 241 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 242 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 243 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 244 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 245 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 246 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 247 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 248 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 249 | DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 250 | DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 251 | DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 252 | DEV_AASRC0_TX2_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 253 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 254 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 255 | DEV_AASRC0_TX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 256 | DEV_AASRC0_TX2_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 257 | DEV_AASRC0_TX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0 | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 258 | DEV_AASRC0_TX2_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1 | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 259 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 260 | DEV_AASRC0_TX2_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC0_TX2_SYNC |
| 261 | DEV_AASRC0_TX3_SYNC | Input muxed clock |
| 262 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 263 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 264 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 265 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 266 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 267 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 268 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 269 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 270 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 271 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 272 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 273 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 274 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP0_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 275 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP1_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 276 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP2_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 277 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP3_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 278 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP4_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 279 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP5_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 280 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP6_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 281 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP7_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 282 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP8_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 283 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP9_AFSX_OUT | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 284 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP10_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 285 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCASP11_AFSX_OUT_DUP0 | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 286 | DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 287 | DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 288 | DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 289 | DEV_AASRC0_TX3_SYNC_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 290 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 291 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 292 | DEV_AASRC0_TX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT3_CLK | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 293 | DEV_AASRC0_TX3_SYNC_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT3_CLK | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 294 | DEV_AASRC0_TX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT0 | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 295 | DEV_AASRC0_TX3_SYNC_PARENT_MCU_ADC_CLK_SEL_OUT1 | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 296 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_AASRC0_TX3_SYNC |
| 297 | DEV_AASRC0_TX3_SYNC_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_AASRC0_TX3_SYNC |
Clocks for ACSPCIE_BUFFER0 Device¶
Device: J721E_DEV_ACSPCIE_BUFFER0 (ID = 337)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_ACSPCIE_BUFFER0_CLKIN0 | Input muxed clock |
| 1 | DEV_ACSPCIE_BUFFER0_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_0_REF_DER_OUT_CLK | Parent input clock option to DEV_ACSPCIE_BUFFER0_CLKIN0 |
| 2 | DEV_ACSPCIE_BUFFER0_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_1_REF_DER_OUT_CLK | Parent input clock option to DEV_ACSPCIE_BUFFER0_CLKIN0 |
| 3 | DEV_ACSPCIE_BUFFER0_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_0_REF1_OUT_CLK | Parent input clock option to DEV_ACSPCIE_BUFFER0_CLKIN0 |
| 4 | DEV_ACSPCIE_BUFFER0_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_1_REF1_OUT_CLK | Parent input clock option to DEV_ACSPCIE_BUFFER0_CLKIN0 |
| 5 | DEV_ACSPCIE_BUFFER0_CLKIN1 | Input muxed clock |
| 6 | DEV_ACSPCIE_BUFFER0_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_0_REF_DER_OUT_CLK | Parent input clock option to DEV_ACSPCIE_BUFFER0_CLKIN1 |
| 7 | DEV_ACSPCIE_BUFFER0_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_1_REF_DER_OUT_CLK | Parent input clock option to DEV_ACSPCIE_BUFFER0_CLKIN1 |
| 8 | DEV_ACSPCIE_BUFFER0_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_0_REF1_OUT_CLK | Parent input clock option to DEV_ACSPCIE_BUFFER0_CLKIN1 |
| 9 | DEV_ACSPCIE_BUFFER0_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_1_REF1_OUT_CLK | Parent input clock option to DEV_ACSPCIE_BUFFER0_CLKIN1 |
| 10 | DEV_ACSPCIE_BUFFER0_CLKOUT0_N | Output clock |
| 11 | DEV_ACSPCIE_BUFFER0_CLKOUT0_P | Output clock |
| 12 | DEV_ACSPCIE_BUFFER0_CLKOUT1_N | Output clock |
| 13 | DEV_ACSPCIE_BUFFER0_CLKOUT1_P | Output clock |
Clocks for ACSPCIE_BUFFER1 Device¶
Device: J721E_DEV_ACSPCIE_BUFFER1 (ID = 338)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_ACSPCIE_BUFFER1_CLKIN0 | Input muxed clock |
| 1 | DEV_ACSPCIE_BUFFER1_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_2_REF_DER_OUT_CLK | Parent input clock option to DEV_ACSPCIE_BUFFER1_CLKIN0 |
| 2 | DEV_ACSPCIE_BUFFER1_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_3_REF_DER_OUT_CLK | Parent input clock option to DEV_ACSPCIE_BUFFER1_CLKIN0 |
| 3 | DEV_ACSPCIE_BUFFER1_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_2_REF1_OUT_CLK | Parent input clock option to DEV_ACSPCIE_BUFFER1_CLKIN0 |
| 4 | DEV_ACSPCIE_BUFFER1_CLKIN0_PARENT_WIZ16B4M4CS_MAIN_3_REF1_OUT_CLK | Parent input clock option to DEV_ACSPCIE_BUFFER1_CLKIN0 |
| 5 | DEV_ACSPCIE_BUFFER1_CLKIN1 | Input muxed clock |
| 6 | DEV_ACSPCIE_BUFFER1_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_2_REF_DER_OUT_CLK | Parent input clock option to DEV_ACSPCIE_BUFFER1_CLKIN1 |
| 7 | DEV_ACSPCIE_BUFFER1_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_3_REF_DER_OUT_CLK | Parent input clock option to DEV_ACSPCIE_BUFFER1_CLKIN1 |
| 8 | DEV_ACSPCIE_BUFFER1_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_2_REF1_OUT_CLK | Parent input clock option to DEV_ACSPCIE_BUFFER1_CLKIN1 |
| 9 | DEV_ACSPCIE_BUFFER1_CLKIN1_PARENT_WIZ16B4M4CS_MAIN_3_REF1_OUT_CLK | Parent input clock option to DEV_ACSPCIE_BUFFER1_CLKIN1 |
| 10 | DEV_ACSPCIE_BUFFER1_CLKOUT0_N | Output clock |
| 11 | DEV_ACSPCIE_BUFFER1_CLKOUT0_P | Output clock |
| 12 | DEV_ACSPCIE_BUFFER1_CLKOUT1_N | Output clock |
| 13 | DEV_ACSPCIE_BUFFER1_CLKOUT1_P | Output clock |
Clocks for ATL0 Device¶
Device: J721E_DEV_ATL0 (ID = 2)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_ATL0_VBUS_CLK | Input clock |
| 1 | DEV_ATL0_ATL_CLK | Input muxed clock |
| 2 | DEV_ATL0_ATL_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT1_CLK | Parent input clock option to DEV_ATL0_ATL_CLK |
| 3 | DEV_ATL0_ATL_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | Parent input clock option to DEV_ATL0_ATL_CLK |
| 4 | DEV_ATL0_ATL_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT1_CLK | Parent input clock option to DEV_ATL0_ATL_CLK |
| 5 | DEV_ATL0_ATL_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT7_CLK | Parent input clock option to DEV_ATL0_ATL_CLK |
| 6 | DEV_ATL0_ATL_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_ATL0_ATL_CLK |
| 7 | DEV_ATL0_ATL_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_ATL0_ATL_CLK |
| 8 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_1 | Output clock |
| 9 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT | Output clock |
| 10 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_3 | Output clock |
| 11 | DEV_ATL0_ATL_IO_PORT_ATCLK_OUT_2 | Output clock |
Clocks for BOARD0 Device¶
Device: J721E_DEV_BOARD0 (ID = 157)
Note
BOARD0 is a special device that represents the board on which the SoC is mounted.
Clocks that are incoming to or outgoing from the SoC are represented in this section from the perspective of the board.
Function documented here implies:
| Function | Description |
|---|---|
| Input clock | Clock is supplied from SoC to the board (It is an output of the SoC) |
| Output clock | Clock is supplied from board to the SoC (It is an output of the Board and input to the SoC) |
NOTE: Clocks which can be bi-directional are listed as Output clock
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_BOARD0_SPI0_CLK_IN | Input clock |
| 2 | DEV_BOARD0_SPI1_CLK_IN | Input clock |
| 4 | DEV_BOARD0_SPI2_CLK_IN | Input clock |
| 6 | DEV_BOARD0_SPI3_CLK_IN | Input clock |
| 8 | DEV_BOARD0_SPI5_CLK_IN | Input clock |
| 10 | DEV_BOARD0_SPI6_CLK_IN | Input clock |
| 12 | DEV_BOARD0_SPI7_CLK_IN | Input clock |
| 14 | DEV_BOARD0_MCU_SPI0_CLK_IN | Input clock |
| 16 | DEV_BOARD0_MCU_SPI1_CLK_IN | Input clock |
| 18 | DEV_BOARD0_MCU_OSPI0_CLK_IN | Input clock |
| 19 | DEV_BOARD0_MCU_OSPI0_LBCLKO_IN | Input clock |
| 20 | DEV_BOARD0_MCU_OSPI0_DQS_OUT | Output clock |
| 21 | DEV_BOARD0_MCU_OSPI1_CLK_IN | Input clock |
| 22 | DEV_BOARD0_MCU_OSPI1_LBCLKO_IN | Input clock |
| 23 | DEV_BOARD0_MCU_OSPI1_DQS_OUT | Output clock |
| 25 | DEV_BOARD0_I2C0_SCL_OUT | Output clock |
| 27 | DEV_BOARD0_I2C1_SCL_OUT | Output clock |
| 29 | DEV_BOARD0_I2C2_SCL_OUT | Output clock |
| 31 | DEV_BOARD0_I2C3_SCL_OUT | Output clock |
| 33 | DEV_BOARD0_I2C4_SCL_OUT | Output clock |
| 35 | DEV_BOARD0_I2C5_SCL_OUT | Output clock |
| 37 | DEV_BOARD0_I2C6_SCL_OUT | Output clock |
| 38 | DEV_BOARD0_MCU_I2C0_SCL_IN | Input clock |
| 39 | DEV_BOARD0_MCU_I2C0_SCL_OUT | Output clock |
| 41 | DEV_BOARD0_MCU_I2C1_SCL_OUT | Output clock |
| 42 | DEV_BOARD0_WKUP_I2C0_SCL_IN | Input clock |
| 43 | DEV_BOARD0_WKUP_I2C0_SCL_OUT | Output clock |
| 44 | DEV_BOARD0_I3C0_SCL_IN | Input clock |
| 45 | DEV_BOARD0_I3C0_SCL_OUT | Output clock |
| 46 | DEV_BOARD0_MCU_I3C0_SCL_IN | Input clock |
| 47 | DEV_BOARD0_MCU_I3C0_SCL_OUT | Output clock |
| 48 | DEV_BOARD0_MCU_I3C1_SCL_IN | Input clock |
| 49 | DEV_BOARD0_MCU_I3C1_SCL_OUT | Output clock |
| 50 | DEV_BOARD0_MCU_HYPERBUS0_CK_IN | Input clock |
| 51 | DEV_BOARD0_MCU_HYPERBUS0_CKN_IN | Input clock |
| 52 | DEV_BOARD0_DSI_TXCLKP_IN | Input clock |
| 53 | DEV_BOARD0_DSI_TXCLKN_IN | Input clock |
| 54 | DEV_BOARD0_PRG0_MDIO0_MDC_IN | Input clock |
| 55 | DEV_BOARD0_PRG0_RGMII1_TXC_IN | Input clock |
| 56 | DEV_BOARD0_PRG0_RGMII1_TXC_OUT | Output clock |
| 57 | DEV_BOARD0_PRG0_RGMII1_RXC_OUT | Output clock |
| 58 | DEV_BOARD0_PRG0_RGMII2_TXC_IN | Input clock |
| 59 | DEV_BOARD0_PRG0_RGMII2_TXC_OUT | Output clock |
| 60 | DEV_BOARD0_PRG0_RGMII2_RXC_OUT | Output clock |
| 61 | DEV_BOARD0_PRG1_MDIO0_MDC_IN | Input clock |
| 62 | DEV_BOARD0_PRG1_RGMII1_TXC_IN | Input clock |
| 63 | DEV_BOARD0_PRG1_RGMII1_TXC_OUT | Output clock |
| 64 | DEV_BOARD0_PRG1_RGMII1_RXC_OUT | Output clock |
| 65 | DEV_BOARD0_PRG1_RGMII2_TXC_IN | Input clock |
| 66 | DEV_BOARD0_PRG1_RGMII2_TXC_OUT | Output clock |
| 67 | DEV_BOARD0_PRG1_RGMII2_RXC_OUT | Output clock |
| 68 | DEV_BOARD0_MDIO0_MDC_IN | Input clock |
| 70 | DEV_BOARD0_RGMII3_RXC_OUT | Output clock |
| 72 | DEV_BOARD0_RGMII4_RXC_OUT | Output clock |
| 74 | DEV_BOARD0_RGMII5_RXC_OUT | Output clock |
| 76 | DEV_BOARD0_RGMII6_RXC_OUT | Output clock |
| 78 | DEV_BOARD0_RGMII7_RXC_OUT | Output clock |
| 80 | DEV_BOARD0_RGMII8_RXC_OUT | Output clock |
| 81 | DEV_BOARD0_RMII_REF_CLK_OUT | Output clock |
| 82 | DEV_BOARD0_CPTS0_RFT_CLK_OUT | Output clock |
| 83 | DEV_BOARD0_MCU_MDIO0_MDC_IN | Input clock |
| 84 | DEV_BOARD0_MCU_RGMII1_TXC_IN | Input clock |
| 85 | DEV_BOARD0_MCU_RGMII1_TXC_OUT | Output clock |
| 86 | DEV_BOARD0_MCU_RGMII1_RXC_OUT | Output clock |
| 87 | DEV_BOARD0_MCU_RMII1_REF_CLK_OUT | Output clock |
| 88 | DEV_BOARD0_MCU_CPTS0_RFT_CLK_OUT | Output clock |
| 89 | DEV_BOARD0_UFS0_REF_CLK_IN | Input clock |
| 91 | DEV_BOARD0_DDR0_CK0_IN | Input clock |
| 92 | DEV_BOARD0_DDR0_CK0_N_IN | Input clock |
| 99 | DEV_BOARD0_MMC0_CLK_IN | Input clock |
| 100 | DEV_BOARD0_MMC1_CLK_IN | Input clock |
| 101 | DEV_BOARD0_MMC2_CLK_IN | Input clock |
| 102 | DEV_BOARD0_GPMC0_CLK_IN | Input clock |
| 103 | DEV_BOARD0_GPMC0_CLK_OUT | Output clock |
| 104 | DEV_BOARD0_GPMC0_FCLK_MUX_IN | Input clock |
| 105 | DEV_BOARD0_MLB0_MLBCLK_OUT | Output clock |
| 106 | DEV_BOARD0_MLB0_MLBCP_OUT | Output clock |
| 108 | DEV_BOARD0_VPFE0_PCLK_OUT | Output clock |
| 109 | DEV_BOARD0_VOUT1_PCLK_IN | Input clock |
| 110 | DEV_BOARD0_VOUT1_EXTPCLKIN_OUT | Output clock |
| 111 | DEV_BOARD0_VOUT2_PCLK_IN | Input clock |
| 112 | DEV_BOARD0_VOUT2_EXTPCLKIN_OUT | Output clock |
| 113 | DEV_BOARD0_OBSCLK0_IN | Input clock |
| 114 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK | Parent input clock option to DEV_BOARD0_OBSCLK0_IN |
| 115 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK | Parent input clock option to DEV_BOARD0_OBSCLK0_IN |
| 116 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK | Parent input clock option to DEV_BOARD0_OBSCLK0_IN |
| 117 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK | Parent input clock option to DEV_BOARD0_OBSCLK0_IN |
| 118 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | Parent input clock option to DEV_BOARD0_OBSCLK0_IN |
| 119 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_5_HSDIVOUT0_CLK | Parent input clock option to DEV_BOARD0_OBSCLK0_IN |
| 120 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_6_HSDIVOUT0_CLK | Parent input clock option to DEV_BOARD0_OBSCLK0_IN |
| 126 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK | Parent input clock option to DEV_BOARD0_OBSCLK0_IN |
| 127 | DEV_BOARD0_OBSCLK0_IN_PARENT_OBSCLK1_MUX_OUT0 | Parent input clock option to DEV_BOARD0_OBSCLK0_IN |
| 128 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK | Parent input clock option to DEV_BOARD0_OBSCLK0_IN |
| 129 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | Parent input clock option to DEV_BOARD0_OBSCLK0_IN |
| 130 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK | Parent input clock option to DEV_BOARD0_OBSCLK0_IN |
| 131 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK | Parent input clock option to DEV_BOARD0_OBSCLK0_IN |
| 132 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT0_CLK | Parent input clock option to DEV_BOARD0_OBSCLK0_IN |
| 133 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK | Parent input clock option to DEV_BOARD0_OBSCLK0_IN |
| 137 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_23_HSDIVOUT0_CLK | Parent input clock option to DEV_BOARD0_OBSCLK0_IN |
| 138 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_24_HSDIVOUT0_CLK | Parent input clock option to DEV_BOARD0_OBSCLK0_IN |
| 139 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_25_HSDIVOUT0_CLK | Parent input clock option to DEV_BOARD0_OBSCLK0_IN |
| 140 | DEV_BOARD0_OBSCLK0_IN_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | Parent input clock option to DEV_BOARD0_OBSCLK0_IN |
| 141 | DEV_BOARD0_OBSCLK0_IN_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_BOARD0_OBSCLK0_IN |
| 142 | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_BOARD0_OBSCLK0_IN |
| 143 | DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0 | Parent input clock option to DEV_BOARD0_OBSCLK0_IN |
| 144 | DEV_BOARD0_OBSCLK0_IN_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_BOARD0_OBSCLK0_IN |
| 145 | DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_BOARD0_OBSCLK0_IN |
| 146 | DEV_BOARD0_OBSCLK1_IN | Input muxed clock |
| 147 | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_7_HSDIVOUT0_CLK4 | Parent input clock option to DEV_BOARD0_OBSCLK1_IN |
| 148 | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV0_16FFT_MAIN_8_HSDIVOUT0_CLK8 | Parent input clock option to DEV_BOARD0_OBSCLK1_IN |
| 149 | DEV_BOARD0_OBSCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_13_HSDIVOUT0_CLK4 | Parent input clock option to DEV_BOARD0_OBSCLK1_IN |
| 152 | DEV_BOARD0_MCU_OBSCLK0_IN | Input muxed clock |
| 153 | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0 | Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN |
| 154 | DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_BOARD0_MCU_OBSCLK0_IN |
| 169 | DEV_BOARD0_SYSCLKOUT0_IN | Input clock |
| 170 | DEV_BOARD0_MCU_SYSCLKOUT0_IN | Input clock |
| 171 | DEV_BOARD0_TRC_CLK_IN | Input clock |
| 172 | DEV_BOARD0_CLKOUT_IN | Input muxed clock |
| 173 | DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK5 | Parent input clock option to DEV_BOARD0_CLKOUT_IN |
| 174 | DEV_BOARD0_CLKOUT_IN_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT0_CLK10 | Parent input clock option to DEV_BOARD0_CLKOUT_IN |
| 175 | DEV_BOARD0_MCU_CLKOUT0_IN | Input muxed clock |
| 176 | DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK5 | Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN |
| 177 | DEV_BOARD0_MCU_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT0_CLK10 | Parent input clock option to DEV_BOARD0_MCU_CLKOUT0_IN |
| 178 | DEV_BOARD0_LED_CLK_OUT | Output clock |
| 179 | DEV_BOARD0_EXT_REFCLK1_OUT | Output clock |
| 180 | DEV_BOARD0_MCU_EXT_REFCLK0_OUT | Output clock |
| 181 | DEV_BOARD0_HFOSC1_CLK_OUT | Output clock |
| 182 | DEV_BOARD0_TCK_OUT | Output clock |
| 183 | DEV_BOARD0_PCIE_REFCLK0P_IN | Input clock |
| 184 | DEV_BOARD0_PCIE_REFCLK0N_IN | Input clock |
| 185 | DEV_BOARD0_PCIE_REFCLK0P_OUT | Output clock |
| 186 | DEV_BOARD0_PCIE_REFCLK0N_OUT | Output clock |
| 187 | DEV_BOARD0_PCIE_REFCLK0P_OUT_IN | Input clock |
| 188 | DEV_BOARD0_PCIE_REFCLK0N_OUT_IN | Input clock |
| 189 | DEV_BOARD0_PCIE_REFCLK1P_IN | Input clock |
| 190 | DEV_BOARD0_PCIE_REFCLK1N_IN | Input clock |
| 191 | DEV_BOARD0_PCIE_REFCLK1P_OUT | Output clock |
| 192 | DEV_BOARD0_PCIE_REFCLK1N_OUT | Output clock |
| 193 | DEV_BOARD0_PCIE_REFCLK1P_OUT_IN | Input clock |
| 194 | DEV_BOARD0_PCIE_REFCLK1N_OUT_IN | Input clock |
| 195 | DEV_BOARD0_PCIE_REFCLK2P_IN | Input clock |
| 196 | DEV_BOARD0_PCIE_REFCLK2N_IN | Input clock |
| 197 | DEV_BOARD0_PCIE_REFCLK2P_OUT | Output clock |
| 198 | DEV_BOARD0_PCIE_REFCLK2N_OUT | Output clock |
| 201 | DEV_BOARD0_PCIE_REFCLK3P_OUT | Output clock |
| 202 | DEV_BOARD0_PCIE_REFCLK3N_OUT | Output clock |
| 203 | DEV_BOARD0_PCIE_REFCLK3P_IN | Input clock |
| 204 | DEV_BOARD0_PCIE_REFCLK3N_IN | Input clock |
| 217 | DEV_BOARD0_MCASP0_ACLKR_IN | Input clock |
| 218 | DEV_BOARD0_MCASP0_ACLKR_OUT | Output clock |
| 219 | DEV_BOARD0_MCASP0_AFSR_OUT | Output clock |
| 220 | DEV_BOARD0_MCASP0_ACLKX_IN | Input clock |
| 221 | DEV_BOARD0_MCASP0_ACLKX_OUT | Output clock |
| 222 | DEV_BOARD0_MCASP0_AFSX_OUT | Output clock |
| 223 | DEV_BOARD0_MCASP1_ACLKR_IN | Input clock |
| 224 | DEV_BOARD0_MCASP1_ACLKR_OUT | Output clock |
| 225 | DEV_BOARD0_MCASP1_AFSR_OUT | Output clock |
| 226 | DEV_BOARD0_MCASP1_ACLKX_IN | Input clock |
| 227 | DEV_BOARD0_MCASP1_ACLKX_OUT | Output clock |
| 228 | DEV_BOARD0_MCASP1_AFSX_OUT | Output clock |
| 229 | DEV_BOARD0_MCASP2_ACLKR_IN | Input clock |
| 230 | DEV_BOARD0_MCASP2_ACLKR_OUT | Output clock |
| 231 | DEV_BOARD0_MCASP2_AFSR_OUT | Output clock |
| 232 | DEV_BOARD0_MCASP2_ACLKX_IN | Input clock |
| 233 | DEV_BOARD0_MCASP2_ACLKX_OUT | Output clock |
| 234 | DEV_BOARD0_MCASP2_AFSX_OUT | Output clock |
| 235 | DEV_BOARD0_MCASP3_ACLKR_IN | Input clock |
| 236 | DEV_BOARD0_MCASP3_ACLKR_OUT | Output clock |
| 237 | DEV_BOARD0_MCASP3_AFSR_OUT | Output clock |
| 238 | DEV_BOARD0_MCASP3_ACLKX_IN | Input clock |
| 239 | DEV_BOARD0_MCASP3_ACLKX_OUT | Output clock |
| 240 | DEV_BOARD0_MCASP3_AFSX_OUT | Output clock |
| 241 | DEV_BOARD0_MCASP4_ACLKR_IN | Input clock |
| 242 | DEV_BOARD0_MCASP4_ACLKR_OUT | Output clock |
| 243 | DEV_BOARD0_MCASP4_AFSR_OUT | Output clock |
| 244 | DEV_BOARD0_MCASP4_ACLKX_IN | Input clock |
| 245 | DEV_BOARD0_MCASP4_ACLKX_OUT | Output clock |
| 246 | DEV_BOARD0_MCASP4_AFSX_OUT | Output clock |
| 247 | DEV_BOARD0_MCASP5_ACLKR_IN | Input clock |
| 248 | DEV_BOARD0_MCASP5_ACLKR_OUT | Output clock |
| 249 | DEV_BOARD0_MCASP5_AFSR_OUT | Output clock |
| 250 | DEV_BOARD0_MCASP5_ACLKX_IN | Input clock |
| 251 | DEV_BOARD0_MCASP5_ACLKX_OUT | Output clock |
| 252 | DEV_BOARD0_MCASP5_AFSX_OUT | Output clock |
| 253 | DEV_BOARD0_MCASP6_ACLKR_IN | Input clock |
| 254 | DEV_BOARD0_MCASP6_ACLKR_OUT | Output clock |
| 255 | DEV_BOARD0_MCASP6_AFSR_OUT | Output clock |
| 256 | DEV_BOARD0_MCASP6_ACLKX_IN | Input clock |
| 257 | DEV_BOARD0_MCASP6_ACLKX_OUT | Output clock |
| 258 | DEV_BOARD0_MCASP6_AFSX_OUT | Output clock |
| 259 | DEV_BOARD0_MCASP7_ACLKR_IN | Input clock |
| 260 | DEV_BOARD0_MCASP7_ACLKR_OUT | Output clock |
| 261 | DEV_BOARD0_MCASP7_AFSR_OUT | Output clock |
| 262 | DEV_BOARD0_MCASP7_ACLKX_IN | Input clock |
| 263 | DEV_BOARD0_MCASP7_ACLKX_OUT | Output clock |
| 264 | DEV_BOARD0_MCASP7_AFSX_OUT | Output clock |
| 265 | DEV_BOARD0_MCASP8_ACLKR_IN | Input clock |
| 267 | DEV_BOARD0_MCASP8_ACLKR_OUT | Output clock |
| 268 | DEV_BOARD0_MCASP8_AFSR_OUT | Output clock |
| 269 | DEV_BOARD0_MCASP8_ACLKX_IN | Input clock |
| 270 | DEV_BOARD0_MCASP8_ACLKX_OUT | Output clock |
| 271 | DEV_BOARD0_MCASP8_AFSX_OUT | Output clock |
| 272 | DEV_BOARD0_MCASP9_ACLKR_IN | Input clock |
| 273 | DEV_BOARD0_MCASP9_ACLKR_OUT | Output clock |
| 274 | DEV_BOARD0_MCASP9_AFSR_OUT | Output clock |
| 275 | DEV_BOARD0_MCASP9_ACLKX_IN | Input clock |
| 276 | DEV_BOARD0_MCASP9_ACLKX_OUT | Output clock |
| 278 | DEV_BOARD0_MCASP9_AFSX_OUT | Output clock |
| 279 | DEV_BOARD0_MCASP10_ACLKR_IN | Input clock |
| 280 | DEV_BOARD0_MCASP10_ACLKR_OUT | Output clock |
| 281 | DEV_BOARD0_MCASP10_AFSR_OUT | Output clock |
| 282 | DEV_BOARD0_MCASP10_ACLKX_IN | Input clock |
| 283 | DEV_BOARD0_MCASP10_ACLKX_OUT | Output clock |
| 284 | DEV_BOARD0_MCASP10_AFSX_OUT | Output clock |
| 285 | DEV_BOARD0_MCASP11_ACLKR_IN | Input clock |
| 286 | DEV_BOARD0_MCASP11_ACLKR_OUT | Output clock |
| 287 | DEV_BOARD0_MCASP11_AFSR_OUT | Output clock |
| 288 | DEV_BOARD0_MCASP11_ACLKX_IN | Input clock |
| 289 | DEV_BOARD0_MCASP11_ACLKX_OUT | Output clock |
| 290 | DEV_BOARD0_MCASP11_AFSX_OUT | Output clock |
| 300 | DEV_BOARD0_AUDIO_EXT_REFCLK0_OUT | Output clock |
| 301 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN | Input muxed clock |
| 302 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 303 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 304 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 305 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 306 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 307 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 308 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 309 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 310 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 311 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 312 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 313 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 314 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 315 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 316 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 317 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 318 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 319 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 320 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 321 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 322 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 323 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 324 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 325 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 326 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 327 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 328 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 329 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 330 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 331 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 334 | DEV_BOARD0_AUDIO_EXT_REFCLK0_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK0_OUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK0_IN |
| 335 | DEV_BOARD0_AUDIO_EXT_REFCLK1_OUT | Output clock |
| 336 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN | Input muxed clock |
| 337 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 338 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 339 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 340 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 341 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 342 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 343 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 344 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 345 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 346 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 347 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 348 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 349 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 350 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 351 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 352 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 353 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 354 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 355 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 356 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 357 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 358 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 359 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 360 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 361 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 362 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 363 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 364 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 365 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 366 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 369 | DEV_BOARD0_AUDIO_EXT_REFCLK1_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK1_OUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK1_IN |
| 370 | DEV_BOARD0_AUDIO_EXT_REFCLK2_OUT | Output clock |
| 371 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN | Input muxed clock |
| 372 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 373 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 374 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 375 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 376 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 377 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 378 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 379 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 380 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 381 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 382 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 383 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 384 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 385 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 386 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 387 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 388 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 389 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 390 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 391 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 392 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 393 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 394 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 395 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 396 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 397 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 398 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 399 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 400 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 401 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 404 | DEV_BOARD0_AUDIO_EXT_REFCLK2_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK2_OUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK2_IN |
| 405 | DEV_BOARD0_AUDIO_EXT_REFCLK3_OUT | Output clock |
| 406 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN | Input muxed clock |
| 407 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 408 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 409 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 410 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 411 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 412 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 413 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 414 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 415 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 416 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 417 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 418 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKR_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 419 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_0_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 420 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_1_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 421 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_2_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 422 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_3_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 423 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_4_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 424 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_5_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 425 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_6_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 426 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_7_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 427 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_8_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 428 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_9_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 429 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_10_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 430 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_MCASP_MAIN_11_MCASP_AHCLKX_POUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 431 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 432 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 433 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 434 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 435 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 436 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
| 439 | DEV_BOARD0_AUDIO_EXT_REFCLK3_IN_PARENT_BOARD_0_AUDIO_EXT_REFCLK3_OUT | Parent input clock option to DEV_BOARD0_AUDIO_EXT_REFCLK3_IN |
Clocks for C66SS0 Device¶
This device has no defined clocks.
Clocks for C66SS0_CORE0 Device¶
Device: J721E_DEV_C66SS0_CORE0 (ID = 142)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_C66SS0_CORE0_GEM_TRC_CLK | Input clock |
| 1 | DEV_C66SS0_CORE0_GEM_CLK2_OUT_CLK | Output clock |
| 4 | DEV_C66SS0_CORE0_GEM_PBIST_ROM_CLK | Output clock |
| 6 | DEV_C66SS0_CORE0_GEM_CLKIN_CLK | Input clock |
Clocks for C66SS0_INTROUTER0 Device¶
Device: J721E_DEV_C66SS0_INTROUTER0 (ID = 121)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_C66SS0_INTROUTER0_INTR_CLK | Input clock |
Clocks for C66SS0_PBIST0 Device¶
This device has no defined clocks.
Clocks for C66SS1 Device¶
This device has no defined clocks.
Clocks for C66SS1_CORE0 Device¶
Device: J721E_DEV_C66SS1_CORE0 (ID = 143)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_C66SS1_CORE0_GEM_TRC_CLK | Input clock |
| 1 | DEV_C66SS1_CORE0_GEM_CLK2_OUT_CLK | Output clock |
| 4 | DEV_C66SS1_CORE0_GEM_PBIST_ROM_CLK | Output clock |
| 6 | DEV_C66SS1_CORE0_GEM_CLKIN_CLK | Input clock |
Clocks for C66SS1_INTROUTER0 Device¶
Device: J721E_DEV_C66SS1_INTROUTER0 (ID = 122)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_C66SS1_INTROUTER0_INTR_CLK | Input clock |
Clocks for C66SS1_PBIST0 Device¶
This device has no defined clocks.
Clocks for C71SS0 Device¶
Device: J721E_DEV_C71SS0 (ID = 15)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_C71SS0_C7X_CLK | Input clock |
| 1 | DEV_C71SS0_PLL_CTRL_CLK | Input clock |
Clocks for C71SS0_MMA Device¶
Device: J721E_DEV_C71SS0_MMA (ID = 16)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_C71SS0_MMA_PLL_CTRL_CLK | Input clock |
| 1 | DEV_C71SS0_MMA_MMA_CLK | Input clock |
Clocks for C71X_0_PBIST_VD Device¶
This device has no defined clocks.
Clocks for CMPEVENT_INTRTR0 Device¶
Device: J721E_DEV_CMPEVENT_INTRTR0 (ID = 123)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_CMPEVENT_INTRTR0_INTR_CLK | Input clock |
Clocks for COMPUTE_CLUSTER0 Device¶
This device has no defined clocks.
Clocks for COMPUTE_CLUSTER0_CFG_WRAP Device¶
Device: J721E_DEV_COMPUTE_CLUSTER0_CFG_WRAP (ID = 5)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_COMPUTE_CLUSTER0_CFG_WRAP_CLK4_CLK | Input clock |
Clocks for COMPUTE_CLUSTER0_CLEC Device¶
Device: J721E_DEV_COMPUTE_CLUSTER0_CLEC (ID = 6)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_COMPUTE_CLUSTER0_CLEC_CLK4_CLK | Input clock |
| 1 | DEV_COMPUTE_CLUSTER0_CLEC_CLK1_CLK | Input clock |
Clocks for COMPUTE_CLUSTER0_CORE_CORE Device¶
Device: J721E_DEV_COMPUTE_CLUSTER0_CORE_CORE (ID = 7)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_COMPUTE_CLUSTER0_CORE_CORE_PSIL_LEAF_CLK | Input clock |
| 1 | DEV_COMPUTE_CLUSTER0_CORE_CORE_CLK1_CLK | Input clock |
Clocks for COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW Device¶
Device: J721E_DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW (ID = 8)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW_PLL_CTRL_CLK | Input clock |
| 1 | DEV_COMPUTE_CLUSTER0_DDR32SS_EMIF0_EW_DDRSS_DDR_PLL_CLK | Input clock |
Clocks for COMPUTE_CLUSTER0_DEBUG_WRAP Device¶
Device: J721E_DEV_COMPUTE_CLUSTER0_DEBUG_WRAP (ID = 9)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_CLK1_CLK_CLK | Input clock |
| 1 | DEV_COMPUTE_CLUSTER0_DEBUG_WRAP_CLK2_CLK_CLK | Input clock |
Clocks for COMPUTE_CLUSTER0_DMSC_WRAP Device¶
Device: J721E_DEV_COMPUTE_CLUSTER0_DMSC_WRAP (ID = 12)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_COMPUTE_CLUSTER0_DMSC_WRAP_CLK4_CLK_CLK | Input clock |
Clocks for COMPUTE_CLUSTER0_EN_MSMC_DOMAIN Device¶
Device: J721E_DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN (ID = 13)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_COMPUTE_CLUSTER0_EN_MSMC_DOMAIN_MSMC_CLK1_CLK | Input clock |
Clocks for COMPUTE_CLUSTER0_GIC500SS Device¶
Device: J721E_DEV_COMPUTE_CLUSTER0_GIC500SS (ID = 14)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_COMPUTE_CLUSTER0_GIC500SS_VCLK_CLK | Input clock |
Clocks for COMPUTE_CLUSTER0_PBIST_WRAP Device¶
Device: J721E_DEV_COMPUTE_CLUSTER0_PBIST_WRAP (ID = 17)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVP_CLK1_CLK_CLK | Input clock |
| 1 | DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK4_CLK_CLK | Input clock |
| 2 | DEV_COMPUTE_CLUSTER0_PBIST_WRAP_DIVH_CLK2_CLK_CLK | Input clock |
Clocks for CPSW0 Device¶
Device: J721E_DEV_CPSW0 (ID = 19)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_CPSW0_GMII3_MT_CLK | Input clock |
| 1 | DEV_CPSW0_SERDES6_TXFCLK | Input clock |
| 2 | DEV_CPSW0_SERDES8_TXMCLK | Input clock |
| 3 | DEV_CPSW0_GMII2_MR_CLK | Input clock |
| 4 | DEV_CPSW0_SERDES2_TXFCLK | Input clock |
| 5 | DEV_CPSW0_SERDES4_RXCLK | Input clock |
| 6 | DEV_CPSW0_SERDES7_TXMCLK | Input clock |
| 7 | DEV_CPSW0_SERDES7_RXCLK | Input clock |
| 8 | DEV_CPSW0_SERDES6_REFCLK | Input clock |
| 9 | DEV_CPSW0_SERDES5_TXFCLK | Input clock |
| 10 | DEV_CPSW0_SERDES5_RXCLK | Input clock |
| 11 | DEV_CPSW0_GMII4_MT_CLK | Input clock |
| 12 | DEV_CPSW0_SERDES3_TXFCLK | Input clock |
| 13 | DEV_CPSW0_SERDES2_REFCLK | Input clock |
| 14 | DEV_CPSW0_SERDES4_RXFCLK | Input clock |
| 15 | DEV_CPSW0_SERDES6_RXFCLK | Input clock |
| 16 | DEV_CPSW0_CPTS_RFT_CLK | Input muxed clock |
| 17 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
| 18 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
| 19 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
| 20 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
| 21 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
| 22 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
| 23 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
| 24 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
| 25 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
| 26 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
| 27 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
| 28 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
| 29 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
| 30 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
| 31 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
| 32 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | Parent input clock option to DEV_CPSW0_CPTS_RFT_CLK |
| 33 | DEV_CPSW0_SERDES5_RXFCLK | Input clock |
| 34 | DEV_CPSW0_SERDES5_TXMCLK | Input clock |
| 35 | DEV_CPSW0_GMII5_MT_CLK | Input clock |
| 36 | DEV_CPSW0_SERDES2_RXCLK | Input clock |
| 37 | DEV_CPSW0_SERDES8_RXFCLK | Input clock |
| 38 | DEV_CPSW0_SERDES1_RXFCLK | Input clock |
| 39 | DEV_CPSW0_SERDES8_RXCLK | Input clock |
| 40 | DEV_CPSW0_GMII_RFT_CLK | Input clock |
| 41 | DEV_CPSW0_SERDES3_REFCLK | Input clock |
| 42 | DEV_CPSW0_RGMII_MHZ_250_CLK | Input clock |
| 43 | DEV_CPSW0_SERDES7_REFCLK | Input clock |
| 44 | DEV_CPSW0_GMII6_MT_CLK | Input clock |
| 45 | DEV_CPSW0_SERDES6_TXMCLK | Input clock |
| 46 | DEV_CPSW0_RMII_MHZ_50_CLK | Input clock |
| 47 | DEV_CPSW0_GMII4_MR_CLK | Input clock |
| 48 | DEV_CPSW0_SERDES2_TXMCLK | Input clock |
| 49 | DEV_CPSW0_RGMII_MHZ_50_CLK | Input clock |
| 50 | DEV_CPSW0_SERDES4_TXMCLK | Input clock |
| 51 | DEV_CPSW0_SERDES3_RXFCLK | Input clock |
| 52 | DEV_CPSW0_GMII8_MT_CLK | Input clock |
| 53 | DEV_CPSW0_SERDES7_TXFCLK | Input clock |
| 54 | DEV_CPSW0_GMII7_MT_CLK | Input clock |
| 55 | DEV_CPSW0_GMII7_MR_CLK | Input clock |
| 56 | DEV_CPSW0_SERDES6_RXCLK | Input clock |
| 57 | DEV_CPSW0_SERDES3_RXCLK | Input clock |
| 58 | DEV_CPSW0_SERDES4_REFCLK | Input clock |
| 59 | DEV_CPSW0_SERDES1_RXCLK | Input clock |
| 60 | DEV_CPSW0_SERDES1_TXFCLK | Input clock |
| 61 | DEV_CPSW0_GMII6_MR_CLK | Input clock |
| 62 | DEV_CPSW0_SERDES1_REFCLK | Input clock |
| 63 | DEV_CPSW0_RGMII_MHZ_5_CLK | Input clock |
| 64 | DEV_CPSW0_SERDES5_REFCLK | Input clock |
| 65 | DEV_CPSW0_GMII2_MT_CLK | Input clock |
| 66 | DEV_CPSW0_SERDES8_TXFCLK | Input clock |
| 67 | DEV_CPSW0_GMII8_MR_CLK | Input clock |
| 68 | DEV_CPSW0_GMII1_MR_CLK | Input clock |
| 69 | DEV_CPSW0_SERDES8_REFCLK | Input clock |
| 70 | DEV_CPSW0_SERDES3_TXMCLK | Input clock |
| 71 | DEV_CPSW0_GMII3_MR_CLK | Input clock |
| 72 | DEV_CPSW0_SERDES1_TXMCLK | Input clock |
| 73 | DEV_CPSW0_SERDES7_RXFCLK | Input clock |
| 74 | DEV_CPSW0_GMII5_MR_CLK | Input clock |
| 75 | DEV_CPSW0_GMII1_MT_CLK | Input clock |
| 76 | DEV_CPSW0_SERDES2_RXFCLK | Input clock |
| 77 | DEV_CPSW0_SERDES4_TXFCLK | Input clock |
| 78 | DEV_CPSW0_SERDES3_TXCLK | Output clock |
| 79 | DEV_CPSW0_CPTS_GENF0 | Output clock |
| 80 | DEV_CPSW0_SERDES5_TXCLK | Output clock |
| 81 | DEV_CPSW0_SERDES6_TXCLK | Output clock |
| 82 | DEV_CPSW0_SERDES8_TXCLK | Output clock |
| 83 | DEV_CPSW0_SERDES1_TXCLK | Output clock |
| 84 | DEV_CPSW0_SERDES4_TXCLK | Output clock |
| 85 | DEV_CPSW0_SERDES2_TXCLK | Output clock |
| 86 | DEV_CPSW0_SERDES7_TXCLK | Output clock |
| 87 | DEV_CPSW0_MDIO_MDCLK_O | Output clock |
| 89 | DEV_CPSW0_CPPI_CLK_CLK | Input clock |
Clocks for CPT2_AGGR0 Device¶
Device: J721E_DEV_CPT2_AGGR0 (ID = 20)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_CPT2_AGGR0_VCLK_CLK | Input clock |
Clocks for CPT2_AGGR1 Device¶
Device: J721E_DEV_CPT2_AGGR1 (ID = 21)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_CPT2_AGGR1_VCLK_CLK | Input clock |
Clocks for CPT2_AGGR2 Device¶
Device: J721E_DEV_CPT2_AGGR2 (ID = 23)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_CPT2_AGGR2_VCLK_CLK | Input clock |
Clocks for CSI_PSILSS0 Device¶
Device: J721E_DEV_CSI_PSILSS0 (ID = 25)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_CSI_PSILSS0_MAIN_CLK | Input clock |
Clocks for CSI_RX_IF0 Device¶
Device: J721E_DEV_CSI_RX_IF0 (ID = 26)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_CSI_RX_IF0_VBUS_CLK_CLK | Input clock |
| 1 | DEV_CSI_RX_IF0_PPI_RX_BYTE_CLK | Input clock |
| 2 | DEV_CSI_RX_IF0_MAIN_CLK_CLK | Input clock |
| 3 | DEV_CSI_RX_IF0_VP_CLK_CLK | Input clock |
Clocks for CSI_RX_IF1 Device¶
Device: J721E_DEV_CSI_RX_IF1 (ID = 27)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_CSI_RX_IF1_VBUS_CLK_CLK | Input clock |
| 1 | DEV_CSI_RX_IF1_PPI_RX_BYTE_CLK | Input clock |
| 2 | DEV_CSI_RX_IF1_MAIN_CLK_CLK | Input clock |
| 3 | DEV_CSI_RX_IF1_VP_CLK_CLK | Input clock |
Clocks for CSI_TX_IF0 Device¶
Device: J721E_DEV_CSI_TX_IF0 (ID = 28)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_CSI_TX_IF0_ESC_CLK_CLK | Input clock |
| 1 | DEV_CSI_TX_IF0_DPHY_TXBYTECLKHS_CL_CLK | Input clock |
| 2 | DEV_CSI_TX_IF0_VBUS_CLK_CLK | Input clock |
| 3 | DEV_CSI_TX_IF0_MAIN_CLK_CLK | Input clock |
Clocks for DCC0 Device¶
Device: J721E_DEV_DCC0 (ID = 30)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DCC0_DCC_INPUT10_CLK | Input clock |
| 1 | DEV_DCC0_DCC_INPUT01_CLK | Input clock |
| 2 | DEV_DCC0_DCC_CLKSRC2_CLK | Input clock |
| 3 | DEV_DCC0_DCC_CLKSRC7_CLK | Input clock |
| 4 | DEV_DCC0_DCC_CLKSRC0_CLK | Input clock |
| 5 | DEV_DCC0_VBUS_CLK | Input clock |
| 6 | DEV_DCC0_DCC_CLKSRC4_CLK | Input clock |
| 7 | DEV_DCC0_DCC_CLKSRC1_CLK | Input clock |
| 8 | DEV_DCC0_DCC_CLKSRC3_CLK | Input clock |
| 9 | DEV_DCC0_DCC_INPUT00_CLK | Input clock |
| 10 | DEV_DCC0_DCC_CLKSRC5_CLK | Input clock |
| 11 | DEV_DCC0_DCC_CLKSRC6_CLK | Input clock |
| 12 | DEV_DCC0_DCC_INPUT02_CLK | Input clock |
Clocks for DCC1 Device¶
Device: J721E_DEV_DCC1 (ID = 31)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DCC1_DCC_INPUT10_CLK | Input clock |
| 1 | DEV_DCC1_DCC_INPUT01_CLK | Input clock |
| 2 | DEV_DCC1_DCC_CLKSRC2_CLK | Input clock |
| 3 | DEV_DCC1_DCC_CLKSRC7_CLK | Input clock |
| 4 | DEV_DCC1_DCC_CLKSRC0_CLK | Input clock |
| 5 | DEV_DCC1_VBUS_CLK | Input clock |
| 6 | DEV_DCC1_DCC_CLKSRC4_CLK | Input clock |
| 7 | DEV_DCC1_DCC_CLKSRC1_CLK | Input clock |
| 8 | DEV_DCC1_DCC_CLKSRC3_CLK | Input clock |
| 9 | DEV_DCC1_DCC_INPUT00_CLK | Input clock |
| 10 | DEV_DCC1_DCC_CLKSRC5_CLK | Input clock |
| 11 | DEV_DCC1_DCC_CLKSRC6_CLK | Input clock |
| 12 | DEV_DCC1_DCC_INPUT02_CLK | Input clock |
Clocks for DCC10 Device¶
Device: J721E_DEV_DCC10 (ID = 41)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DCC10_DCC_INPUT10_CLK | Input clock |
| 1 | DEV_DCC10_DCC_INPUT01_CLK | Input clock |
| 2 | DEV_DCC10_DCC_CLKSRC2_CLK | Input clock |
| 3 | DEV_DCC10_DCC_CLKSRC7_CLK | Input clock |
| 4 | DEV_DCC10_DCC_CLKSRC0_CLK | Input clock |
| 5 | DEV_DCC10_VBUS_CLK | Input clock |
| 6 | DEV_DCC10_DCC_CLKSRC4_CLK | Input clock |
| 7 | DEV_DCC10_DCC_CLKSRC1_CLK | Input clock |
| 8 | DEV_DCC10_DCC_CLKSRC3_CLK | Input clock |
| 9 | DEV_DCC10_DCC_INPUT00_CLK | Input clock |
| 10 | DEV_DCC10_DCC_CLKSRC5_CLK | Input clock |
| 11 | DEV_DCC10_DCC_CLKSRC6_CLK | Input clock |
| 12 | DEV_DCC10_DCC_INPUT02_CLK | Input clock |
Clocks for DCC11 Device¶
Device: J721E_DEV_DCC11 (ID = 42)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DCC11_DCC_INPUT10_CLK | Input clock |
| 1 | DEV_DCC11_DCC_INPUT01_CLK | Input clock |
| 2 | DEV_DCC11_DCC_CLKSRC2_CLK | Input clock |
| 3 | DEV_DCC11_DCC_CLKSRC7_CLK | Input clock |
| 4 | DEV_DCC11_DCC_CLKSRC0_CLK | Input clock |
| 5 | DEV_DCC11_VBUS_CLK | Input clock |
| 6 | DEV_DCC11_DCC_CLKSRC4_CLK | Input clock |
| 7 | DEV_DCC11_DCC_CLKSRC1_CLK | Input clock |
| 8 | DEV_DCC11_DCC_CLKSRC3_CLK | Input clock |
| 9 | DEV_DCC11_DCC_INPUT00_CLK | Input clock |
| 10 | DEV_DCC11_DCC_CLKSRC5_CLK | Input clock |
| 11 | DEV_DCC11_DCC_CLKSRC6_CLK | Input clock |
| 12 | DEV_DCC11_DCC_INPUT02_CLK | Input clock |
Clocks for DCC12 Device¶
Device: J721E_DEV_DCC12 (ID = 43)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DCC12_DCC_INPUT10_CLK | Input clock |
| 1 | DEV_DCC12_DCC_INPUT01_CLK | Input clock |
| 2 | DEV_DCC12_DCC_CLKSRC2_CLK | Input clock |
| 3 | DEV_DCC12_DCC_CLKSRC7_CLK | Input clock |
| 4 | DEV_DCC12_DCC_CLKSRC0_CLK | Input clock |
| 5 | DEV_DCC12_VBUS_CLK | Input clock |
| 6 | DEV_DCC12_DCC_CLKSRC4_CLK | Input clock |
| 7 | DEV_DCC12_DCC_CLKSRC1_CLK | Input clock |
| 8 | DEV_DCC12_DCC_CLKSRC3_CLK | Input clock |
| 9 | DEV_DCC12_DCC_INPUT00_CLK | Input clock |
| 10 | DEV_DCC12_DCC_CLKSRC5_CLK | Input clock |
| 11 | DEV_DCC12_DCC_CLKSRC6_CLK | Input clock |
| 12 | DEV_DCC12_DCC_INPUT02_CLK | Input clock |
Clocks for DCC2 Device¶
Device: J721E_DEV_DCC2 (ID = 32)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DCC2_DCC_INPUT10_CLK | Input clock |
| 1 | DEV_DCC2_DCC_INPUT01_CLK | Input clock |
| 2 | DEV_DCC2_DCC_CLKSRC2_CLK | Input clock |
| 3 | DEV_DCC2_DCC_CLKSRC7_CLK | Input clock |
| 4 | DEV_DCC2_DCC_CLKSRC0_CLK | Input clock |
| 5 | DEV_DCC2_VBUS_CLK | Input clock |
| 6 | DEV_DCC2_DCC_CLKSRC4_CLK | Input clock |
| 7 | DEV_DCC2_DCC_CLKSRC1_CLK | Input clock |
| 8 | DEV_DCC2_DCC_CLKSRC3_CLK | Input clock |
| 9 | DEV_DCC2_DCC_INPUT00_CLK | Input clock |
| 10 | DEV_DCC2_DCC_CLKSRC5_CLK | Input clock |
| 11 | DEV_DCC2_DCC_CLKSRC6_CLK | Input clock |
| 12 | DEV_DCC2_DCC_INPUT02_CLK | Input clock |
Clocks for DCC3 Device¶
Device: J721E_DEV_DCC3 (ID = 33)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DCC3_DCC_INPUT10_CLK | Input clock |
| 1 | DEV_DCC3_DCC_INPUT01_CLK | Input clock |
| 2 | DEV_DCC3_DCC_CLKSRC2_CLK | Input clock |
| 3 | DEV_DCC3_DCC_CLKSRC7_CLK | Input clock |
| 4 | DEV_DCC3_DCC_CLKSRC0_CLK | Input clock |
| 5 | DEV_DCC3_VBUS_CLK | Input clock |
| 6 | DEV_DCC3_DCC_CLKSRC4_CLK | Input clock |
| 7 | DEV_DCC3_DCC_CLKSRC1_CLK | Input clock |
| 8 | DEV_DCC3_DCC_CLKSRC3_CLK | Input clock |
| 9 | DEV_DCC3_DCC_INPUT00_CLK | Input clock |
| 10 | DEV_DCC3_DCC_CLKSRC5_CLK | Input clock |
| 11 | DEV_DCC3_DCC_CLKSRC6_CLK | Input clock |
| 12 | DEV_DCC3_DCC_INPUT02_CLK | Input clock |
Clocks for DCC4 Device¶
Device: J721E_DEV_DCC4 (ID = 34)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DCC4_DCC_INPUT10_CLK | Input clock |
| 1 | DEV_DCC4_DCC_INPUT01_CLK | Input clock |
| 2 | DEV_DCC4_DCC_CLKSRC2_CLK | Input clock |
| 3 | DEV_DCC4_DCC_CLKSRC7_CLK | Input clock |
| 4 | DEV_DCC4_DCC_CLKSRC0_CLK | Input clock |
| 5 | DEV_DCC4_VBUS_CLK | Input clock |
| 6 | DEV_DCC4_DCC_CLKSRC4_CLK | Input clock |
| 7 | DEV_DCC4_DCC_CLKSRC1_CLK | Input clock |
| 8 | DEV_DCC4_DCC_CLKSRC3_CLK | Input clock |
| 9 | DEV_DCC4_DCC_INPUT00_CLK | Input clock |
| 10 | DEV_DCC4_DCC_CLKSRC5_CLK | Input clock |
| 11 | DEV_DCC4_DCC_CLKSRC6_CLK | Input clock |
| 12 | DEV_DCC4_DCC_INPUT02_CLK | Input clock |
Clocks for DCC5 Device¶
Device: J721E_DEV_DCC5 (ID = 36)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DCC5_DCC_INPUT10_CLK | Input clock |
| 1 | DEV_DCC5_DCC_INPUT01_CLK | Input clock |
| 2 | DEV_DCC5_DCC_CLKSRC2_CLK | Input clock |
| 3 | DEV_DCC5_DCC_CLKSRC7_CLK | Input clock |
| 4 | DEV_DCC5_DCC_CLKSRC0_CLK | Input clock |
| 5 | DEV_DCC5_VBUS_CLK | Input clock |
| 6 | DEV_DCC5_DCC_CLKSRC4_CLK | Input clock |
| 7 | DEV_DCC5_DCC_CLKSRC1_CLK | Input clock |
| 8 | DEV_DCC5_DCC_CLKSRC3_CLK | Input clock |
| 9 | DEV_DCC5_DCC_INPUT00_CLK | Input clock |
| 10 | DEV_DCC5_DCC_CLKSRC5_CLK | Input clock |
| 11 | DEV_DCC5_DCC_CLKSRC6_CLK | Input clock |
| 12 | DEV_DCC5_DCC_INPUT02_CLK | Input clock |
Clocks for DCC6 Device¶
Device: J721E_DEV_DCC6 (ID = 37)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DCC6_DCC_INPUT10_CLK | Input clock |
| 1 | DEV_DCC6_DCC_INPUT01_CLK | Input clock |
| 2 | DEV_DCC6_DCC_CLKSRC2_CLK | Input clock |
| 3 | DEV_DCC6_DCC_CLKSRC7_CLK | Input clock |
| 4 | DEV_DCC6_DCC_CLKSRC0_CLK | Input clock |
| 5 | DEV_DCC6_VBUS_CLK | Input clock |
| 6 | DEV_DCC6_DCC_CLKSRC4_CLK | Input clock |
| 7 | DEV_DCC6_DCC_CLKSRC1_CLK | Input clock |
| 8 | DEV_DCC6_DCC_CLKSRC3_CLK | Input clock |
| 9 | DEV_DCC6_DCC_INPUT00_CLK | Input clock |
| 10 | DEV_DCC6_DCC_CLKSRC5_CLK | Input clock |
| 11 | DEV_DCC6_DCC_CLKSRC6_CLK | Input clock |
| 12 | DEV_DCC6_DCC_INPUT02_CLK | Input clock |
Clocks for DCC7 Device¶
Device: J721E_DEV_DCC7 (ID = 38)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DCC7_DCC_INPUT10_CLK | Input clock |
| 1 | DEV_DCC7_DCC_INPUT01_CLK | Input clock |
| 2 | DEV_DCC7_DCC_CLKSRC2_CLK | Input clock |
| 3 | DEV_DCC7_DCC_CLKSRC7_CLK | Input clock |
| 4 | DEV_DCC7_DCC_CLKSRC0_CLK | Input clock |
| 5 | DEV_DCC7_VBUS_CLK | Input clock |
| 6 | DEV_DCC7_DCC_CLKSRC4_CLK | Input clock |
| 7 | DEV_DCC7_DCC_CLKSRC1_CLK | Input clock |
| 8 | DEV_DCC7_DCC_CLKSRC3_CLK | Input clock |
| 9 | DEV_DCC7_DCC_INPUT00_CLK | Input clock |
| 10 | DEV_DCC7_DCC_CLKSRC5_CLK | Input clock |
| 11 | DEV_DCC7_DCC_CLKSRC6_CLK | Input clock |
| 12 | DEV_DCC7_DCC_INPUT02_CLK | Input clock |
Clocks for DCC8 Device¶
Device: J721E_DEV_DCC8 (ID = 39)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DCC8_DCC_INPUT10_CLK | Input clock |
| 1 | DEV_DCC8_DCC_INPUT01_CLK | Input clock |
| 2 | DEV_DCC8_DCC_CLKSRC2_CLK | Input clock |
| 3 | DEV_DCC8_DCC_CLKSRC7_CLK | Input clock |
| 4 | DEV_DCC8_DCC_CLKSRC0_CLK | Input clock |
| 5 | DEV_DCC8_VBUS_CLK | Input clock |
| 6 | DEV_DCC8_DCC_CLKSRC4_CLK | Input clock |
| 7 | DEV_DCC8_DCC_CLKSRC1_CLK | Input clock |
| 8 | DEV_DCC8_DCC_CLKSRC3_CLK | Input clock |
| 9 | DEV_DCC8_DCC_INPUT00_CLK | Input clock |
| 10 | DEV_DCC8_DCC_CLKSRC5_CLK | Input clock |
| 11 | DEV_DCC8_DCC_CLKSRC6_CLK | Input clock |
| 12 | DEV_DCC8_DCC_INPUT02_CLK | Input clock |
Clocks for DCC9 Device¶
Device: J721E_DEV_DCC9 (ID = 40)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DCC9_DCC_INPUT10_CLK | Input clock |
| 1 | DEV_DCC9_DCC_INPUT01_CLK | Input clock |
| 2 | DEV_DCC9_DCC_CLKSRC2_CLK | Input clock |
| 3 | DEV_DCC9_DCC_CLKSRC7_CLK | Input clock |
| 4 | DEV_DCC9_DCC_CLKSRC0_CLK | Input clock |
| 5 | DEV_DCC9_VBUS_CLK | Input clock |
| 6 | DEV_DCC9_DCC_CLKSRC4_CLK | Input clock |
| 7 | DEV_DCC9_DCC_CLKSRC1_CLK | Input clock |
| 8 | DEV_DCC9_DCC_CLKSRC3_CLK | Input clock |
| 9 | DEV_DCC9_DCC_INPUT00_CLK | Input clock |
| 10 | DEV_DCC9_DCC_CLKSRC5_CLK | Input clock |
| 11 | DEV_DCC9_DCC_CLKSRC6_CLK | Input clock |
| 12 | DEV_DCC9_DCC_INPUT02_CLK | Input clock |
Clocks for DDR0 Device¶
Device: J721E_DEV_DDR0 (ID = 47)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DDR0_DDRSS_VBUS_CLK | Input clock |
| 1 | DEV_DDR0_PLL_CTRL_CLK | Input clock |
| 2 | DEV_DDR0_DDRSS_DDR_PLL_CLK | Input clock |
| 3 | DEV_DDR0_DDRSS_CFG_CLK | Input clock |
| 4 | DEV_DDR0_DDRSS_IO_CK_N | Output clock |
| 5 | DEV_DDR0_DDRSS_IO_CK | Output clock |
Clocks for DEBUGSS_WRAP0 Device¶
Device: J721E_DEV_DEBUGSS_WRAP0 (ID = 304)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 5 | DEV_DEBUGSS_WRAP0_TREXPT_CLK | Input clock |
| 9 | DEV_DEBUGSS_WRAP0_CORE_CLK | Input clock |
| 25 | DEV_DEBUGSS_WRAP0_JTAG_TCK | Input clock |
| 32 | DEV_DEBUGSS_WRAP0_CSTPIU_TRACECLK | Output clock |
| 35 | DEV_DEBUGSS_WRAP0_ATB_CLK | Input clock |
Clocks for DECODER0 Device¶
Device: J721E_DEV_DECODER0 (ID = 144)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DECODER0_SYS_CLK | Input clock |
Clocks for DMPAC0 Device¶
Device: J721E_DEV_DMPAC0 (ID = 48)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DMPAC0_CLK | Input clock |
| 1 | DEV_DMPAC0_PLL_DCO_CLK | Input clock |
Clocks for DMPAC0_SDE_0 Device¶
Device: J721E_DEV_DMPAC0_SDE_0 (ID = 305)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DMPAC0_SDE_0_CLK | Input clock |
Clocks for DPHY_RX0 Device¶
Device: J721E_DEV_DPHY_RX0 (ID = 147)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DPHY_RX0_MAIN_CLK_CLK | Input clock |
| 1 | DEV_DPHY_RX0_PPI_RX_BYTE_CLK | Output clock |
Clocks for DPHY_RX1 Device¶
Device: J721E_DEV_DPHY_RX1 (ID = 148)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DPHY_RX1_MAIN_CLK_CLK | Input clock |
| 1 | DEV_DPHY_RX1_PPI_RX_BYTE_CLK | Output clock |
Clocks for DPHY_TX0 Device¶
Device: J721E_DEV_DPHY_TX0 (ID = 296)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DPHY_TX0_CLK | Input clock |
| 1 | DEV_DPHY_TX0_PSM_CLK | Input clock |
| 2 | DEV_DPHY_TX0_IP1_PPI_M_TXCLKESC_CLK | Input clock |
| 3 | DEV_DPHY_TX0_DPHY_REF_CLK | Input muxed clock |
| 4 | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK |
| 5 | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK |
| 6 | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK |
| 7 | DEV_DPHY_TX0_DPHY_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | Parent input clock option to DEV_DPHY_TX0_DPHY_REF_CLK |
| 8 | DEV_DPHY_TX0_IP1_PPI_TXBYTECLKHS_CL_CLK | Output clock |
| 9 | DEV_DPHY_TX0_IP1_PPI_M_RXCLKESC_CLK | Output clock |
| 10 | DEV_DPHY_TX0_CK_P | Output clock |
| 11 | DEV_DPHY_TX0_CK_M | Output clock |
| 12 | DEV_DPHY_TX0_IP2_PPI_TXBYTECLKHS_CL_CLK | Output clock |
Clocks for DSS0 Device¶
Device: J721E_DEV_DSS0 (ID = 152)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DSS0_DSS_FUNC_CLK | Input clock |
| 1 | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK | Input muxed clock |
| 2 | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK | Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK |
| 3 | DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK_PARENT_DPI_1_PCLK_SEL_OUT0 | Parent input clock option to DEV_DSS0_DSS_INST0_DPI_0_IN_2X_CLK |
| 4 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK | Input muxed clock |
| 5 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT0_CLK | Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK |
| 6 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0 | Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK |
| 7 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI1_EXT_CLKSEL_OUT0 | Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK |
| 8 | DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK | Parent input clock option to DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK |
| 9 | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK | Input muxed clock |
| 10 | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT0_CLK | Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK |
| 11 | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT0_CLK | Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK |
| 12 | DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0 | Parent input clock option to DEV_DSS0_DSS_INST0_DPI_2_IN_2X_CLK |
| 13 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK | Input muxed clock |
| 14 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_16_HSDIVOUT1_CLK | Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK |
| 15 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_17_HSDIVOUT1_CLK | Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK |
| 16 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_HSDIV1_16FFT_MAIN_18_HSDIVOUT1_CLK | Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK |
| 17 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0 | Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK |
| 18 | DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK_PARENT_DPI1_EXT_CLKSEL_OUT0 | Parent input clock option to DEV_DSS0_DSS_INST0_DPI_3_IN_2X_CLK |
| 23 | DEV_DSS0_DSS_INST0_DPI_0_OUT_CLK | Output clock |
| 24 | DEV_DSS0_DSS_INST0_DPI_0_OUT_2X_CLK | Output clock |
| 25 | DEV_DSS0_DSS_INST0_DPI_1_OUT_CLK | Output clock |
| 27 | DEV_DSS0_DSS_INST0_DPI_2_OUT_CLK | Output clock |
| 29 | DEV_DSS0_DSS_INST0_DPI_3_OUT_CLK | Output clock |
| 31 | DEV_DSS0_DPI0_EXT_CLKSEL | Input muxed clock |
| 32 | DEV_DSS0_DPI0_EXT_CLKSEL_PARENT_HSDIV1_16FFT_MAIN_19_HSDIVOUT0_CLK | Parent input clock option to DEV_DSS0_DPI0_EXT_CLKSEL |
| 33 | DEV_DSS0_DPI0_EXT_CLKSEL_PARENT_BOARD_0_VOUT1_EXTPCLKIN_OUT | Parent input clock option to DEV_DSS0_DPI0_EXT_CLKSEL |
| 34 | DEV_DSS0_DPI1_EXT_CLKSEL | Input muxed clock |
| 35 | DEV_DSS0_DPI1_EXT_CLKSEL_PARENT_HSDIV1_16FFT_MAIN_23_HSDIVOUT0_CLK | Parent input clock option to DEV_DSS0_DPI1_EXT_CLKSEL |
| 36 | DEV_DSS0_DPI1_EXT_CLKSEL_PARENT_BOARD_0_VOUT2_EXTPCLKIN_OUT | Parent input clock option to DEV_DSS0_DPI1_EXT_CLKSEL |
Clocks for DSS_DSI0 Device¶
Device: J721E_DEV_DSS_DSI0 (ID = 150)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DSS_DSI0_DPHY_0_RX_ESC_CLK | Input clock |
| 1 | DEV_DSS_DSI0_DPI_0_CLK | Input clock |
| 2 | DEV_DSS_DSI0_PLL_CTRL_CLK | Input clock |
| 3 | DEV_DSS_DSI0_PPI_0_TXBYTECLKHS_CL_CLK | Input clock |
| 4 | DEV_DSS_DSI0_DPHY_0_TX_ESC_CLK | Input clock |
| 5 | DEV_DSS_DSI0_SYS_CLK | Input clock |
Clocks for DSS_EDP0 Device¶
Device: J721E_DEV_DSS_EDP0 (ID = 151)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_DSS_EDP0_PHY_LN1_TXFCLK | Input clock |
| 1 | DEV_DSS_EDP0_DPI_2_CLK | Input clock |
| 2 | DEV_DSS_EDP0_PHY_LN2_TXFCLK | Input clock |
| 3 | DEV_DSS_EDP0_PHY_LN0_RXCLK | Input clock |
| 4 | DEV_DSS_EDP0_PHY_LN2_TXMCLK | Input clock |
| 5 | DEV_DSS_EDP0_PHY_LN0_RXFCLK | Input clock |
| 6 | DEV_DSS_EDP0_PHY_LN0_REFCLK | Input clock |
| 7 | DEV_DSS_EDP0_PHY_LN1_RXCLK | Input clock |
| 8 | DEV_DSS_EDP0_PHY_LN2_RXFCLK | Input clock |
| 9 | DEV_DSS_EDP0_DPI_4_CLK | Input clock |
| 10 | DEV_DSS_EDP0_DPI_2_2X_CLK | Input clock |
| 11 | DEV_DSS_EDP0_PHY_LN0_TXFCLK | Input clock |
| 12 | DEV_DSS_EDP0_PHY_LN2_RXCLK | Input clock |
| 13 | DEV_DSS_EDP0_PHY_LN2_REFCLK | Input clock |
| 14 | DEV_DSS_EDP0_PHY_LN3_REFCLK | Input clock |
| 15 | DEV_DSS_EDP0_DPI_5_CLK | Input clock |
| 16 | DEV_DSS_EDP0_PHY_LN3_RXCLK | Input clock |
| 17 | DEV_DSS_EDP0_PHY_LN1_REFCLK | Input clock |
| 18 | DEV_DSS_EDP0_AIF_I2S_CLK | Input clock |
| 19 | DEV_DSS_EDP0_PHY_LN3_TXFCLK | Input clock |
| 20 | DEV_DSS_EDP0_DPI_3_CLK | Input clock |
| 21 | DEV_DSS_EDP0_PHY_LN1_RXFCLK | Input clock |
| 22 | DEV_DSS_EDP0_PHY_LN1_TXMCLK | Input clock |
| 23 | DEV_DSS_EDP0_PLL_CTRL_CLK | Input clock |
| 24 | DEV_DSS_EDP0_PHY_LN3_TXMCLK | Input clock |
| 25 | DEV_DSS_EDP0_PHY_LN3_RXFCLK | Input clock |
| 26 | DEV_DSS_EDP0_PHY_LN0_TXMCLK | Input clock |
| 27 | DEV_DSS_EDP0_PHY_LN2_TXCLK | Output clock |
| 28 | DEV_DSS_EDP0_PHY_LN3_TXCLK | Output clock |
| 29 | DEV_DSS_EDP0_PHY_LN0_TXCLK | Output clock |
| 30 | DEV_DSS_EDP0_PHY_LN1_TXCLK | Output clock |
| 36 | DEV_DSS_EDP0_DPTX_MOD_CLK | Input clock |
Clocks for ECAP0 Device¶
Device: J721E_DEV_ECAP0 (ID = 80)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_ECAP0_VBUS_CLK | Input clock |
Clocks for ECAP1 Device¶
Device: J721E_DEV_ECAP1 (ID = 81)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_ECAP1_VBUS_CLK | Input clock |
Clocks for ECAP2 Device¶
Device: J721E_DEV_ECAP2 (ID = 82)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_ECAP2_VBUS_CLK | Input clock |
Clocks for EHRPWM0 Device¶
Device: J721E_DEV_EHRPWM0 (ID = 83)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_EHRPWM0_VBUSP_CLK | Input clock |
Clocks for EHRPWM1 Device¶
Device: J721E_DEV_EHRPWM1 (ID = 84)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_EHRPWM1_VBUSP_CLK | Input clock |
Clocks for EHRPWM2 Device¶
Device: J721E_DEV_EHRPWM2 (ID = 85)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_EHRPWM2_VBUSP_CLK | Input clock |
Clocks for EHRPWM3 Device¶
Device: J721E_DEV_EHRPWM3 (ID = 86)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_EHRPWM3_VBUSP_CLK | Input clock |
Clocks for EHRPWM4 Device¶
Device: J721E_DEV_EHRPWM4 (ID = 87)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_EHRPWM4_VBUSP_CLK | Input clock |
Clocks for EHRPWM5 Device¶
Device: J721E_DEV_EHRPWM5 (ID = 88)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_EHRPWM5_VBUSP_CLK | Input clock |
Clocks for ELM0 Device¶
Device: J721E_DEV_ELM0 (ID = 89)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_ELM0_VBUSP_CLK | Input clock |
Clocks for EMIF_DATA_0_VD Device¶
This device has no defined clocks.
Clocks for ENCODER0 Device¶
Device: J721E_DEV_ENCODER0 (ID = 153)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_ENCODER0_SYS_CLK | Input clock |
Clocks for EQEP0 Device¶
Device: J721E_DEV_EQEP0 (ID = 94)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_EQEP0_VBUS_CLK | Input clock |
Clocks for EQEP1 Device¶
Device: J721E_DEV_EQEP1 (ID = 95)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_EQEP1_VBUS_CLK | Input clock |
Clocks for EQEP2 Device¶
Device: J721E_DEV_EQEP2 (ID = 96)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_EQEP2_VBUS_CLK | Input clock |
Clocks for ESM0 Device¶
Device: J721E_DEV_ESM0 (ID = 97)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_ESM0_CLK | Input clock |
Clocks for GPIO0 Device¶
Device: J721E_DEV_GPIO0 (ID = 105)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_GPIO0_MMR_CLK | Input clock |
Clocks for GPIO1 Device¶
Device: J721E_DEV_GPIO1 (ID = 106)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_GPIO1_MMR_CLK | Input clock |
Clocks for GPIO2 Device¶
Device: J721E_DEV_GPIO2 (ID = 107)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_GPIO2_MMR_CLK | Input clock |
Clocks for GPIO3 Device¶
Device: J721E_DEV_GPIO3 (ID = 108)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_GPIO3_MMR_CLK | Input clock |
Clocks for GPIO4 Device¶
Device: J721E_DEV_GPIO4 (ID = 109)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_GPIO4_MMR_CLK | Input clock |
Clocks for GPIO5 Device¶
Device: J721E_DEV_GPIO5 (ID = 110)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_GPIO5_MMR_CLK | Input clock |
Clocks for GPIO6 Device¶
Device: J721E_DEV_GPIO6 (ID = 111)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_GPIO6_MMR_CLK | Input clock |
Clocks for GPIO7 Device¶
Device: J721E_DEV_GPIO7 (ID = 112)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_GPIO7_MMR_CLK | Input clock |
Clocks for GPIOMUX_INTRTR0 Device¶
Device: J721E_DEV_GPIOMUX_INTRTR0 (ID = 131)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_GPIOMUX_INTRTR0_INTR_CLK | Input clock |
Clocks for GPMC0 Device¶
Device: J721E_DEV_GPMC0 (ID = 115)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_GPMC0_PI_GPMC_RET_CLK | Input clock |
| 1 | DEV_GPMC0_VBUSP_CLK | Input clock |
| 2 | DEV_GPMC0_FUNC_CLK | Input muxed clock |
| 3 | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK | Parent input clock option to DEV_GPMC0_FUNC_CLK |
| 4 | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK6 | Parent input clock option to DEV_GPMC0_FUNC_CLK |
| 5 | DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT1_CLK4 | Parent input clock option to DEV_GPMC0_FUNC_CLK |
| 6 | DEV_GPMC0_FUNC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK4 | Parent input clock option to DEV_GPMC0_FUNC_CLK |
| 7 | DEV_GPMC0_PO_GPMC_DEV_CLK | Output clock |
Clocks for GPU0 Device¶
This device has no defined clocks.
Clocks for GPU0_DFT_PBIST_0 Device¶
This device has no defined clocks.
Clocks for GPU0_GPUCORE_0 Device¶
This device has no defined clocks.
Clocks for GPU0_GPU_0 Device¶
Device: J721E_DEV_GPU0_GPU_0 (ID = 125)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_GPU0_GPU_0_GPU_PLL_CLK | Input clock |
Clocks for GTC0 Device¶
Device: J721E_DEV_GTC0 (ID = 61)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_GTC0_VBUSP_CLK | Input clock |
| 1 | DEV_GTC0_GTC_CLK | Input muxed clock |
| 2 | DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | Parent input clock option to DEV_GTC0_GTC_CLK |
| 3 | DEV_GTC0_GTC_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | Parent input clock option to DEV_GTC0_GTC_CLK |
| 4 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_GTC0_GTC_CLK |
| 5 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_GTC0_GTC_CLK |
| 6 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_GTC0_GTC_CLK |
| 7 | DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_GTC0_GTC_CLK |
| 8 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK | Parent input clock option to DEV_GTC0_GTC_CLK |
| 9 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK | Parent input clock option to DEV_GTC0_GTC_CLK |
| 10 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK | Parent input clock option to DEV_GTC0_GTC_CLK |
| 11 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK | Parent input clock option to DEV_GTC0_GTC_CLK |
| 12 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK | Parent input clock option to DEV_GTC0_GTC_CLK |
| 13 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK | Parent input clock option to DEV_GTC0_GTC_CLK |
| 14 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK | Parent input clock option to DEV_GTC0_GTC_CLK |
| 15 | DEV_GTC0_GTC_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK | Parent input clock option to DEV_GTC0_GTC_CLK |
| 16 | DEV_GTC0_GTC_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | Parent input clock option to DEV_GTC0_GTC_CLK |
| 17 | DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | Parent input clock option to DEV_GTC0_GTC_CLK |
Clocks for I2C0 Device¶
Device: J721E_DEV_I2C0 (ID = 187)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_I2C0_PISYS_CLK | Input clock |
| 1 | DEV_I2C0_PISCL | Input clock |
| 2 | DEV_I2C0_CLK | Input clock |
| 3 | DEV_I2C0_PORSCL | Output clock |
Clocks for I2C1 Device¶
Device: J721E_DEV_I2C1 (ID = 188)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_I2C1_PISYS_CLK | Input clock |
| 1 | DEV_I2C1_PISCL | Input clock |
| 2 | DEV_I2C1_CLK | Input clock |
| 3 | DEV_I2C1_PORSCL | Output clock |
Clocks for I2C2 Device¶
Device: J721E_DEV_I2C2 (ID = 189)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_I2C2_PISYS_CLK | Input clock |
| 1 | DEV_I2C2_PISCL | Input clock |
| 2 | DEV_I2C2_CLK | Input clock |
| 3 | DEV_I2C2_PORSCL | Output clock |
Clocks for I2C3 Device¶
Device: J721E_DEV_I2C3 (ID = 190)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_I2C3_PISYS_CLK | Input clock |
| 1 | DEV_I2C3_PISCL | Input clock |
| 2 | DEV_I2C3_CLK | Input clock |
| 3 | DEV_I2C3_PORSCL | Output clock |
Clocks for I2C4 Device¶
Device: J721E_DEV_I2C4 (ID = 191)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_I2C4_PISYS_CLK | Input clock |
| 1 | DEV_I2C4_PISCL | Input clock |
| 2 | DEV_I2C4_CLK | Input clock |
| 3 | DEV_I2C4_PORSCL | Output clock |
Clocks for I2C5 Device¶
Device: J721E_DEV_I2C5 (ID = 192)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_I2C5_PISYS_CLK | Input clock |
| 1 | DEV_I2C5_PISCL | Input clock |
| 2 | DEV_I2C5_CLK | Input clock |
| 3 | DEV_I2C5_PORSCL | Output clock |
Clocks for I2C6 Device¶
Device: J721E_DEV_I2C6 (ID = 193)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_I2C6_PISYS_CLK | Input clock |
| 1 | DEV_I2C6_PISCL | Input clock |
| 2 | DEV_I2C6_CLK | Input clock |
| 3 | DEV_I2C6_PORSCL | Output clock |
Clocks for I3C0 Device¶
Device: J721E_DEV_I3C0 (ID = 116)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_I3C0_I3C_PCLK_CLK | Input clock |
| 1 | DEV_I3C0_I3C_SCL_DI | Input clock |
| 2 | DEV_I3C0_I3C_SCLK_CLK | Input clock |
| 3 | DEV_I3C0_I3C_SCL_DO | Output clock |
Clocks for LED0 Device¶
Device: J721E_DEV_LED0 (ID = 127)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_LED0_LED_CLK | Input clock |
| 1 | DEV_LED0_VBUS_CLK | Input clock |
Clocks for MAIN2MCU_LVL_INTRTR0 Device¶
Device: J721E_DEV_MAIN2MCU_LVL_INTRTR0 (ID = 128)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MAIN2MCU_LVL_INTRTR0_INTR_CLK | Input clock |
Clocks for MAIN2MCU_PLS_INTRTR0 Device¶
Device: J721E_DEV_MAIN2MCU_PLS_INTRTR0 (ID = 130)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MAIN2MCU_PLS_INTRTR0_INTR_CLK | Input clock |
Clocks for MAIN2WKUPMCU_VD Device¶
This device has no defined clocks.
Clocks for MAIN_PLL8_SEL_EXTWAVE_VD Device¶
Device: J721E_DEV_MAIN_PLL8_SEL_EXTWAVE_VD (ID = 342)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MAIN_PLL8_SEL_EXTWAVE_VD_CLK | Input muxed clock |
| 1 | DEV_MAIN_PLL8_SEL_EXTWAVE_VD_CLK_PARENT_PLLFRAC2_SSMOD_16FFT_MAIN_8_FOUTVCOP_CLK | Parent input clock option to DEV_MAIN_PLL8_SEL_EXTWAVE_VD_CLK |
| 2 | DEV_MAIN_PLL8_SEL_EXTWAVE_VD_CLK_PARENT_HSDIV0_16FFT_MAIN_8_HSDIVOUT0_CLK | Parent input clock option to DEV_MAIN_PLL8_SEL_EXTWAVE_VD_CLK |
Clocks for MCAN0 Device¶
Device: J721E_DEV_MCAN0 (ID = 156)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCAN0_MCANSS_HCLK_CLK | Input clock |
| 1 | DEV_MCAN0_MCANSS_CCLK_CLK | Input muxed clock |
| 2 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK |
| 3 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK |
| 4 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK |
| 5 | DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCAN0_MCANSS_CCLK_CLK |
Clocks for MCAN1 Device¶
Device: J721E_DEV_MCAN1 (ID = 158)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCAN1_MCANSS_HCLK_CLK | Input clock |
| 1 | DEV_MCAN1_MCANSS_CCLK_CLK | Input muxed clock |
| 2 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK |
| 3 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK |
| 4 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK |
| 5 | DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCAN1_MCANSS_CCLK_CLK |
Clocks for MCAN10 Device¶
Device: J721E_DEV_MCAN10 (ID = 168)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCAN10_MCANSS_HCLK_CLK | Input clock |
| 1 | DEV_MCAN10_MCANSS_CCLK_CLK | Input muxed clock |
| 2 | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK |
| 3 | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK |
| 4 | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK |
| 5 | DEV_MCAN10_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCAN10_MCANSS_CCLK_CLK |
Clocks for MCAN11 Device¶
Device: J721E_DEV_MCAN11 (ID = 169)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCAN11_MCANSS_HCLK_CLK | Input clock |
| 1 | DEV_MCAN11_MCANSS_CCLK_CLK | Input muxed clock |
| 2 | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK |
| 3 | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK |
| 4 | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK |
| 5 | DEV_MCAN11_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCAN11_MCANSS_CCLK_CLK |
Clocks for MCAN12 Device¶
Device: J721E_DEV_MCAN12 (ID = 170)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCAN12_MCANSS_HCLK_CLK | Input clock |
| 1 | DEV_MCAN12_MCANSS_CCLK_CLK | Input muxed clock |
| 2 | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK |
| 3 | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK |
| 4 | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK |
| 5 | DEV_MCAN12_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCAN12_MCANSS_CCLK_CLK |
Clocks for MCAN13 Device¶
Device: J721E_DEV_MCAN13 (ID = 171)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCAN13_MCANSS_HCLK_CLK | Input clock |
| 1 | DEV_MCAN13_MCANSS_CCLK_CLK | Input muxed clock |
| 2 | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK |
| 3 | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK |
| 4 | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK |
| 5 | DEV_MCAN13_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCAN13_MCANSS_CCLK_CLK |
Clocks for MCAN2 Device¶
Device: J721E_DEV_MCAN2 (ID = 160)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCAN2_MCANSS_HCLK_CLK | Input clock |
| 1 | DEV_MCAN2_MCANSS_CCLK_CLK | Input muxed clock |
| 2 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK |
| 3 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK |
| 4 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK |
| 5 | DEV_MCAN2_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCAN2_MCANSS_CCLK_CLK |
Clocks for MCAN3 Device¶
Device: J721E_DEV_MCAN3 (ID = 161)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCAN3_MCANSS_HCLK_CLK | Input clock |
| 1 | DEV_MCAN3_MCANSS_CCLK_CLK | Input muxed clock |
| 2 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK |
| 3 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK |
| 4 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK |
| 5 | DEV_MCAN3_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCAN3_MCANSS_CCLK_CLK |
Clocks for MCAN4 Device¶
Device: J721E_DEV_MCAN4 (ID = 162)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCAN4_MCANSS_HCLK_CLK | Input clock |
| 1 | DEV_MCAN4_MCANSS_CCLK_CLK | Input muxed clock |
| 2 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK |
| 3 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK |
| 4 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK |
| 5 | DEV_MCAN4_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCAN4_MCANSS_CCLK_CLK |
Clocks for MCAN5 Device¶
Device: J721E_DEV_MCAN5 (ID = 163)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCAN5_MCANSS_HCLK_CLK | Input clock |
| 1 | DEV_MCAN5_MCANSS_CCLK_CLK | Input muxed clock |
| 2 | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK |
| 3 | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK |
| 4 | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK |
| 5 | DEV_MCAN5_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCAN5_MCANSS_CCLK_CLK |
Clocks for MCAN6 Device¶
Device: J721E_DEV_MCAN6 (ID = 164)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCAN6_MCANSS_HCLK_CLK | Input clock |
| 1 | DEV_MCAN6_MCANSS_CCLK_CLK | Input muxed clock |
| 2 | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK |
| 3 | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK |
| 4 | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK |
| 5 | DEV_MCAN6_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCAN6_MCANSS_CCLK_CLK |
Clocks for MCAN7 Device¶
Device: J721E_DEV_MCAN7 (ID = 165)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCAN7_MCANSS_HCLK_CLK | Input clock |
| 1 | DEV_MCAN7_MCANSS_CCLK_CLK | Input muxed clock |
| 2 | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK |
| 3 | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK |
| 4 | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK |
| 5 | DEV_MCAN7_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCAN7_MCANSS_CCLK_CLK |
Clocks for MCAN8 Device¶
Device: J721E_DEV_MCAN8 (ID = 166)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCAN8_MCANSS_HCLK_CLK | Input clock |
| 1 | DEV_MCAN8_MCANSS_CCLK_CLK | Input muxed clock |
| 2 | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK |
| 3 | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK |
| 4 | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK |
| 5 | DEV_MCAN8_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCAN8_MCANSS_CCLK_CLK |
Clocks for MCAN9 Device¶
Device: J721E_DEV_MCAN9 (ID = 167)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCAN9_MCANSS_HCLK_CLK | Input clock |
| 1 | DEV_MCAN9_MCANSS_CCLK_CLK | Input muxed clock |
| 2 | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK | Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK |
| 3 | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK |
| 4 | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK |
| 5 | DEV_MCAN9_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCAN9_MCANSS_CCLK_CLK |
Clocks for MCASP0 Device¶
Device: J721E_DEV_MCASP0 (ID = 174)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCASP0_VBUSP_CLK | Input clock |
| 1 | DEV_MCASP0_AUX_CLK | Input muxed clock |
| 2 | DEV_MCASP0_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP0_AUX_CLK |
| 3 | DEV_MCASP0_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MCASP0_AUX_CLK |
| 4 | DEV_MCASP0_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP0_AUX_CLK |
| 6 | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP0_AUX_CLK |
| 7 | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP0_AUX_CLK |
| 8 | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP0_AUX_CLK |
| 9 | DEV_MCASP0_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP0_AUX_CLK |
| 10 | DEV_MCASP0_MCASP_ACLKX_POUT | Output clock |
| 11 | DEV_MCASP0_MCASP_ACLKX_PIN | Input clock |
| 12 | DEV_MCASP0_MCASP_ACLKR_POUT | Output clock |
| 13 | DEV_MCASP0_MCASP_ACLKR_PIN | Input clock |
| 14 | DEV_MCASP0_MCASP_AHCLKX_POUT | Output clock |
| 15 | DEV_MCASP0_MCASP_AHCLKX_PIN | Input muxed clock |
| 16 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN |
| 17 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN |
| 18 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN |
| 19 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN |
| 20 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN |
| 21 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN |
| 22 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN |
| 23 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN |
| 24 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN |
| 25 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN |
| 26 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN |
| 27 | DEV_MCASP0_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKX_PIN |
| 28 | DEV_MCASP0_MCASP_AHCLKR_POUT | Output clock |
| 29 | DEV_MCASP0_MCASP_AHCLKR_PIN | Input muxed clock |
| 30 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN |
| 31 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN |
| 32 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN |
| 33 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN |
| 34 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN |
| 35 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN |
| 36 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN |
| 37 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN |
| 38 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN |
| 39 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN |
| 40 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN |
| 41 | DEV_MCASP0_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP0_MCASP_AHCLKR_PIN |
Clocks for MCASP1 Device¶
Device: J721E_DEV_MCASP1 (ID = 175)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCASP1_VBUSP_CLK | Input clock |
| 1 | DEV_MCASP1_AUX_CLK | Input muxed clock |
| 2 | DEV_MCASP1_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP1_AUX_CLK |
| 3 | DEV_MCASP1_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MCASP1_AUX_CLK |
| 4 | DEV_MCASP1_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP1_AUX_CLK |
| 6 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP1_AUX_CLK |
| 7 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP1_AUX_CLK |
| 8 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP1_AUX_CLK |
| 9 | DEV_MCASP1_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP1_AUX_CLK |
| 10 | DEV_MCASP1_MCASP_ACLKX_POUT | Output clock |
| 11 | DEV_MCASP1_MCASP_ACLKX_PIN | Input clock |
| 12 | DEV_MCASP1_MCASP_ACLKR_POUT | Output clock |
| 13 | DEV_MCASP1_MCASP_ACLKR_PIN | Input clock |
| 14 | DEV_MCASP1_MCASP_AHCLKX_POUT | Output clock |
| 15 | DEV_MCASP1_MCASP_AHCLKX_PIN | Input muxed clock |
| 16 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 17 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 18 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 19 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 20 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 21 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 22 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 23 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 24 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 25 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 26 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 27 | DEV_MCASP1_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKX_PIN |
| 28 | DEV_MCASP1_MCASP_AHCLKR_POUT | Output clock |
| 29 | DEV_MCASP1_MCASP_AHCLKR_PIN | Input muxed clock |
| 30 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 31 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 32 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 33 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 34 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 35 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 36 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 37 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 38 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 39 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 40 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
| 41 | DEV_MCASP1_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP1_MCASP_AHCLKR_PIN |
Clocks for MCASP10 Device¶
Device: J721E_DEV_MCASP10 (ID = 184)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCASP10_VBUSP_CLK | Input clock |
| 1 | DEV_MCASP10_AUX_CLK | Input muxed clock |
| 2 | DEV_MCASP10_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP10_AUX_CLK |
| 3 | DEV_MCASP10_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MCASP10_AUX_CLK |
| 4 | DEV_MCASP10_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP10_AUX_CLK |
| 6 | DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP10_AUX_CLK |
| 7 | DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP10_AUX_CLK |
| 8 | DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP10_AUX_CLK |
| 9 | DEV_MCASP10_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP10_AUX_CLK |
| 10 | DEV_MCASP10_MCASP_ACLKX_POUT | Output clock |
| 11 | DEV_MCASP10_MCASP_ACLKX_PIN | Input clock |
| 12 | DEV_MCASP10_MCASP_ACLKR_POUT | Output clock |
| 13 | DEV_MCASP10_MCASP_ACLKR_PIN | Input clock |
| 14 | DEV_MCASP10_MCASP_AHCLKX_POUT | Output clock |
| 15 | DEV_MCASP10_MCASP_AHCLKX_PIN | Input muxed clock |
| 16 | DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN |
| 17 | DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN |
| 18 | DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN |
| 19 | DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN |
| 20 | DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN |
| 21 | DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN |
| 22 | DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN |
| 23 | DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN |
| 24 | DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN |
| 25 | DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN |
| 26 | DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN |
| 27 | DEV_MCASP10_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP10_MCASP_AHCLKX_PIN |
| 28 | DEV_MCASP10_MCASP_AHCLKR_POUT | Output clock |
| 29 | DEV_MCASP10_MCASP_AHCLKR_PIN | Input muxed clock |
| 30 | DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN |
| 31 | DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN |
| 32 | DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN |
| 33 | DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN |
| 34 | DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN |
| 35 | DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN |
| 36 | DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN |
| 37 | DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN |
| 38 | DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN |
| 39 | DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN |
| 40 | DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN |
| 41 | DEV_MCASP10_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP10_MCASP_AHCLKR_PIN |
Clocks for MCASP11 Device¶
Device: J721E_DEV_MCASP11 (ID = 185)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCASP11_VBUSP_CLK | Input clock |
| 1 | DEV_MCASP11_AUX_CLK | Input muxed clock |
| 2 | DEV_MCASP11_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP11_AUX_CLK |
| 3 | DEV_MCASP11_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MCASP11_AUX_CLK |
| 4 | DEV_MCASP11_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP11_AUX_CLK |
| 6 | DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP11_AUX_CLK |
| 7 | DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP11_AUX_CLK |
| 8 | DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP11_AUX_CLK |
| 9 | DEV_MCASP11_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP11_AUX_CLK |
| 10 | DEV_MCASP11_MCASP_ACLKX_POUT | Output clock |
| 11 | DEV_MCASP11_MCASP_ACLKX_PIN | Input clock |
| 12 | DEV_MCASP11_MCASP_ACLKR_POUT | Output clock |
| 13 | DEV_MCASP11_MCASP_ACLKR_PIN | Input clock |
| 14 | DEV_MCASP11_MCASP_AHCLKX_POUT | Output clock |
| 15 | DEV_MCASP11_MCASP_AHCLKX_PIN | Input muxed clock |
| 16 | DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN |
| 17 | DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN |
| 18 | DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN |
| 19 | DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN |
| 20 | DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN |
| 21 | DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN |
| 22 | DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN |
| 23 | DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN |
| 24 | DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN |
| 25 | DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN |
| 26 | DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN |
| 27 | DEV_MCASP11_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP11_MCASP_AHCLKX_PIN |
| 28 | DEV_MCASP11_MCASP_AHCLKR_POUT | Output clock |
| 29 | DEV_MCASP11_MCASP_AHCLKR_PIN | Input muxed clock |
| 30 | DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN |
| 31 | DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN |
| 32 | DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN |
| 33 | DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN |
| 34 | DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN |
| 35 | DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN |
| 36 | DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN |
| 37 | DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN |
| 38 | DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN |
| 39 | DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN |
| 40 | DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN |
| 41 | DEV_MCASP11_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP11_MCASP_AHCLKR_PIN |
Clocks for MCASP2 Device¶
Device: J721E_DEV_MCASP2 (ID = 176)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCASP2_VBUSP_CLK | Input clock |
| 1 | DEV_MCASP2_AUX_CLK | Input muxed clock |
| 2 | DEV_MCASP2_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP2_AUX_CLK |
| 3 | DEV_MCASP2_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MCASP2_AUX_CLK |
| 4 | DEV_MCASP2_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP2_AUX_CLK |
| 6 | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP2_AUX_CLK |
| 7 | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP2_AUX_CLK |
| 8 | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP2_AUX_CLK |
| 9 | DEV_MCASP2_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP2_AUX_CLK |
| 10 | DEV_MCASP2_MCASP_ACLKX_POUT | Output clock |
| 11 | DEV_MCASP2_MCASP_ACLKX_PIN | Input clock |
| 12 | DEV_MCASP2_MCASP_ACLKR_POUT | Output clock |
| 13 | DEV_MCASP2_MCASP_ACLKR_PIN | Input clock |
| 14 | DEV_MCASP2_MCASP_AHCLKX_POUT | Output clock |
| 15 | DEV_MCASP2_MCASP_AHCLKX_PIN | Input muxed clock |
| 16 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN |
| 17 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN |
| 18 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN |
| 19 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN |
| 20 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN |
| 21 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN |
| 22 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN |
| 23 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN |
| 24 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN |
| 25 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN |
| 26 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN |
| 27 | DEV_MCASP2_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKX_PIN |
| 28 | DEV_MCASP2_MCASP_AHCLKR_POUT | Output clock |
| 29 | DEV_MCASP2_MCASP_AHCLKR_PIN | Input muxed clock |
| 30 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN |
| 31 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN |
| 32 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN |
| 33 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN |
| 34 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN |
| 35 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN |
| 36 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN |
| 37 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN |
| 38 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN |
| 39 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN |
| 40 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN |
| 41 | DEV_MCASP2_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP2_MCASP_AHCLKR_PIN |
Clocks for MCASP3 Device¶
Device: J721E_DEV_MCASP3 (ID = 177)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCASP3_VBUSP_CLK | Input clock |
| 1 | DEV_MCASP3_AUX_CLK | Input muxed clock |
| 2 | DEV_MCASP3_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP3_AUX_CLK |
| 3 | DEV_MCASP3_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MCASP3_AUX_CLK |
| 4 | DEV_MCASP3_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP3_AUX_CLK |
| 6 | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP3_AUX_CLK |
| 7 | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP3_AUX_CLK |
| 8 | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP3_AUX_CLK |
| 9 | DEV_MCASP3_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP3_AUX_CLK |
| 10 | DEV_MCASP3_MCASP_ACLKX_POUT | Output clock |
| 11 | DEV_MCASP3_MCASP_ACLKX_PIN | Input clock |
| 12 | DEV_MCASP3_MCASP_ACLKR_POUT | Output clock |
| 13 | DEV_MCASP3_MCASP_ACLKR_PIN | Input clock |
| 14 | DEV_MCASP3_MCASP_AHCLKX_POUT | Output clock |
| 15 | DEV_MCASP3_MCASP_AHCLKX_PIN | Input muxed clock |
| 16 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN |
| 17 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN |
| 18 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN |
| 19 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN |
| 20 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN |
| 21 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN |
| 22 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN |
| 23 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN |
| 24 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN |
| 25 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN |
| 26 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN |
| 27 | DEV_MCASP3_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKX_PIN |
| 28 | DEV_MCASP3_MCASP_AHCLKR_POUT | Output clock |
| 29 | DEV_MCASP3_MCASP_AHCLKR_PIN | Input muxed clock |
| 30 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN |
| 31 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN |
| 32 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN |
| 33 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN |
| 34 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN |
| 35 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN |
| 36 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN |
| 37 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN |
| 38 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN |
| 39 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN |
| 40 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN |
| 41 | DEV_MCASP3_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP3_MCASP_AHCLKR_PIN |
Clocks for MCASP4 Device¶
Device: J721E_DEV_MCASP4 (ID = 178)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCASP4_VBUSP_CLK | Input clock |
| 1 | DEV_MCASP4_AUX_CLK | Input muxed clock |
| 2 | DEV_MCASP4_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP4_AUX_CLK |
| 3 | DEV_MCASP4_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MCASP4_AUX_CLK |
| 4 | DEV_MCASP4_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP4_AUX_CLK |
| 6 | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP4_AUX_CLK |
| 7 | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP4_AUX_CLK |
| 8 | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP4_AUX_CLK |
| 9 | DEV_MCASP4_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP4_AUX_CLK |
| 10 | DEV_MCASP4_MCASP_ACLKX_POUT | Output clock |
| 11 | DEV_MCASP4_MCASP_ACLKX_PIN | Input clock |
| 12 | DEV_MCASP4_MCASP_ACLKR_POUT | Output clock |
| 13 | DEV_MCASP4_MCASP_ACLKR_PIN | Input clock |
| 14 | DEV_MCASP4_MCASP_AHCLKX_POUT | Output clock |
| 15 | DEV_MCASP4_MCASP_AHCLKX_PIN | Input muxed clock |
| 16 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN |
| 17 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN |
| 18 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN |
| 19 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN |
| 20 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN |
| 21 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN |
| 22 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN |
| 23 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN |
| 24 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN |
| 25 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN |
| 26 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN |
| 27 | DEV_MCASP4_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKX_PIN |
| 28 | DEV_MCASP4_MCASP_AHCLKR_POUT | Output clock |
| 29 | DEV_MCASP4_MCASP_AHCLKR_PIN | Input muxed clock |
| 30 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN |
| 31 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN |
| 32 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN |
| 33 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN |
| 34 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN |
| 35 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN |
| 36 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN |
| 37 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN |
| 38 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN |
| 39 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN |
| 40 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN |
| 41 | DEV_MCASP4_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP4_MCASP_AHCLKR_PIN |
Clocks for MCASP5 Device¶
Device: J721E_DEV_MCASP5 (ID = 179)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCASP5_VBUSP_CLK | Input clock |
| 1 | DEV_MCASP5_AUX_CLK | Input muxed clock |
| 2 | DEV_MCASP5_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP5_AUX_CLK |
| 3 | DEV_MCASP5_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MCASP5_AUX_CLK |
| 4 | DEV_MCASP5_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP5_AUX_CLK |
| 6 | DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP5_AUX_CLK |
| 7 | DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP5_AUX_CLK |
| 8 | DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP5_AUX_CLK |
| 9 | DEV_MCASP5_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP5_AUX_CLK |
| 10 | DEV_MCASP5_MCASP_ACLKX_POUT | Output clock |
| 11 | DEV_MCASP5_MCASP_ACLKX_PIN | Input clock |
| 12 | DEV_MCASP5_MCASP_ACLKR_POUT | Output clock |
| 13 | DEV_MCASP5_MCASP_ACLKR_PIN | Input clock |
| 14 | DEV_MCASP5_MCASP_AHCLKX_POUT | Output clock |
| 15 | DEV_MCASP5_MCASP_AHCLKX_PIN | Input muxed clock |
| 16 | DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN |
| 17 | DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN |
| 18 | DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN |
| 19 | DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN |
| 20 | DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN |
| 21 | DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN |
| 22 | DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN |
| 23 | DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN |
| 24 | DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN |
| 25 | DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN |
| 26 | DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN |
| 27 | DEV_MCASP5_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP5_MCASP_AHCLKX_PIN |
| 28 | DEV_MCASP5_MCASP_AHCLKR_POUT | Output clock |
| 29 | DEV_MCASP5_MCASP_AHCLKR_PIN | Input muxed clock |
| 30 | DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN |
| 31 | DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN |
| 32 | DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN |
| 33 | DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN |
| 34 | DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN |
| 35 | DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN |
| 36 | DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN |
| 37 | DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN |
| 38 | DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN |
| 39 | DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN |
| 40 | DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN |
| 41 | DEV_MCASP5_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP5_MCASP_AHCLKR_PIN |
Clocks for MCASP6 Device¶
Device: J721E_DEV_MCASP6 (ID = 180)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCASP6_VBUSP_CLK | Input clock |
| 1 | DEV_MCASP6_AUX_CLK | Input muxed clock |
| 2 | DEV_MCASP6_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP6_AUX_CLK |
| 3 | DEV_MCASP6_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MCASP6_AUX_CLK |
| 4 | DEV_MCASP6_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP6_AUX_CLK |
| 6 | DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP6_AUX_CLK |
| 7 | DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP6_AUX_CLK |
| 8 | DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP6_AUX_CLK |
| 9 | DEV_MCASP6_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP6_AUX_CLK |
| 10 | DEV_MCASP6_MCASP_ACLKX_POUT | Output clock |
| 11 | DEV_MCASP6_MCASP_ACLKX_PIN | Input clock |
| 12 | DEV_MCASP6_MCASP_ACLKR_POUT | Output clock |
| 13 | DEV_MCASP6_MCASP_ACLKR_PIN | Input clock |
| 14 | DEV_MCASP6_MCASP_AHCLKX_POUT | Output clock |
| 15 | DEV_MCASP6_MCASP_AHCLKX_PIN | Input muxed clock |
| 16 | DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN |
| 17 | DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN |
| 18 | DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN |
| 19 | DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN |
| 20 | DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN |
| 21 | DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN |
| 22 | DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN |
| 23 | DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN |
| 24 | DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN |
| 25 | DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN |
| 26 | DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN |
| 27 | DEV_MCASP6_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP6_MCASP_AHCLKX_PIN |
| 28 | DEV_MCASP6_MCASP_AHCLKR_POUT | Output clock |
| 29 | DEV_MCASP6_MCASP_AHCLKR_PIN | Input muxed clock |
| 30 | DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN |
| 31 | DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN |
| 32 | DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN |
| 33 | DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN |
| 34 | DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN |
| 35 | DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN |
| 36 | DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN |
| 37 | DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN |
| 38 | DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN |
| 39 | DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN |
| 40 | DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN |
| 41 | DEV_MCASP6_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP6_MCASP_AHCLKR_PIN |
Clocks for MCASP7 Device¶
Device: J721E_DEV_MCASP7 (ID = 181)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCASP7_VBUSP_CLK | Input clock |
| 1 | DEV_MCASP7_AUX_CLK | Input muxed clock |
| 2 | DEV_MCASP7_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP7_AUX_CLK |
| 3 | DEV_MCASP7_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MCASP7_AUX_CLK |
| 4 | DEV_MCASP7_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP7_AUX_CLK |
| 6 | DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP7_AUX_CLK |
| 7 | DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP7_AUX_CLK |
| 8 | DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP7_AUX_CLK |
| 9 | DEV_MCASP7_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP7_AUX_CLK |
| 10 | DEV_MCASP7_MCASP_ACLKX_POUT | Output clock |
| 11 | DEV_MCASP7_MCASP_ACLKX_PIN | Input clock |
| 12 | DEV_MCASP7_MCASP_ACLKR_POUT | Output clock |
| 13 | DEV_MCASP7_MCASP_ACLKR_PIN | Input clock |
| 14 | DEV_MCASP7_MCASP_AHCLKX_POUT | Output clock |
| 15 | DEV_MCASP7_MCASP_AHCLKX_PIN | Input muxed clock |
| 16 | DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN |
| 17 | DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN |
| 18 | DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN |
| 19 | DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN |
| 20 | DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN |
| 21 | DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN |
| 22 | DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN |
| 23 | DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN |
| 24 | DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN |
| 25 | DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN |
| 26 | DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN |
| 27 | DEV_MCASP7_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP7_MCASP_AHCLKX_PIN |
| 28 | DEV_MCASP7_MCASP_AHCLKR_POUT | Output clock |
| 29 | DEV_MCASP7_MCASP_AHCLKR_PIN | Input muxed clock |
| 30 | DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN |
| 31 | DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN |
| 32 | DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN |
| 33 | DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN |
| 34 | DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN |
| 35 | DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN |
| 36 | DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN |
| 37 | DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN |
| 38 | DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN |
| 39 | DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN |
| 40 | DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN |
| 41 | DEV_MCASP7_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP7_MCASP_AHCLKR_PIN |
Clocks for MCASP8 Device¶
Device: J721E_DEV_MCASP8 (ID = 182)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCASP8_VBUSP_CLK | Input clock |
| 1 | DEV_MCASP8_AUX_CLK | Input muxed clock |
| 2 | DEV_MCASP8_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP8_AUX_CLK |
| 3 | DEV_MCASP8_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MCASP8_AUX_CLK |
| 4 | DEV_MCASP8_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP8_AUX_CLK |
| 6 | DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP8_AUX_CLK |
| 7 | DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP8_AUX_CLK |
| 8 | DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP8_AUX_CLK |
| 9 | DEV_MCASP8_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP8_AUX_CLK |
| 10 | DEV_MCASP8_MCASP_ACLKX_POUT | Output clock |
| 11 | DEV_MCASP8_MCASP_ACLKX_PIN | Input clock |
| 12 | DEV_MCASP8_MCASP_ACLKR_POUT | Output clock |
| 13 | DEV_MCASP8_MCASP_ACLKR_PIN | Input clock |
| 14 | DEV_MCASP8_MCASP_AHCLKX_POUT | Output clock |
| 15 | DEV_MCASP8_MCASP_AHCLKX_PIN | Input muxed clock |
| 16 | DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN |
| 17 | DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN |
| 18 | DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN |
| 19 | DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN |
| 20 | DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN |
| 21 | DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN |
| 22 | DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN |
| 23 | DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN |
| 24 | DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN |
| 25 | DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN |
| 26 | DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN |
| 27 | DEV_MCASP8_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP8_MCASP_AHCLKX_PIN |
| 28 | DEV_MCASP8_MCASP_AHCLKR_POUT | Output clock |
| 29 | DEV_MCASP8_MCASP_AHCLKR_PIN | Input muxed clock |
| 30 | DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN |
| 31 | DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN |
| 32 | DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN |
| 33 | DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN |
| 34 | DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN |
| 35 | DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN |
| 36 | DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN |
| 37 | DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN |
| 38 | DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN |
| 39 | DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN |
| 40 | DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN |
| 41 | DEV_MCASP8_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP8_MCASP_AHCLKR_PIN |
Clocks for MCASP9 Device¶
Device: J721E_DEV_MCASP9 (ID = 183)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCASP9_VBUSP_CLK | Input clock |
| 1 | DEV_MCASP9_AUX_CLK | Input muxed clock |
| 2 | DEV_MCASP9_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP9_AUX_CLK |
| 3 | DEV_MCASP9_AUX_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MCASP9_AUX_CLK |
| 4 | DEV_MCASP9_AUX_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT0_CLK | Parent input clock option to DEV_MCASP9_AUX_CLK |
| 6 | DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP9_AUX_CLK |
| 7 | DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP9_AUX_CLK |
| 8 | DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP9_AUX_CLK |
| 9 | DEV_MCASP9_AUX_CLK_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP9_AUX_CLK |
| 10 | DEV_MCASP9_MCASP_ACLKX_POUT | Output clock |
| 11 | DEV_MCASP9_MCASP_ACLKX_PIN | Input clock |
| 12 | DEV_MCASP9_MCASP_ACLKR_POUT | Output clock |
| 13 | DEV_MCASP9_MCASP_ACLKR_PIN | Input clock |
| 14 | DEV_MCASP9_MCASP_AHCLKX_POUT | Output clock |
| 15 | DEV_MCASP9_MCASP_AHCLKX_PIN | Input muxed clock |
| 16 | DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN |
| 17 | DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN |
| 18 | DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN |
| 19 | DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN |
| 20 | DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN |
| 21 | DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN |
| 22 | DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN |
| 23 | DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN |
| 24 | DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN |
| 25 | DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN |
| 26 | DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN |
| 27 | DEV_MCASP9_MCASP_AHCLKX_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP9_MCASP_AHCLKX_PIN |
| 28 | DEV_MCASP9_MCASP_AHCLKR_POUT | Output clock |
| 29 | DEV_MCASP9_MCASP_AHCLKR_PIN | Input muxed clock |
| 30 | DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN |
| 31 | DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN |
| 32 | DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT0 | Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN |
| 33 | DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT1 | Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN |
| 34 | DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT2 | Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN |
| 35 | DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_MCASP_AHCLKO_MUX_OUT3 | Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN |
| 36 | DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCLK_OUT | Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN |
| 37 | DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_BOARD_0_MLB0_MLBCP_OUT2 | Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN |
| 38 | DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT | Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN |
| 39 | DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_1 | Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN |
| 40 | DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_2 | Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN |
| 41 | DEV_MCASP9_MCASP_AHCLKR_PIN_PARENT_ATL_MAIN_0_ATL_IO_PORT_ATCLK_OUT_3 | Parent input clock option to DEV_MCASP9_MCASP_AHCLKR_PIN |
Clocks for MCSPI0 Device¶
Device: J721E_DEV_MCSPI0 (ID = 266)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCSPI0_VBUSP_CLK | Input clock |
| 1 | DEV_MCSPI0_CLKSPIREF_CLK | Input clock |
| 2 | DEV_MCSPI0_IO_CLKSPIO_CLK | Output clock |
Clocks for MCSPI1 Device¶
Device: J721E_DEV_MCSPI1 (ID = 267)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCSPI1_VBUSP_CLK | Input clock |
| 1 | DEV_MCSPI1_CLKSPIREF_CLK | Input clock |
| 2 | DEV_MCSPI1_IO_CLKSPIO_CLK | Output clock |
Clocks for MCSPI2 Device¶
Device: J721E_DEV_MCSPI2 (ID = 268)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCSPI2_VBUSP_CLK | Input clock |
| 1 | DEV_MCSPI2_CLKSPIREF_CLK | Input clock |
| 2 | DEV_MCSPI2_IO_CLKSPIO_CLK | Output clock |
Clocks for MCSPI3 Device¶
Device: J721E_DEV_MCSPI3 (ID = 269)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCSPI3_VBUSP_CLK | Input clock |
| 1 | DEV_MCSPI3_CLKSPIREF_CLK | Input clock |
| 2 | DEV_MCSPI3_IO_CLKSPII_CLK | Input muxed clock |
| 3 | DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK | Parent input clock option to DEV_MCSPI3_IO_CLKSPII_CLK |
| 4 | DEV_MCSPI3_IO_CLKSPIO_CLK | Output clock |
Clocks for MCSPI4 Device¶
Device: J721E_DEV_MCSPI4 (ID = 270)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCSPI4_VBUSP_CLK | Input clock |
| 1 | DEV_MCSPI4_CLKSPIREF_CLK | Input clock |
| 2 | DEV_MCSPI4_IO_CLKSPII_CLK | Input clock |
| 3 | DEV_MCSPI4_IO_CLKSPIO_CLK | Output clock |
Clocks for MCSPI5 Device¶
Device: J721E_DEV_MCSPI5 (ID = 271)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCSPI5_VBUSP_CLK | Input clock |
| 1 | DEV_MCSPI5_CLKSPIREF_CLK | Input clock |
| 2 | DEV_MCSPI5_IO_CLKSPIO_CLK | Output clock |
Clocks for MCSPI6 Device¶
Device: J721E_DEV_MCSPI6 (ID = 272)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCSPI6_VBUSP_CLK | Input clock |
| 1 | DEV_MCSPI6_CLKSPIREF_CLK | Input clock |
| 2 | DEV_MCSPI6_IO_CLKSPIO_CLK | Output clock |
Clocks for MCSPI7 Device¶
Device: J721E_DEV_MCSPI7 (ID = 273)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCSPI7_VBUSP_CLK | Input clock |
| 1 | DEV_MCSPI7_CLKSPIREF_CLK | Input clock |
| 2 | DEV_MCSPI7_IO_CLKSPIO_CLK | Output clock |
Clocks for MCU_ADC12_16FFC0 Device¶
Device: J721E_DEV_MCU_ADC12_16FFC0 (ID = 0)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_ADC12_16FFC0_SYS_CLK | Input clock |
| 1 | DEV_MCU_ADC12_16FFC0_ADC_CLK | Input muxed clock |
| 2 | DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCU_ADC12_16FFC0_ADC_CLK |
| 3 | DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK | Parent input clock option to DEV_MCU_ADC12_16FFC0_ADC_CLK |
| 4 | DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK | Parent input clock option to DEV_MCU_ADC12_16FFC0_ADC_CLK |
| 5 | DEV_MCU_ADC12_16FFC0_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCU_ADC12_16FFC0_ADC_CLK |
| 6 | DEV_MCU_ADC12_16FFC0_VBUS_CLK | Input clock |
Clocks for MCU_ADC12_16FFC1 Device¶
Device: J721E_DEV_MCU_ADC12_16FFC1 (ID = 1)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_ADC12_16FFC1_SYS_CLK | Input clock |
| 1 | DEV_MCU_ADC12_16FFC1_ADC_CLK | Input muxed clock |
| 2 | DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCU_ADC12_16FFC1_ADC_CLK |
| 3 | DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT1_CLK | Parent input clock option to DEV_MCU_ADC12_16FFC1_ADC_CLK |
| 4 | DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_HSDIV1_16FFT_MCU_0_HSDIVOUT1_CLK | Parent input clock option to DEV_MCU_ADC12_16FFC1_ADC_CLK |
| 5 | DEV_MCU_ADC12_16FFC1_ADC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCU_ADC12_16FFC1_ADC_CLK |
| 6 | DEV_MCU_ADC12_16FFC1_VBUS_CLK | Input clock |
Clocks for MCU_CPSW0 Device¶
Device: J721E_DEV_MCU_CPSW0 (ID = 18)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_CPSW0_RGMII1_RXC_I | Input clock |
| 1 | DEV_MCU_CPSW0_RGMII_MHZ_250_CLK | Input clock |
| 2 | DEV_MCU_CPSW0_CPTS_RFT_CLK | Input muxed clock |
| 3 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
| 4 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
| 5 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
| 6 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
| 7 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
| 8 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
| 9 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
| 10 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
| 11 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
| 12 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
| 13 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
| 14 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
| 15 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
| 16 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
| 17 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
| 18 | DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK2 | Parent input clock option to DEV_MCU_CPSW0_CPTS_RFT_CLK |
| 19 | DEV_MCU_CPSW0_GMII_RFT_CLK | Input clock |
| 20 | DEV_MCU_CPSW0_RMII_MHZ_50_CLK | Input clock |
| 21 | DEV_MCU_CPSW0_RGMII_MHZ_50_CLK | Input clock |
| 22 | DEV_MCU_CPSW0_CPPI_CLK_CLK | Input clock |
| 23 | DEV_MCU_CPSW0_RGMII_MHZ_5_CLK | Input clock |
| 24 | DEV_MCU_CPSW0_GMII1_MR_CLK | Input clock |
| 25 | DEV_MCU_CPSW0_GMII1_MT_CLK | Input clock |
| 26 | DEV_MCU_CPSW0_RGMII1_TXC_I | Input clock |
| 27 | DEV_MCU_CPSW0_RGMII1_TXC_O | Output clock |
| 28 | DEV_MCU_CPSW0_CPTS_GENF0 | Output clock |
| 29 | DEV_MCU_CPSW0_MDIO_MDCLK_O | Output clock |
Clocks for MCU_CPT2_AGGR0 Device¶
Device: J721E_DEV_MCU_CPT2_AGGR0 (ID = 24)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_CPT2_AGGR0_VCLK_CLK | Input clock |
Clocks for MCU_DCC0 Device¶
Device: J721E_DEV_MCU_DCC0 (ID = 44)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_DCC0_DCC_INPUT10_CLK | Input clock |
| 1 | DEV_MCU_DCC0_DCC_INPUT01_CLK | Input clock |
| 2 | DEV_MCU_DCC0_DCC_CLKSRC2_CLK | Input clock |
| 3 | DEV_MCU_DCC0_DCC_CLKSRC7_CLK | Input clock |
| 4 | DEV_MCU_DCC0_DCC_CLKSRC0_CLK | Input clock |
| 5 | DEV_MCU_DCC0_VBUS_CLK | Input clock |
| 6 | DEV_MCU_DCC0_DCC_CLKSRC4_CLK | Input clock |
| 7 | DEV_MCU_DCC0_DCC_CLKSRC1_CLK | Input clock |
| 8 | DEV_MCU_DCC0_DCC_CLKSRC3_CLK | Input clock |
| 9 | DEV_MCU_DCC0_DCC_INPUT00_CLK | Input clock |
| 10 | DEV_MCU_DCC0_DCC_CLKSRC5_CLK | Input clock |
| 11 | DEV_MCU_DCC0_DCC_CLKSRC6_CLK | Input clock |
| 12 | DEV_MCU_DCC0_DCC_INPUT02_CLK | Input clock |
Clocks for MCU_DCC1 Device¶
Device: J721E_DEV_MCU_DCC1 (ID = 45)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_DCC1_DCC_INPUT10_CLK | Input clock |
| 1 | DEV_MCU_DCC1_DCC_INPUT01_CLK | Input clock |
| 2 | DEV_MCU_DCC1_DCC_CLKSRC2_CLK | Input clock |
| 3 | DEV_MCU_DCC1_DCC_CLKSRC7_CLK | Input clock |
| 4 | DEV_MCU_DCC1_DCC_CLKSRC0_CLK | Input clock |
| 5 | DEV_MCU_DCC1_VBUS_CLK | Input clock |
| 6 | DEV_MCU_DCC1_DCC_CLKSRC4_CLK | Input clock |
| 7 | DEV_MCU_DCC1_DCC_CLKSRC1_CLK | Input clock |
| 8 | DEV_MCU_DCC1_DCC_CLKSRC3_CLK | Input clock |
| 9 | DEV_MCU_DCC1_DCC_INPUT00_CLK | Input clock |
| 10 | DEV_MCU_DCC1_DCC_CLKSRC5_CLK | Input clock |
| 11 | DEV_MCU_DCC1_DCC_CLKSRC6_CLK | Input clock |
| 12 | DEV_MCU_DCC1_DCC_INPUT02_CLK | Input clock |
Clocks for MCU_DCC2 Device¶
Device: J721E_DEV_MCU_DCC2 (ID = 46)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_DCC2_DCC_INPUT10_CLK | Input clock |
| 1 | DEV_MCU_DCC2_DCC_INPUT01_CLK | Input clock |
| 2 | DEV_MCU_DCC2_DCC_CLKSRC7_CLK | Input clock |
| 3 | DEV_MCU_DCC2_DCC_CLKSRC0_CLK | Input clock |
| 4 | DEV_MCU_DCC2_VBUS_CLK | Input clock |
| 5 | DEV_MCU_DCC2_DCC_CLKSRC4_CLK | Input clock |
| 6 | DEV_MCU_DCC2_DCC_CLKSRC1_CLK | Input clock |
| 7 | DEV_MCU_DCC2_DCC_CLKSRC3_CLK | Input clock |
| 8 | DEV_MCU_DCC2_DCC_INPUT00_CLK | Input clock |
| 9 | DEV_MCU_DCC2_DCC_CLKSRC6_CLK | Input clock |
| 10 | DEV_MCU_DCC2_DCC_INPUT02_CLK | Input clock |
Clocks for MCU_ESM0 Device¶
Device: J721E_DEV_MCU_ESM0 (ID = 98)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_ESM0_CLK | Input clock |
Clocks for MCU_FSS0 Device¶
This device has no defined clocks.
Clocks for MCU_FSS0_FSAS_0 Device¶
Device: J721E_DEV_MCU_FSS0_FSAS_0 (ID = 101)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_FSS0_FSAS_0_GCLK | Input clock |
Clocks for MCU_FSS0_HYPERBUS1P0_0 Device¶
Device: J721E_DEV_MCU_FSS0_HYPERBUS1P0_0 (ID = 102)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_INV_CLK | Input clock |
| 1 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_INV_CLK | Input clock |
| 2 | DEV_MCU_FSS0_HYPERBUS1P0_0_CBA_CLK | Input clock |
| 3 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX2_CLK | Input clock |
| 4 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_CLKX1_CLK | Input clock |
| 5 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_N | Output clock |
| 6 | DEV_MCU_FSS0_HYPERBUS1P0_0_HPB_OUT_CLK_P | Output clock |
Clocks for MCU_FSS0_OSPI_0 Device¶
Device: J721E_DEV_MCU_FSS0_OSPI_0 (ID = 103)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK | Input muxed clock |
| 1 | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK | Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK |
| 2 | DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK | Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK |
| 3 | DEV_MCU_FSS0_OSPI_0_OSPI_HCLK_CLK | Input clock |
| 4 | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK | Input muxed clock |
| 5 | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI0_DQS_OUT | Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK |
| 6 | DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_0_OSPI_OCLK_CLK | Parent input clock option to DEV_MCU_FSS0_OSPI_0_OSPI_ICLK_CLK |
| 7 | DEV_MCU_FSS0_OSPI_0_OSPI_PCLK_CLK | Input clock |
| 8 | DEV_MCU_FSS0_OSPI_0_OSPI_DQS_CLK | Input clock |
| 9 | DEV_MCU_FSS0_OSPI_0_OSPI_OCLK_CLK | Output clock |
Clocks for MCU_FSS0_OSPI_1 Device¶
Device: J721E_DEV_MCU_FSS0_OSPI_1 (ID = 104)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK | Input muxed clock |
| 1 | DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK | Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK |
| 2 | DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT4_CLK | Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK |
| 3 | DEV_MCU_FSS0_OSPI_1_OSPI_HCLK_CLK | Input clock |
| 4 | DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK | Input muxed clock |
| 5 | DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_BOARD_0_MCU_OSPI1_DQS_OUT | Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK |
| 6 | DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK_PARENT_FSS_MCU_0_OSPI_1_OSPI_OCLK_CLK | Parent input clock option to DEV_MCU_FSS0_OSPI_1_OSPI_ICLK_CLK |
| 7 | DEV_MCU_FSS0_OSPI_1_OSPI_PCLK_CLK | Input clock |
| 8 | DEV_MCU_FSS0_OSPI_1_OSPI_DQS_CLK | Input clock |
| 9 | DEV_MCU_FSS0_OSPI_1_OSPI_OCLK_CLK | Output clock |
Clocks for MCU_I2C0 Device¶
Device: J721E_DEV_MCU_I2C0 (ID = 194)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_I2C0_PISYS_CLK | Input clock |
| 1 | DEV_MCU_I2C0_PISCL | Input clock |
| 2 | DEV_MCU_I2C0_CLK | Input clock |
| 3 | DEV_MCU_I2C0_PORSCL | Output clock |
Clocks for MCU_I2C1 Device¶
Device: J721E_DEV_MCU_I2C1 (ID = 195)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_I2C1_PISYS_CLK | Input clock |
| 1 | DEV_MCU_I2C1_PISCL | Input clock |
| 2 | DEV_MCU_I2C1_CLK | Input clock |
| 3 | DEV_MCU_I2C1_PORSCL | Output clock |
Clocks for MCU_I3C0 Device¶
Device: J721E_DEV_MCU_I3C0 (ID = 117)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_I3C0_I3C_PCLK_CLK | Input clock |
| 1 | DEV_MCU_I3C0_I3C_SCL_DI | Input clock |
| 2 | DEV_MCU_I3C0_I3C_SCLK_CLK | Input clock |
| 3 | DEV_MCU_I3C0_I3C_SCL_DO | Output clock |
Clocks for MCU_I3C1 Device¶
Device: J721E_DEV_MCU_I3C1 (ID = 118)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_I3C1_I3C_PCLK_CLK | Input clock |
| 1 | DEV_MCU_I3C1_I3C_SCL_DI | Input clock |
| 2 | DEV_MCU_I3C1_I3C_SCLK_CLK | Input clock |
| 3 | DEV_MCU_I3C1_I3C_SCL_DO | Output clock |
Clocks for MCU_MCAN0 Device¶
Device: J721E_DEV_MCU_MCAN0 (ID = 172)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_MCAN0_MCANSS_HCLK_CLK | Input clock |
| 1 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK | Input muxed clock |
| 2 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK | Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK |
| 3 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK |
| 4 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK | Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK |
| 5 | DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCU_MCAN0_MCANSS_CCLK_CLK |
Clocks for MCU_MCAN1 Device¶
Device: J721E_DEV_MCU_MCAN1 (ID = 173)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_MCAN1_MCANSS_HCLK_CLK | Input clock |
| 1 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK | Input muxed clock |
| 2 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK | Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK |
| 3 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK |
| 4 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK | Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK |
| 5 | DEV_MCU_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCU_MCAN1_MCANSS_CCLK_CLK |
Clocks for MCU_MCSPI0 Device¶
Device: J721E_DEV_MCU_MCSPI0 (ID = 274)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_MCSPI0_VBUSP_CLK | Input clock |
| 1 | DEV_MCU_MCSPI0_CLKSPIREF_CLK | Input clock |
| 2 | DEV_MCU_MCSPI0_IO_CLKSPIO_CLK | Output clock |
Clocks for MCU_MCSPI1 Device¶
Device: J721E_DEV_MCU_MCSPI1 (ID = 275)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_MCSPI1_VBUSP_CLK | Input clock |
| 1 | DEV_MCU_MCSPI1_CLKSPIREF_CLK | Input clock |
| 2 | DEV_MCU_MCSPI1_IO_CLKSPII_CLK | Input muxed clock |
| 3 | DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK | Parent input clock option to DEV_MCU_MCSPI1_IO_CLKSPII_CLK |
| 4 | DEV_MCU_MCSPI1_IO_CLKSPIO_CLK | Output clock |
Clocks for MCU_MCSPI2 Device¶
Device: J721E_DEV_MCU_MCSPI2 (ID = 276)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_MCSPI2_VBUSP_CLK | Input clock |
| 1 | DEV_MCU_MCSPI2_CLKSPIREF_CLK | Input clock |
| 2 | DEV_MCU_MCSPI2_IO_CLKSPII_CLK | Input clock |
| 3 | DEV_MCU_MCSPI2_IO_CLKSPIO_CLK | Output clock |
Clocks for MCU_PBIST0 Device¶
This device has no defined clocks.
Clocks for MCU_PBIST1 Device¶
This device has no defined clocks.
Clocks for MCU_R5FSS0 Device¶
This device has no defined clocks.
Clocks for MCU_R5FSS0_CORE0 Device¶
Device: J721E_DEV_MCU_R5FSS0_CORE0 (ID = 250)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_R5FSS0_CORE0_CPU_CLK | Input muxed clock |
| 1 | DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK | Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK |
| 2 | DEV_MCU_R5FSS0_CORE0_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3 | Parent input clock option to DEV_MCU_R5FSS0_CORE0_CPU_CLK |
| 3 | DEV_MCU_R5FSS0_CORE0_INTERFACE_CLK | Input clock |
| 4 | DEV_MCU_R5FSS0_CORE0_INTERFACE_PHASE | Input clock |
Clocks for MCU_R5FSS0_CORE1 Device¶
Device: J721E_DEV_MCU_R5FSS0_CORE1 (ID = 251)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_R5FSS0_CORE1_CPU_CLK | Input muxed clock |
| 1 | DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK | Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK |
| 2 | DEV_MCU_R5FSS0_CORE1_CPU_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK3 | Parent input clock option to DEV_MCU_R5FSS0_CORE1_CPU_CLK |
| 3 | DEV_MCU_R5FSS0_CORE1_INTERFACE_CLK | Input clock |
| 4 | DEV_MCU_R5FSS0_CORE1_INTERFACE_PHASE | Input clock |
Clocks for MCU_RTI0 Device¶
Device: J721E_DEV_MCU_RTI0 (ID = 262)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_RTI0_VBUSP_CLK | Input clock |
| 1 | DEV_MCU_RTI0_RTI_CLK | Input muxed clock |
| 2 | DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCU_RTI0_RTI_CLK |
| 3 | DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_MCU_RTI0_RTI_CLK |
| 4 | DEV_MCU_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_MCU_RTI0_RTI_CLK |
| 5 | DEV_MCU_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | Parent input clock option to DEV_MCU_RTI0_RTI_CLK |
Clocks for MCU_RTI1 Device¶
Device: J721E_DEV_MCU_RTI1 (ID = 263)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_RTI1_VBUSP_CLK | Input clock |
| 1 | DEV_MCU_RTI1_RTI_CLK | Input muxed clock |
| 2 | DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCU_RTI1_RTI_CLK |
| 3 | DEV_MCU_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_MCU_RTI1_RTI_CLK |
| 4 | DEV_MCU_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_MCU_RTI1_RTI_CLK |
| 5 | DEV_MCU_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | Parent input clock option to DEV_MCU_RTI1_RTI_CLK |
Clocks for MCU_SA2_UL0 Device¶
Device: J721E_DEV_MCU_SA2_UL0 (ID = 265)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_SA2_UL0_X2_CLK | Input clock |
| 1 | DEV_MCU_SA2_UL0_PKA_IN_CLK | Input clock |
| 2 | DEV_MCU_SA2_UL0_X1_CLK | Input clock |
Clocks for MCU_TIMER0 Device¶
Device: J721E_DEV_MCU_TIMER0 (ID = 35)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_TIMER0_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_MCU_TIMER0_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK |
| 3 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK |
| 4 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK |
| 5 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK |
| 6 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK |
| 7 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK |
| 8 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK |
| 9 | DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | Parent input clock option to DEV_MCU_TIMER0_TIMER_TCLK_CLK |
| 10 | DEV_MCU_TIMER0_TIMER_PWM | Output clock |
Clocks for MCU_TIMER1 Device¶
Device: J721E_DEV_MCU_TIMER1 (ID = 71)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_TIMER1_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_MCU_TIMER1_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT1 | Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK |
| 3 | DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_0_TIMER_PWM | Parent input clock option to DEV_MCU_TIMER1_TIMER_TCLK_CLK |
Clocks for MCU_TIMER1_CLKSEL_VD Device¶
Device: J721E_DEV_MCU_TIMER1_CLKSEL_VD (ID = 322)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_TIMER1_CLKSEL_VD_CLK | Input muxed clock |
| 1 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK |
| 2 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK |
| 3 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK |
| 4 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK |
| 5 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK |
| 6 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK |
| 7 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK |
| 8 | DEV_MCU_TIMER1_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | Parent input clock option to DEV_MCU_TIMER1_CLKSEL_VD_CLK |
Clocks for MCU_TIMER2 Device¶
Device: J721E_DEV_MCU_TIMER2 (ID = 72)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_TIMER2_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_MCU_TIMER2_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK |
| 3 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK |
| 4 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK |
| 5 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK |
| 6 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK |
| 7 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK |
| 8 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK |
| 9 | DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | Parent input clock option to DEV_MCU_TIMER2_TIMER_TCLK_CLK |
| 10 | DEV_MCU_TIMER2_TIMER_PWM | Output clock |
Clocks for MCU_TIMER3 Device¶
Device: J721E_DEV_MCU_TIMER3 (ID = 73)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_TIMER3_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_MCU_TIMER3_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT3 | Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK |
| 3 | DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_2_TIMER_PWM | Parent input clock option to DEV_MCU_TIMER3_TIMER_TCLK_CLK |
Clocks for MCU_TIMER3_CLKSEL_VD Device¶
Device: J721E_DEV_MCU_TIMER3_CLKSEL_VD (ID = 323)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_TIMER3_CLKSEL_VD_CLK | Input muxed clock |
| 1 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK |
| 2 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK |
| 3 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK |
| 4 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK |
| 5 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK |
| 6 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK |
| 7 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK |
| 8 | DEV_MCU_TIMER3_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | Parent input clock option to DEV_MCU_TIMER3_CLKSEL_VD_CLK |
Clocks for MCU_TIMER4 Device¶
Device: J721E_DEV_MCU_TIMER4 (ID = 74)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_TIMER4_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_MCU_TIMER4_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK |
| 3 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK |
| 4 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK |
| 5 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK |
| 6 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK |
| 7 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK |
| 8 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK |
| 9 | DEV_MCU_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | Parent input clock option to DEV_MCU_TIMER4_TIMER_TCLK_CLK |
| 10 | DEV_MCU_TIMER4_TIMER_PWM | Output clock |
Clocks for MCU_TIMER5 Device¶
Device: J721E_DEV_MCU_TIMER5 (ID = 75)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_TIMER5_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_MCU_TIMER5_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT5 | Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK |
| 3 | DEV_MCU_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_4_TIMER_PWM | Parent input clock option to DEV_MCU_TIMER5_TIMER_TCLK_CLK |
Clocks for MCU_TIMER5_CLKSEL_VD Device¶
Device: J721E_DEV_MCU_TIMER5_CLKSEL_VD (ID = 324)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_TIMER5_CLKSEL_VD_CLK | Input muxed clock |
| 1 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK |
| 2 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK |
| 3 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK |
| 4 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK |
| 5 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK |
| 6 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK |
| 7 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK |
| 8 | DEV_MCU_TIMER5_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | Parent input clock option to DEV_MCU_TIMER5_CLKSEL_VD_CLK |
Clocks for MCU_TIMER6 Device¶
Device: J721E_DEV_MCU_TIMER6 (ID = 76)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_TIMER6_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_MCU_TIMER6_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK |
| 3 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK |
| 4 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK |
| 5 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK |
| 6 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK |
| 7 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK |
| 8 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK |
| 9 | DEV_MCU_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | Parent input clock option to DEV_MCU_TIMER6_TIMER_TCLK_CLK |
| 10 | DEV_MCU_TIMER6_TIMER_PWM | Output clock |
Clocks for MCU_TIMER7 Device¶
Device: J721E_DEV_MCU_TIMER7 (ID = 77)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_TIMER7_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_MCU_TIMER7_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT7 | Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK |
| 3 | DEV_MCU_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_6_TIMER_PWM | Parent input clock option to DEV_MCU_TIMER7_TIMER_TCLK_CLK |
Clocks for MCU_TIMER7_CLKSEL_VD Device¶
Device: J721E_DEV_MCU_TIMER7_CLKSEL_VD (ID = 325)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_TIMER7_CLKSEL_VD_CLK | Input muxed clock |
| 1 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK |
| 2 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK |
| 3 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK |
| 4 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK |
| 5 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK |
| 6 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK |
| 7 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK |
| 8 | DEV_MCU_TIMER7_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | Parent input clock option to DEV_MCU_TIMER7_CLKSEL_VD_CLK |
Clocks for MCU_TIMER8 Device¶
Device: J721E_DEV_MCU_TIMER8 (ID = 78)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_TIMER8_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_MCU_TIMER8_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK |
| 3 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK |
| 4 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK |
| 5 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK |
| 6 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK |
| 7 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK |
| 8 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK |
| 9 | DEV_MCU_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | Parent input clock option to DEV_MCU_TIMER8_TIMER_TCLK_CLK |
| 10 | DEV_MCU_TIMER8_TIMER_PWM | Output clock |
Clocks for MCU_TIMER9 Device¶
Device: J721E_DEV_MCU_TIMER9 (ID = 79)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_TIMER9_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_MCU_TIMER9_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_MCU_TIMER_CLKSEL_OUT9 | Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK |
| 3 | DEV_MCU_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MCU_8_TIMER_PWM | Parent input clock option to DEV_MCU_TIMER9_TIMER_TCLK_CLK |
Clocks for MCU_TIMER9_CLKSEL_VD Device¶
Device: J721E_DEV_MCU_TIMER9_CLKSEL_VD (ID = 326)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_TIMER9_CLKSEL_VD_CLK | Input muxed clock |
| 1 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK |
| 2 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_K3_PLL_CTRL_WRAP_WKUP_0_CHIP_DIV1_CLK_CLK6 | Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK |
| 3 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK |
| 4 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK |
| 5 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK |
| 6 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK |
| 7 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_CPSW_2GUSS_MCU_0_CPTS_GENF0 | Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK |
| 8 | DEV_MCU_TIMER9_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | Parent input clock option to DEV_MCU_TIMER9_CLKSEL_VD_CLK |
Clocks for MCU_UART0 Device¶
Device: J721E_DEV_MCU_UART0 (ID = 149)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MCU_UART0_FCLK_CLK | Input muxed clock |
| 1 | DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK | Parent input clock option to DEV_MCU_UART0_FCLK_CLK |
| 2 | DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT5_CLK | Parent input clock option to DEV_MCU_UART0_FCLK_CLK |
| 3 | DEV_MCU_UART0_VBUSP_CLK | Input clock |
Clocks for MLB0 Device¶
Device: J721E_DEV_MLB0 (ID = 186)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MLB0_MLBSS_MLB_CLK | Input clock |
| 1 | DEV_MLB0_MLBSS_SCLK_CLK | Input clock |
| 2 | DEV_MLB0_MLBSS_HCLK_CLK | Input clock |
| 3 | DEV_MLB0_MLBSS_PCLK_CLK | Input clock |
| 4 | DEV_MLB0_MLBSS_AMLB_CLK | Input clock |
Clocks for MMCSD0 Device¶
Device: J721E_DEV_MMCSD0 (ID = 91)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MMCSD0_EMMCSS_VBUS_CLK | Input clock |
| 1 | DEV_MMCSD0_EMMCSS_XIN_CLK | Input muxed clock |
| 2 | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK | Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK |
| 3 | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK | Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK |
| 4 | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK |
| 5 | DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK | Parent input clock option to DEV_MMCSD0_EMMCSS_XIN_CLK |
| 6 | DEV_MMCSD0_EMMCSS_IO_CLK | Output clock |
Clocks for MMCSD1 Device¶
Device: J721E_DEV_MMCSD1 (ID = 92)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MMCSD1_EMMCSDSS_XIN_CLK | Input muxed clock |
| 1 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK | Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK |
| 2 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK | Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK |
| 3 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK |
| 4 | DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK | Parent input clock option to DEV_MMCSD1_EMMCSDSS_XIN_CLK |
| 5 | DEV_MMCSD1_EMMCSDSS_VBUS_CLK | Input clock |
| 6 | DEV_MMCSD1_EMMCSDSS_IO_CLK_I | Input clock |
| 7 | DEV_MMCSD1_EMMCSDSS_IO_CLK_O | Output clock |
Clocks for MMCSD2 Device¶
Device: J721E_DEV_MMCSD2 (ID = 93)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_MMCSD2_EMMCSDSS_XIN_CLK | Input muxed clock |
| 1 | DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK | Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK |
| 2 | DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK | Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK |
| 3 | DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK | Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK |
| 4 | DEV_MMCSD2_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK | Parent input clock option to DEV_MMCSD2_EMMCSDSS_XIN_CLK |
| 5 | DEV_MMCSD2_EMMCSDSS_VBUS_CLK | Input clock |
| 6 | DEV_MMCSD2_EMMCSDSS_IO_CLK_I | Input clock |
| 7 | DEV_MMCSD2_EMMCSDSS_IO_CLK_O | Output clock |
Clocks for PBIST0 Device¶
This device has no defined clocks.
Clocks for PBIST1 Device¶
This device has no defined clocks.
Clocks for PBIST10 Device¶
This device has no defined clocks.
Clocks for PBIST2 Device¶
This device has no defined clocks.
Clocks for PBIST3 Device¶
This device has no defined clocks.
Clocks for PBIST4 Device¶
This device has no defined clocks.
Clocks for PBIST5 Device¶
This device has no defined clocks.
Clocks for PBIST6 Device¶
This device has no defined clocks.
Clocks for PBIST7 Device¶
This device has no defined clocks.
Clocks for PBIST9 Device¶
This device has no defined clocks.
Clocks for PCIE0 Device¶
Device: J721E_DEV_PCIE0 (ID = 239)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_PCIE0_PCIE_LANE1_TXMCLK | Input clock |
| 1 | DEV_PCIE0_PCIE_CBA_CLK | Input clock |
| 2 | DEV_PCIE0_PCIE_LANE1_RXCLK | Input clock |
| 3 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK | Input muxed clock |
| 4 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
| 5 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
| 6 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
| 7 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
| 8 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
| 9 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
| 10 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
| 11 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
| 12 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
| 13 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
| 14 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
| 15 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
| 16 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0 | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
| 17 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0 | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
| 18 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
| 19 | DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | Parent input clock option to DEV_PCIE0_PCIE_CPTS_RCLK_CLK |
| 20 | DEV_PCIE0_PCIE_LANE1_TXFCLK | Input clock |
| 21 | DEV_PCIE0_PCIE_LANE1_REFCLK | Input clock |
| 22 | DEV_PCIE0_PCIE_LANE0_REFCLK | Input clock |
| 23 | DEV_PCIE0_PCIE_LANE0_TXMCLK | Input clock |
| 24 | DEV_PCIE0_PCIE_LANE0_TXFCLK | Input clock |
| 25 | DEV_PCIE0_PCIE_PM_CLK | Input clock |
| 26 | DEV_PCIE0_PCIE_LANE0_RXFCLK | Input clock |
| 27 | DEV_PCIE0_PCIE_LANE1_RXFCLK | Input clock |
| 28 | DEV_PCIE0_PCIE_LANE0_RXCLK | Input clock |
| 29 | DEV_PCIE0_PCIE_LANE1_TXCLK | Output clock |
| 30 | DEV_PCIE0_PCIE_LANE0_TXCLK | Output clock |
Clocks for PCIE1 Device¶
Device: J721E_DEV_PCIE1 (ID = 240)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_PCIE1_PCIE_LANE1_TXMCLK | Input clock |
| 1 | DEV_PCIE1_PCIE_CBA_CLK | Input clock |
| 2 | DEV_PCIE1_PCIE_LANE1_RXCLK | Input clock |
| 3 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK | Input muxed clock |
| 4 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
| 5 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
| 6 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
| 7 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
| 8 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
| 9 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
| 10 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
| 11 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
| 12 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
| 13 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
| 14 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
| 15 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
| 16 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0 | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
| 17 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0 | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
| 18 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
| 19 | DEV_PCIE1_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | Parent input clock option to DEV_PCIE1_PCIE_CPTS_RCLK_CLK |
| 20 | DEV_PCIE1_PCIE_LANE1_TXFCLK | Input clock |
| 21 | DEV_PCIE1_PCIE_LANE1_REFCLK | Input clock |
| 22 | DEV_PCIE1_PCIE_LANE0_REFCLK | Input clock |
| 23 | DEV_PCIE1_PCIE_LANE0_TXMCLK | Input clock |
| 24 | DEV_PCIE1_PCIE_LANE0_TXFCLK | Input clock |
| 25 | DEV_PCIE1_PCIE_PM_CLK | Input clock |
| 26 | DEV_PCIE1_PCIE_LANE0_RXFCLK | Input clock |
| 27 | DEV_PCIE1_PCIE_LANE1_RXFCLK | Input clock |
| 28 | DEV_PCIE1_PCIE_LANE0_RXCLK | Input clock |
| 29 | DEV_PCIE1_PCIE_LANE1_TXCLK | Output clock |
| 30 | DEV_PCIE1_PCIE_LANE0_TXCLK | Output clock |
Clocks for PCIE2 Device¶
Device: J721E_DEV_PCIE2 (ID = 241)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_PCIE2_PCIE_LANE1_TXMCLK | Input clock |
| 1 | DEV_PCIE2_PCIE_CBA_CLK | Input clock |
| 2 | DEV_PCIE2_PCIE_LANE1_RXCLK | Input clock |
| 3 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK | Input muxed clock |
| 4 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
| 5 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
| 6 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
| 7 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
| 8 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
| 9 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
| 10 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
| 11 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
| 12 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
| 13 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
| 14 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
| 15 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
| 16 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0 | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
| 17 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0 | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
| 18 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
| 19 | DEV_PCIE2_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | Parent input clock option to DEV_PCIE2_PCIE_CPTS_RCLK_CLK |
| 20 | DEV_PCIE2_PCIE_LANE1_TXFCLK | Input clock |
| 21 | DEV_PCIE2_PCIE_LANE1_REFCLK | Input clock |
| 22 | DEV_PCIE2_PCIE_LANE0_REFCLK | Input clock |
| 23 | DEV_PCIE2_PCIE_LANE0_TXMCLK | Input clock |
| 24 | DEV_PCIE2_PCIE_LANE0_TXFCLK | Input clock |
| 25 | DEV_PCIE2_PCIE_PM_CLK | Input clock |
| 26 | DEV_PCIE2_PCIE_LANE0_RXFCLK | Input clock |
| 27 | DEV_PCIE2_PCIE_LANE1_RXFCLK | Input clock |
| 28 | DEV_PCIE2_PCIE_LANE0_RXCLK | Input clock |
| 29 | DEV_PCIE2_PCIE_LANE1_TXCLK | Output clock |
| 30 | DEV_PCIE2_PCIE_LANE0_TXCLK | Output clock |
Clocks for PCIE3 Device¶
Device: J721E_DEV_PCIE3 (ID = 242)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_PCIE3_PCIE_LANE1_TXMCLK | Input clock |
| 1 | DEV_PCIE3_PCIE_CBA_CLK | Input clock |
| 2 | DEV_PCIE3_PCIE_LANE1_RXCLK | Input clock |
| 3 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK | Input muxed clock |
| 4 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
| 5 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
| 6 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
| 7 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
| 8 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
| 9 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
| 10 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
| 11 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
| 12 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
| 13 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
| 14 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
| 15 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
| 16 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK_DUP0 | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
| 17 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK_DUP0 | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
| 18 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
| 19 | DEV_PCIE3_PCIE_CPTS_RCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | Parent input clock option to DEV_PCIE3_PCIE_CPTS_RCLK_CLK |
| 20 | DEV_PCIE3_PCIE_LANE1_TXFCLK | Input clock |
| 21 | DEV_PCIE3_PCIE_LANE1_REFCLK | Input clock |
| 22 | DEV_PCIE3_PCIE_LANE0_REFCLK | Input clock |
| 23 | DEV_PCIE3_PCIE_LANE0_TXMCLK | Input clock |
| 24 | DEV_PCIE3_PCIE_LANE0_TXFCLK | Input clock |
| 25 | DEV_PCIE3_PCIE_PM_CLK | Input clock |
| 26 | DEV_PCIE3_PCIE_LANE0_RXFCLK | Input clock |
| 27 | DEV_PCIE3_PCIE_LANE1_RXFCLK | Input clock |
| 28 | DEV_PCIE3_PCIE_LANE0_RXCLK | Input clock |
| 29 | DEV_PCIE3_PCIE_LANE1_TXCLK | Output clock |
| 30 | DEV_PCIE3_PCIE_LANE0_TXCLK | Output clock |
Clocks for PRU_ICSSG0 Device¶
Device: J721E_DEV_PRU_ICSSG0 (ID = 119)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_PRU_ICSSG0_PR1_RGMII0_RXC_I | Input clock |
| 1 | DEV_PRU_ICSSG0_VCLK_CLK | Input clock |
| 2 | DEV_PRU_ICSSG0_PR1_RGMII1_TXC_I | Input clock |
| 3 | DEV_PRU_ICSSG0_IEP_CLK | Input muxed clock |
| 4 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK |
| 5 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK |
| 6 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK |
| 7 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK |
| 8 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK |
| 9 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK |
| 10 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK |
| 11 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK |
| 12 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK |
| 13 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK |
| 14 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK |
| 15 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK |
| 16 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK |
| 17 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK |
| 18 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK |
| 19 | DEV_PRU_ICSSG0_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | Parent input clock option to DEV_PRU_ICSSG0_IEP_CLK |
| 20 | DEV_PRU_ICSSG0_RGMII_MHZ_5_CLK | Input clock |
| 21 | DEV_PRU_ICSSG0_PR1_RGMII1_RXC_I | Input clock |
| 22 | DEV_PRU_ICSSG0_UCLK_CLK | Input clock |
| 23 | DEV_PRU_ICSSG0_PR1_RGMII0_TXC_I | Input clock |
| 24 | DEV_PRU_ICSSG0_CORE_CLK | Input muxed clock |
| 25 | DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK | Parent input clock option to DEV_PRU_ICSSG0_CORE_CLK |
| 26 | DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | Parent input clock option to DEV_PRU_ICSSG0_CORE_CLK |
| 27 | DEV_PRU_ICSSG0_RGMII_MHZ_250_CLK | Input clock |
| 28 | DEV_PRU_ICSSG0_RGMII_MHZ_50_CLK | Input clock |
| 29 | DEV_PRU_ICSSG0_PR1_RGMII1_TXC_O | Output clock |
| 30 | DEV_PRU_ICSSG0_PR1_MDIO_MDCLK_O | Output clock |
| 31 | DEV_PRU_ICSSG0_PR1_RGMII0_TXC_O | Output clock |
Clocks for PRU_ICSSG1 Device¶
Device: J721E_DEV_PRU_ICSSG1 (ID = 120)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_PRU_ICSSG1_SERDES0_RXCLK | Input muxed clock |
| 1 | DEV_PRU_ICSSG1_SERDES0_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_RXCLK | Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXCLK |
| 2 | DEV_PRU_ICSSG1_SERDES0_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_RXCLK | Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXCLK |
| 3 | DEV_PRU_ICSSG1_PR1_RGMII0_RXC_I | Input clock |
| 4 | DEV_PRU_ICSSG1_VCLK_CLK | Input clock |
| 5 | DEV_PRU_ICSSG1_PR1_RGMII1_TXC_I | Input clock |
| 6 | DEV_PRU_ICSSG1_SERDES0_RXFCLK | Input muxed clock |
| 7 | DEV_PRU_ICSSG1_SERDES0_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_RXFCLK | Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXFCLK |
| 8 | DEV_PRU_ICSSG1_SERDES0_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_RXFCLK | Parent input clock option to DEV_PRU_ICSSG1_SERDES0_RXFCLK |
| 9 | DEV_PRU_ICSSG1_IEP_CLK | Input muxed clock |
| 10 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK |
| 11 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_POSTDIV3_16FFT_MAIN_0_HSDIVOUT6_CLK | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK |
| 12 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK |
| 13 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK |
| 14 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK |
| 15 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK |
| 16 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN0_TXMCLK | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK |
| 17 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_0_IP2_LN1_TXMCLK | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK |
| 18 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN0_TXMCLK | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK |
| 19 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_1_IP2_LN1_TXMCLK | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK |
| 20 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN0_TXMCLK | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK |
| 21 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_2_IP2_LN1_TXMCLK | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK |
| 22 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN0_TXMCLK | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK |
| 23 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B4M4CS_MAIN_3_IP2_LN1_TXMCLK | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK |
| 24 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK |
| 25 | DEV_PRU_ICSSG1_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | Parent input clock option to DEV_PRU_ICSSG1_IEP_CLK |
| 26 | DEV_PRU_ICSSG1_RGMII_MHZ_5_CLK | Input clock |
| 27 | DEV_PRU_ICSSG1_SERDES0_TXMCLK | Input muxed clock |
| 28 | DEV_PRU_ICSSG1_SERDES0_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_TXMCLK | Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXMCLK |
| 29 | DEV_PRU_ICSSG1_SERDES0_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_TXMCLK | Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXMCLK |
| 30 | DEV_PRU_ICSSG1_SERDES0_REFCLK | Input muxed clock |
| 31 | DEV_PRU_ICSSG1_SERDES0_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_REFCLK | Parent input clock option to DEV_PRU_ICSSG1_SERDES0_REFCLK |
| 32 | DEV_PRU_ICSSG1_SERDES0_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_REFCLK | Parent input clock option to DEV_PRU_ICSSG1_SERDES0_REFCLK |
| 33 | DEV_PRU_ICSSG1_SERDES1_RXFCLK | Input muxed clock |
| 34 | DEV_PRU_ICSSG1_SERDES1_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_RXFCLK | Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXFCLK |
| 35 | DEV_PRU_ICSSG1_SERDES1_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_RXFCLK | Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXFCLK |
| 36 | DEV_PRU_ICSSG1_PR1_RGMII1_RXC_I | Input clock |
| 37 | DEV_PRU_ICSSG1_SERDES1_RXCLK | Input muxed clock |
| 38 | DEV_PRU_ICSSG1_SERDES1_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_RXCLK | Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXCLK |
| 39 | DEV_PRU_ICSSG1_SERDES1_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_RXCLK | Parent input clock option to DEV_PRU_ICSSG1_SERDES1_RXCLK |
| 40 | DEV_PRU_ICSSG1_SERDES1_TXFCLK | Input muxed clock |
| 41 | DEV_PRU_ICSSG1_SERDES1_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_TXFCLK | Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXFCLK |
| 42 | DEV_PRU_ICSSG1_SERDES1_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_TXFCLK | Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXFCLK |
| 43 | DEV_PRU_ICSSG1_SERDES1_TXMCLK | Input muxed clock |
| 44 | DEV_PRU_ICSSG1_SERDES1_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_TXMCLK | Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXMCLK |
| 45 | DEV_PRU_ICSSG1_SERDES1_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_TXMCLK | Parent input clock option to DEV_PRU_ICSSG1_SERDES1_TXMCLK |
| 46 | DEV_PRU_ICSSG1_SERDES0_TXFCLK | Input muxed clock |
| 47 | DEV_PRU_ICSSG1_SERDES0_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN0_TXFCLK | Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXFCLK |
| 48 | DEV_PRU_ICSSG1_SERDES0_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN0_TXFCLK | Parent input clock option to DEV_PRU_ICSSG1_SERDES0_TXFCLK |
| 49 | DEV_PRU_ICSSG1_UCLK_CLK | Input clock |
| 50 | DEV_PRU_ICSSG1_PR1_RGMII0_TXC_I | Input clock |
| 51 | DEV_PRU_ICSSG1_SERDES1_REFCLK | Input muxed clock |
| 52 | DEV_PRU_ICSSG1_SERDES1_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP4_LN1_REFCLK | Parent input clock option to DEV_PRU_ICSSG1_SERDES1_REFCLK |
| 53 | DEV_PRU_ICSSG1_SERDES1_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP4_LN1_REFCLK | Parent input clock option to DEV_PRU_ICSSG1_SERDES1_REFCLK |
| 54 | DEV_PRU_ICSSG1_CORE_CLK | Input muxed clock |
| 55 | DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK | Parent input clock option to DEV_PRU_ICSSG1_CORE_CLK |
| 56 | DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT1_CLK | Parent input clock option to DEV_PRU_ICSSG1_CORE_CLK |
| 57 | DEV_PRU_ICSSG1_RGMII_MHZ_250_CLK | Input clock |
| 58 | DEV_PRU_ICSSG1_RGMII_MHZ_50_CLK | Input clock |
| 59 | DEV_PRU_ICSSG1_PR1_RGMII1_TXC_O | Output clock |
| 60 | DEV_PRU_ICSSG1_PR1_MDIO_MDCLK_O | Output clock |
| 61 | DEV_PRU_ICSSG1_PR1_RGMII0_TXC_O | Output clock |
| 62 | DEV_PRU_ICSSG1_SERDES0_TXCLK | Output clock |
| 63 | DEV_PRU_ICSSG1_SERDES1_TXCLK | Output clock |
Clocks for PSC0 Device¶
Device: J721E_DEV_PSC0 (ID = 133)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_PSC0_SLOW_CLK | Input clock |
| 1 | DEV_PSC0_CLK | Input clock |
Clocks for R5FSS0 Device¶
This device has no defined clocks.
Clocks for R5FSS0_CORE0 Device¶
Device: J721E_DEV_R5FSS0_CORE0 (ID = 245)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_R5FSS0_CORE0_CPU_CLK | Input clock |
| 1 | DEV_R5FSS0_CORE0_INTERFACE_CLK | Input clock |
| 2 | DEV_R5FSS0_CORE0_INTERFACE_PHASE | Input clock |
Clocks for R5FSS0_CORE1 Device¶
Device: J721E_DEV_R5FSS0_CORE1 (ID = 246)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_R5FSS0_CORE1_CPU_CLK | Input clock |
| 1 | DEV_R5FSS0_CORE1_INTERFACE_CLK | Input clock |
| 2 | DEV_R5FSS0_CORE1_INTERFACE_PHASE | Input clock |
Clocks for R5FSS0_INTROUTER0 Device¶
Device: J721E_DEV_R5FSS0_INTROUTER0 (ID = 134)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_R5FSS0_INTROUTER0_INTR_CLK | Input clock |
Clocks for R5FSS1 Device¶
This device has no defined clocks.
Clocks for R5FSS1_CORE0 Device¶
Device: J721E_DEV_R5FSS1_CORE0 (ID = 247)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_R5FSS1_CORE0_CPU_CLK | Input clock |
| 1 | DEV_R5FSS1_CORE0_INTERFACE_CLK | Input clock |
| 2 | DEV_R5FSS1_CORE0_INTERFACE_PHASE | Input clock |
Clocks for R5FSS1_CORE1 Device¶
Device: J721E_DEV_R5FSS1_CORE1 (ID = 248)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_R5FSS1_CORE1_CPU_CLK | Input clock |
| 1 | DEV_R5FSS1_CORE1_INTERFACE_CLK | Input clock |
| 2 | DEV_R5FSS1_CORE1_INTERFACE_PHASE | Input clock |
Clocks for R5FSS1_INTROUTER0 Device¶
Device: J721E_DEV_R5FSS1_INTROUTER0 (ID = 135)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_R5FSS1_INTROUTER0_INTR_CLK | Input clock |
Clocks for RTI0 Device¶
Device: J721E_DEV_RTI0 (ID = 252)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_RTI0_VBUSP_CLK | Input clock |
| 1 | DEV_RTI0_RTI_CLK | Input muxed clock |
| 2 | DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_RTI0_RTI_CLK |
| 3 | DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_RTI0_RTI_CLK |
| 4 | DEV_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_RTI0_RTI_CLK |
| 5 | DEV_RTI0_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | Parent input clock option to DEV_RTI0_RTI_CLK |
| 6 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_RTI0_RTI_CLK |
| 7 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | Parent input clock option to DEV_RTI0_RTI_CLK |
| 8 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | Parent input clock option to DEV_RTI0_RTI_CLK |
| 9 | DEV_RTI0_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | Parent input clock option to DEV_RTI0_RTI_CLK |
Clocks for RTI1 Device¶
Device: J721E_DEV_RTI1 (ID = 253)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_RTI1_VBUSP_CLK | Input clock |
| 1 | DEV_RTI1_RTI_CLK | Input muxed clock |
| 2 | DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_RTI1_RTI_CLK |
| 3 | DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_RTI1_RTI_CLK |
| 4 | DEV_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_RTI1_RTI_CLK |
| 5 | DEV_RTI1_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | Parent input clock option to DEV_RTI1_RTI_CLK |
| 6 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_RTI1_RTI_CLK |
| 7 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | Parent input clock option to DEV_RTI1_RTI_CLK |
| 8 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | Parent input clock option to DEV_RTI1_RTI_CLK |
| 9 | DEV_RTI1_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | Parent input clock option to DEV_RTI1_RTI_CLK |
Clocks for RTI15 Device¶
Device: J721E_DEV_RTI15 (ID = 257)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_RTI15_VBUSP_CLK | Input clock |
| 1 | DEV_RTI15_RTI_CLK | Input muxed clock |
| 2 | DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_RTI15_RTI_CLK |
| 3 | DEV_RTI15_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_RTI15_RTI_CLK |
| 4 | DEV_RTI15_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_RTI15_RTI_CLK |
| 5 | DEV_RTI15_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | Parent input clock option to DEV_RTI15_RTI_CLK |
| 6 | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_RTI15_RTI_CLK |
| 7 | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | Parent input clock option to DEV_RTI15_RTI_CLK |
| 8 | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | Parent input clock option to DEV_RTI15_RTI_CLK |
| 9 | DEV_RTI15_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | Parent input clock option to DEV_RTI15_RTI_CLK |
Clocks for RTI16 Device¶
Device: J721E_DEV_RTI16 (ID = 256)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_RTI16_VBUSP_CLK | Input clock |
| 1 | DEV_RTI16_RTI_CLK | Input muxed clock |
| 2 | DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_RTI16_RTI_CLK |
| 3 | DEV_RTI16_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_RTI16_RTI_CLK |
| 4 | DEV_RTI16_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_RTI16_RTI_CLK |
| 5 | DEV_RTI16_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | Parent input clock option to DEV_RTI16_RTI_CLK |
| 6 | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_RTI16_RTI_CLK |
| 7 | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | Parent input clock option to DEV_RTI16_RTI_CLK |
| 8 | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | Parent input clock option to DEV_RTI16_RTI_CLK |
| 9 | DEV_RTI16_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | Parent input clock option to DEV_RTI16_RTI_CLK |
Clocks for RTI24 Device¶
Device: J721E_DEV_RTI24 (ID = 254)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_RTI24_VBUSP_CLK | Input clock |
| 1 | DEV_RTI24_RTI_CLK | Input muxed clock |
| 2 | DEV_RTI24_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_RTI24_RTI_CLK |
| 3 | DEV_RTI24_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_RTI24_RTI_CLK |
| 4 | DEV_RTI24_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_RTI24_RTI_CLK |
| 5 | DEV_RTI24_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | Parent input clock option to DEV_RTI24_RTI_CLK |
| 6 | DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_RTI24_RTI_CLK |
| 7 | DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | Parent input clock option to DEV_RTI24_RTI_CLK |
| 8 | DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | Parent input clock option to DEV_RTI24_RTI_CLK |
| 9 | DEV_RTI24_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | Parent input clock option to DEV_RTI24_RTI_CLK |
Clocks for RTI25 Device¶
Device: J721E_DEV_RTI25 (ID = 255)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_RTI25_VBUSP_CLK | Input clock |
| 1 | DEV_RTI25_RTI_CLK | Input muxed clock |
| 2 | DEV_RTI25_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_RTI25_RTI_CLK |
| 3 | DEV_RTI25_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_RTI25_RTI_CLK |
| 4 | DEV_RTI25_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_RTI25_RTI_CLK |
| 5 | DEV_RTI25_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | Parent input clock option to DEV_RTI25_RTI_CLK |
| 6 | DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_RTI25_RTI_CLK |
| 7 | DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | Parent input clock option to DEV_RTI25_RTI_CLK |
| 8 | DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | Parent input clock option to DEV_RTI25_RTI_CLK |
| 9 | DEV_RTI25_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | Parent input clock option to DEV_RTI25_RTI_CLK |
Clocks for RTI28 Device¶
Device: J721E_DEV_RTI28 (ID = 258)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_RTI28_VBUSP_CLK | Input clock |
| 1 | DEV_RTI28_RTI_CLK | Input muxed clock |
| 2 | DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_RTI28_RTI_CLK |
| 3 | DEV_RTI28_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_RTI28_RTI_CLK |
| 4 | DEV_RTI28_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_RTI28_RTI_CLK |
| 5 | DEV_RTI28_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | Parent input clock option to DEV_RTI28_RTI_CLK |
| 6 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_RTI28_RTI_CLK |
| 7 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | Parent input clock option to DEV_RTI28_RTI_CLK |
| 8 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | Parent input clock option to DEV_RTI28_RTI_CLK |
| 9 | DEV_RTI28_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | Parent input clock option to DEV_RTI28_RTI_CLK |
Clocks for RTI29 Device¶
Device: J721E_DEV_RTI29 (ID = 259)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_RTI29_VBUSP_CLK | Input clock |
| 1 | DEV_RTI29_RTI_CLK | Input muxed clock |
| 2 | DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_RTI29_RTI_CLK |
| 3 | DEV_RTI29_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_RTI29_RTI_CLK |
| 4 | DEV_RTI29_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_RTI29_RTI_CLK |
| 5 | DEV_RTI29_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | Parent input clock option to DEV_RTI29_RTI_CLK |
| 6 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_RTI29_RTI_CLK |
| 7 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | Parent input clock option to DEV_RTI29_RTI_CLK |
| 8 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | Parent input clock option to DEV_RTI29_RTI_CLK |
| 9 | DEV_RTI29_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | Parent input clock option to DEV_RTI29_RTI_CLK |
Clocks for RTI30 Device¶
Device: J721E_DEV_RTI30 (ID = 260)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_RTI30_VBUSP_CLK | Input clock |
| 1 | DEV_RTI30_RTI_CLK | Input muxed clock |
| 2 | DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_RTI30_RTI_CLK |
| 3 | DEV_RTI30_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_RTI30_RTI_CLK |
| 4 | DEV_RTI30_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_RTI30_RTI_CLK |
| 5 | DEV_RTI30_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | Parent input clock option to DEV_RTI30_RTI_CLK |
| 6 | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_RTI30_RTI_CLK |
| 7 | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | Parent input clock option to DEV_RTI30_RTI_CLK |
| 8 | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | Parent input clock option to DEV_RTI30_RTI_CLK |
| 9 | DEV_RTI30_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | Parent input clock option to DEV_RTI30_RTI_CLK |
Clocks for RTI31 Device¶
Device: J721E_DEV_RTI31 (ID = 261)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_RTI31_VBUSP_CLK | Input clock |
| 1 | DEV_RTI31_RTI_CLK | Input muxed clock |
| 2 | DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_RTI31_RTI_CLK |
| 3 | DEV_RTI31_RTI_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_RTI31_RTI_CLK |
| 4 | DEV_RTI31_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_RTI31_RTI_CLK |
| 5 | DEV_RTI31_RTI_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_32K_CLK | Parent input clock option to DEV_RTI31_RTI_CLK |
| 6 | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_RTI31_RTI_CLK |
| 7 | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP0 | Parent input clock option to DEV_RTI31_RTI_CLK |
| 8 | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP1 | Parent input clock option to DEV_RTI31_RTI_CLK |
| 9 | DEV_RTI31_RTI_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT_DUP2 | Parent input clock option to DEV_RTI31_RTI_CLK |
Clocks for SA2_UL0 Device¶
Device: J721E_DEV_SA2_UL0 (ID = 264)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_SA2_UL0_X2_CLK | Input clock |
| 1 | DEV_SA2_UL0_PKA_IN_CLK | Input clock |
| 2 | DEV_SA2_UL0_X1_CLK | Input clock |
Clocks for SERDES_10G0 Device¶
Device: J721E_DEV_SERDES_10G0 (ID = 297)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_SERDES_10G0_IP1_LN3_TXCLK | Input clock |
| 1 | DEV_SERDES_10G0_CLK | Input clock |
| 2 | DEV_SERDES_10G0_IP3_LN2_TXCLK | Input clock |
| 3 | DEV_SERDES_10G0_IP1_LN2_TXCLK | Input clock |
| 4 | DEV_SERDES_10G0_IP1_LN0_TXCLK | Input clock |
| 5 | DEV_SERDES_10G0_IP3_LN1_TXCLK | Input clock |
| 6 | DEV_SERDES_10G0_IP3_LN3_TXCLK | Input clock |
| 7 | DEV_SERDES_10G0_IP3_LN0_TXCLK | Input clock |
| 8 | DEV_SERDES_10G0_IP1_LN1_TXCLK | Input clock |
| 9 | DEV_SERDES_10G0_CORE_REF_CLK | Input muxed clock |
| 10 | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK |
| 11 | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK |
| 12 | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK |
| 13 | DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | Parent input clock option to DEV_SERDES_10G0_CORE_REF_CLK |
| 14 | DEV_SERDES_10G0_IP1_LN1_REFCLK | Output clock |
| 15 | DEV_SERDES_10G0_IP1_LN2_RXCLK | Output clock |
| 16 | DEV_SERDES_10G0_IP3_LN1_TXFCLK | Output clock |
| 17 | DEV_SERDES_10G0_IP1_LN0_RXFCLK | Output clock |
| 18 | DEV_SERDES_10G0_IP1_LN3_RXCLK | Output clock |
| 19 | DEV_SERDES_10G0_IP3_LN3_RXCLK | Output clock |
| 20 | DEV_SERDES_10G0_IP3_LN1_TXMCLK | Output clock |
| 21 | DEV_SERDES_10G0_IP3_LN3_RXFCLK | Output clock |
| 22 | DEV_SERDES_10G0_IP3_LN3_REFCLK | Output clock |
| 23 | DEV_SERDES_10G0_IP3_LN2_RXCLK | Output clock |
| 24 | DEV_SERDES_10G0_IP1_LN0_TXFCLK | Output clock |
| 25 | DEV_SERDES_10G0_IP3_LN3_TXMCLK | Output clock |
| 26 | DEV_SERDES_10G0_IP3_LN1_RXFCLK | Output clock |
| 27 | DEV_SERDES_10G0_IP3_LN0_RXFCLK | Output clock |
| 28 | DEV_SERDES_10G0_IP1_LN1_TXMCLK | Output clock |
| 29 | DEV_SERDES_10G0_IP1_LN1_RXFCLK | Output clock |
| 30 | DEV_SERDES_10G0_IP3_LN3_TXFCLK | Output clock |
| 31 | DEV_SERDES_10G0_IP1_LN3_TXFCLK | Output clock |
| 32 | DEV_SERDES_10G0_IP1_LN3_TXMCLK | Output clock |
| 33 | DEV_SERDES_10G0_IP3_LN1_REFCLK | Output clock |
| 34 | DEV_SERDES_10G0_IP3_LN0_REFCLK | Output clock |
| 35 | DEV_SERDES_10G0_IP1_LN3_REFCLK | Output clock |
| 36 | DEV_SERDES_10G0_IP3_LN0_RXCLK | Output clock |
| 37 | DEV_SERDES_10G0_IP3_LN2_REFCLK | Output clock |
| 38 | DEV_SERDES_10G0_IP1_LN0_RXCLK | Output clock |
| 39 | DEV_SERDES_10G0_IP1_LN0_REFCLK | Output clock |
| 40 | DEV_SERDES_10G0_IP1_LN2_RXFCLK | Output clock |
| 41 | DEV_SERDES_10G0_IP1_LN1_TXFCLK | Output clock |
| 42 | DEV_SERDES_10G0_IP3_LN0_TXFCLK | Output clock |
| 43 | DEV_SERDES_10G0_REF_OUT_CLK | Output clock |
| 44 | DEV_SERDES_10G0_IP3_LN1_RXCLK | Output clock |
| 45 | DEV_SERDES_10G0_IP1_LN2_TXFCLK | Output clock |
| 46 | DEV_SERDES_10G0_IP1_LN0_TXMCLK | Output clock |
| 47 | DEV_SERDES_10G0_IP3_LN2_RXFCLK | Output clock |
| 48 | DEV_SERDES_10G0_IP1_LN2_TXMCLK | Output clock |
| 49 | DEV_SERDES_10G0_IP3_LN2_TXMCLK | Output clock |
| 50 | DEV_SERDES_10G0_IP1_LN2_REFCLK | Output clock |
| 51 | DEV_SERDES_10G0_IP3_LN2_TXFCLK | Output clock |
| 52 | DEV_SERDES_10G0_IP3_LN0_TXMCLK | Output clock |
| 53 | DEV_SERDES_10G0_IP1_LN3_RXFCLK | Output clock |
| 54 | DEV_SERDES_10G0_IP1_LN1_RXCLK | Output clock |
Clocks for SERDES_16G0 Device¶
Device: J721E_DEV_SERDES_16G0 (ID = 292)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_SERDES_16G0_CORE_REF1_CLK | Input muxed clock |
| 1 | DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK |
| 2 | DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK |
| 3 | DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK |
| 4 | DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | Parent input clock option to DEV_SERDES_16G0_CORE_REF1_CLK |
| 5 | DEV_SERDES_16G0_CLK | Input clock |
| 6 | DEV_SERDES_16G0_IP1_LN0_TXCLK | Input clock |
| 7 | DEV_SERDES_16G0_IP2_LN1_TXCLK | Input clock |
| 8 | DEV_SERDES_16G0_IP3_LN1_TXCLK | Input clock |
| 9 | DEV_SERDES_16G0_IP2_LN0_TXCLK | Input clock |
| 10 | DEV_SERDES_16G0_IP1_LN1_TXCLK | Input clock |
| 11 | DEV_SERDES_16G0_CORE_REF_CLK | Input muxed clock |
| 12 | DEV_SERDES_16G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK |
| 13 | DEV_SERDES_16G0_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK |
| 14 | DEV_SERDES_16G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK |
| 15 | DEV_SERDES_16G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | Parent input clock option to DEV_SERDES_16G0_CORE_REF_CLK |
| 16 | DEV_SERDES_16G0_IP2_LN0_TXFCLK | Output clock |
| 17 | DEV_SERDES_16G0_IP1_LN1_REFCLK | Output clock |
| 18 | DEV_SERDES_16G0_IP3_LN1_TXMCLK | Output clock |
| 19 | DEV_SERDES_16G0_IP3_LN1_TXFCLK | Output clock |
| 20 | DEV_SERDES_16G0_IP1_LN0_RXFCLK | Output clock |
| 21 | DEV_SERDES_16G0_IP2_LN1_REFCLK | Output clock |
| 22 | DEV_SERDES_16G0_IP2_LN1_TXFCLK | Output clock |
| 23 | DEV_SERDES_16G0_REF_DER_OUT_CLK | Output clock |
| 24 | DEV_SERDES_16G0_IP1_LN0_TXFCLK | Output clock |
| 25 | DEV_SERDES_16G0_IP3_LN1_RXFCLK | Output clock |
| 26 | DEV_SERDES_16G0_IP1_LN1_TXMCLK | Output clock |
| 27 | DEV_SERDES_16G0_IP1_LN1_RXFCLK | Output clock |
| 28 | DEV_SERDES_16G0_IP3_LN1_RXCLK | Output clock |
| 29 | DEV_SERDES_16G0_IP3_LN1_REFCLK | Output clock |
| 30 | DEV_SERDES_16G0_IP2_LN1_RXCLK | Output clock |
| 31 | DEV_SERDES_16G0_IP2_LN0_RXFCLK | Output clock |
| 32 | DEV_SERDES_16G0_IP1_LN0_RXCLK | Output clock |
| 33 | DEV_SERDES_16G0_REF_OUT_CLK | Output clock |
| 34 | DEV_SERDES_16G0_REF1_OUT_CLK | Output clock |
| 35 | DEV_SERDES_16G0_IP1_LN0_REFCLK | Output clock |
| 36 | DEV_SERDES_16G0_IP1_LN0_TXMCLK | Output clock |
| 37 | DEV_SERDES_16G0_IP2_LN1_RXFCLK | Output clock |
| 38 | DEV_SERDES_16G0_IP2_LN1_TXMCLK | Output clock |
| 39 | DEV_SERDES_16G0_IP2_LN0_REFCLK | Output clock |
| 40 | DEV_SERDES_16G0_IP2_LN0_TXMCLK | Output clock |
| 41 | DEV_SERDES_16G0_IP1_LN1_TXFCLK | Output clock |
| 42 | DEV_SERDES_16G0_IP2_LN0_RXCLK | Output clock |
| 43 | DEV_SERDES_16G0_IP1_LN1_RXCLK | Output clock |
| 49 | DEV_SERDES_16G0_CMN_REFCLK1_M | Input clock |
| 57 | DEV_SERDES_16G0_CMN_REFCLK1_P | Input clock |
Clocks for SERDES_16G1 Device¶
Device: J721E_DEV_SERDES_16G1 (ID = 293)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_SERDES_16G1_CORE_REF1_CLK | Input muxed clock |
| 1 | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK |
| 2 | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK |
| 3 | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK |
| 4 | DEV_SERDES_16G1_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | Parent input clock option to DEV_SERDES_16G1_CORE_REF1_CLK |
| 5 | DEV_SERDES_16G1_CLK | Input clock |
| 6 | DEV_SERDES_16G1_IP1_LN0_TXCLK | Input clock |
| 7 | DEV_SERDES_16G1_IP2_LN1_TXCLK | Input clock |
| 8 | DEV_SERDES_16G1_IP4_LN1_TXCLK | Input clock |
| 9 | DEV_SERDES_16G1_IP4_LN0_TXCLK | Input clock |
| 10 | DEV_SERDES_16G1_IP3_LN1_TXCLK | Input clock |
| 11 | DEV_SERDES_16G1_IP2_LN0_TXCLK | Input clock |
| 12 | DEV_SERDES_16G1_IP1_LN1_TXCLK | Input clock |
| 13 | DEV_SERDES_16G1_CORE_REF_CLK | Input muxed clock |
| 14 | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK |
| 15 | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK |
| 16 | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK |
| 17 | DEV_SERDES_16G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | Parent input clock option to DEV_SERDES_16G1_CORE_REF_CLK |
| 18 | DEV_SERDES_16G1_IP2_LN0_TXFCLK | Output clock |
| 19 | DEV_SERDES_16G1_IP1_LN1_REFCLK | Output clock |
| 20 | DEV_SERDES_16G1_IP4_LN1_RXFCLK | Output clock |
| 21 | DEV_SERDES_16G1_IP3_LN1_TXMCLK | Output clock |
| 22 | DEV_SERDES_16G1_IP3_LN1_TXFCLK | Output clock |
| 23 | DEV_SERDES_16G1_IP1_LN0_RXFCLK | Output clock |
| 24 | DEV_SERDES_16G1_IP2_LN1_REFCLK | Output clock |
| 25 | DEV_SERDES_16G1_IP2_LN1_TXFCLK | Output clock |
| 26 | DEV_SERDES_16G1_REF_DER_OUT_CLK | Output clock |
| 27 | DEV_SERDES_16G1_IP1_LN0_TXFCLK | Output clock |
| 28 | DEV_SERDES_16G1_IP3_LN1_RXFCLK | Output clock |
| 29 | DEV_SERDES_16G1_IP1_LN1_TXMCLK | Output clock |
| 30 | DEV_SERDES_16G1_IP1_LN1_RXFCLK | Output clock |
| 31 | DEV_SERDES_16G1_IP4_LN1_REFCLK | Output clock |
| 32 | DEV_SERDES_16G1_IP3_LN1_RXCLK | Output clock |
| 33 | DEV_SERDES_16G1_IP4_LN1_TXMCLK | Output clock |
| 34 | DEV_SERDES_16G1_IP3_LN1_REFCLK | Output clock |
| 35 | DEV_SERDES_16G1_IP4_LN0_REFCLK | Output clock |
| 36 | DEV_SERDES_16G1_IP2_LN1_RXCLK | Output clock |
| 37 | DEV_SERDES_16G1_IP2_LN0_RXFCLK | Output clock |
| 38 | DEV_SERDES_16G1_IP1_LN0_RXCLK | Output clock |
| 39 | DEV_SERDES_16G1_REF_OUT_CLK | Output clock |
| 40 | DEV_SERDES_16G1_REF1_OUT_CLK | Output clock |
| 41 | DEV_SERDES_16G1_IP4_LN1_RXCLK | Output clock |
| 42 | DEV_SERDES_16G1_IP1_LN0_REFCLK | Output clock |
| 43 | DEV_SERDES_16G1_IP1_LN0_TXMCLK | Output clock |
| 44 | DEV_SERDES_16G1_IP4_LN0_TXFCLK | Output clock |
| 45 | DEV_SERDES_16G1_IP4_LN0_RXCLK | Output clock |
| 46 | DEV_SERDES_16G1_IP2_LN1_RXFCLK | Output clock |
| 47 | DEV_SERDES_16G1_IP2_LN1_TXMCLK | Output clock |
| 48 | DEV_SERDES_16G1_IP4_LN0_RXFCLK | Output clock |
| 49 | DEV_SERDES_16G1_IP2_LN0_REFCLK | Output clock |
| 50 | DEV_SERDES_16G1_IP2_LN0_TXMCLK | Output clock |
| 51 | DEV_SERDES_16G1_IP1_LN1_TXFCLK | Output clock |
| 52 | DEV_SERDES_16G1_IP2_LN0_RXCLK | Output clock |
| 53 | DEV_SERDES_16G1_IP4_LN0_TXMCLK | Output clock |
| 54 | DEV_SERDES_16G1_IP1_LN1_RXCLK | Output clock |
| 55 | DEV_SERDES_16G1_IP4_LN1_TXFCLK | Output clock |
| 60 | DEV_SERDES_16G1_CMN_REFCLK1_M | Input clock |
| 67 | DEV_SERDES_16G1_CMN_REFCLK1_P | Input clock |
Clocks for SERDES_16G2 Device¶
Device: J721E_DEV_SERDES_16G2 (ID = 294)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_SERDES_16G2_CORE_REF1_CLK | Input muxed clock |
| 1 | DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK |
| 2 | DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK |
| 3 | DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK |
| 4 | DEV_SERDES_16G2_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | Parent input clock option to DEV_SERDES_16G2_CORE_REF1_CLK |
| 5 | DEV_SERDES_16G2_CLK | Input clock |
| 6 | DEV_SERDES_16G2_IP2_LN1_TXCLK | Input clock |
| 7 | DEV_SERDES_16G2_IP4_LN1_TXCLK | Input clock |
| 8 | DEV_SERDES_16G2_IP4_LN0_TXCLK | Input clock |
| 9 | DEV_SERDES_16G2_IP3_LN1_TXCLK | Input clock |
| 10 | DEV_SERDES_16G2_IP2_LN0_TXCLK | Input clock |
| 11 | DEV_SERDES_16G2_CORE_REF_CLK | Input muxed clock |
| 12 | DEV_SERDES_16G2_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_SERDES_16G2_CORE_REF_CLK |
| 13 | DEV_SERDES_16G2_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_SERDES_16G2_CORE_REF_CLK |
| 14 | DEV_SERDES_16G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | Parent input clock option to DEV_SERDES_16G2_CORE_REF_CLK |
| 15 | DEV_SERDES_16G2_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | Parent input clock option to DEV_SERDES_16G2_CORE_REF_CLK |
| 16 | DEV_SERDES_16G2_IP2_LN0_TXFCLK | Output clock |
| 17 | DEV_SERDES_16G2_IP4_LN1_RXFCLK | Output clock |
| 18 | DEV_SERDES_16G2_IP3_LN1_TXMCLK | Output clock |
| 19 | DEV_SERDES_16G2_IP3_LN1_TXFCLK | Output clock |
| 20 | DEV_SERDES_16G2_IP2_LN1_REFCLK | Output clock |
| 21 | DEV_SERDES_16G2_IP2_LN1_TXFCLK | Output clock |
| 22 | DEV_SERDES_16G2_REF_DER_OUT_CLK | Output clock |
| 23 | DEV_SERDES_16G2_IP3_LN1_RXFCLK | Output clock |
| 24 | DEV_SERDES_16G2_IP4_LN1_REFCLK | Output clock |
| 25 | DEV_SERDES_16G2_IP3_LN1_RXCLK | Output clock |
| 26 | DEV_SERDES_16G2_IP4_LN1_TXMCLK | Output clock |
| 27 | DEV_SERDES_16G2_IP3_LN1_REFCLK | Output clock |
| 28 | DEV_SERDES_16G2_IP4_LN0_REFCLK | Output clock |
| 29 | DEV_SERDES_16G2_IP2_LN1_RXCLK | Output clock |
| 30 | DEV_SERDES_16G2_IP2_LN0_RXFCLK | Output clock |
| 31 | DEV_SERDES_16G2_REF_OUT_CLK | Output clock |
| 32 | DEV_SERDES_16G2_REF1_OUT_CLK | Output clock |
| 33 | DEV_SERDES_16G2_IP4_LN1_RXCLK | Output clock |
| 34 | DEV_SERDES_16G2_IP4_LN0_TXFCLK | Output clock |
| 35 | DEV_SERDES_16G2_IP4_LN0_RXCLK | Output clock |
| 36 | DEV_SERDES_16G2_IP2_LN1_RXFCLK | Output clock |
| 37 | DEV_SERDES_16G2_IP2_LN1_TXMCLK | Output clock |
| 38 | DEV_SERDES_16G2_IP4_LN0_RXFCLK | Output clock |
| 39 | DEV_SERDES_16G2_IP2_LN0_REFCLK | Output clock |
| 40 | DEV_SERDES_16G2_IP2_LN0_TXMCLK | Output clock |
| 41 | DEV_SERDES_16G2_IP2_LN0_RXCLK | Output clock |
| 42 | DEV_SERDES_16G2_IP4_LN0_TXMCLK | Output clock |
| 43 | DEV_SERDES_16G2_IP4_LN1_TXFCLK | Output clock |
| 51 | DEV_SERDES_16G2_CMN_REFCLK1_M | Input clock |
| 61 | DEV_SERDES_16G2_CMN_REFCLK1_P | Input clock |
Clocks for SERDES_16G3 Device¶
Device: J721E_DEV_SERDES_16G3 (ID = 295)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_SERDES_16G3_CORE_REF1_CLK | Input muxed clock |
| 1 | DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK |
| 2 | DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK |
| 3 | DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK |
| 4 | DEV_SERDES_16G3_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | Parent input clock option to DEV_SERDES_16G3_CORE_REF1_CLK |
| 5 | DEV_SERDES_16G3_CLK | Input clock |
| 6 | DEV_SERDES_16G3_IP2_LN1_TXCLK | Input clock |
| 7 | DEV_SERDES_16G3_IP3_LN1_TXCLK | Input clock |
| 8 | DEV_SERDES_16G3_IP2_LN0_TXCLK | Input clock |
| 9 | DEV_SERDES_16G3_CORE_REF_CLK | Input muxed clock |
| 10 | DEV_SERDES_16G3_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_SERDES_16G3_CORE_REF_CLK |
| 11 | DEV_SERDES_16G3_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_SERDES_16G3_CORE_REF_CLK |
| 12 | DEV_SERDES_16G3_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | Parent input clock option to DEV_SERDES_16G3_CORE_REF_CLK |
| 13 | DEV_SERDES_16G3_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | Parent input clock option to DEV_SERDES_16G3_CORE_REF_CLK |
| 14 | DEV_SERDES_16G3_IP2_LN0_TXFCLK | Output clock |
| 15 | DEV_SERDES_16G3_IP3_LN1_TXMCLK | Output clock |
| 16 | DEV_SERDES_16G3_IP3_LN1_TXFCLK | Output clock |
| 17 | DEV_SERDES_16G3_IP2_LN1_REFCLK | Output clock |
| 18 | DEV_SERDES_16G3_IP2_LN1_TXFCLK | Output clock |
| 19 | DEV_SERDES_16G3_REF_DER_OUT_CLK | Output clock |
| 20 | DEV_SERDES_16G3_IP3_LN1_RXFCLK | Output clock |
| 21 | DEV_SERDES_16G3_IP3_LN1_RXCLK | Output clock |
| 22 | DEV_SERDES_16G3_IP3_LN1_REFCLK | Output clock |
| 23 | DEV_SERDES_16G3_IP2_LN1_RXCLK | Output clock |
| 24 | DEV_SERDES_16G3_IP2_LN0_RXFCLK | Output clock |
| 25 | DEV_SERDES_16G3_REF_OUT_CLK | Output clock |
| 26 | DEV_SERDES_16G3_REF1_OUT_CLK | Output clock |
| 27 | DEV_SERDES_16G3_IP2_LN1_RXFCLK | Output clock |
| 28 | DEV_SERDES_16G3_IP2_LN1_TXMCLK | Output clock |
| 29 | DEV_SERDES_16G3_IP2_LN0_REFCLK | Output clock |
| 30 | DEV_SERDES_16G3_IP2_LN0_TXMCLK | Output clock |
| 31 | DEV_SERDES_16G3_IP2_LN0_RXCLK | Output clock |
| 40 | DEV_SERDES_16G3_CMN_REFCLK1_M | Input clock |
| 51 | DEV_SERDES_16G3_CMN_REFCLK1_P | Input clock |
Clocks for STM0 Device¶
Device: J721E_DEV_STM0 (ID = 29)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_STM0_VBUSP_CLK | Input clock |
| 1 | DEV_STM0_CORE_CLK | Input clock |
| 2 | DEV_STM0_ATB_CLK | Input clock |
Clocks for TIMER0 Device¶
Device: J721E_DEV_TIMER0 (ID = 49)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER0_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER0_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
| 3 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
| 4 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
| 5 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
| 6 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
| 7 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
| 8 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
| 9 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
| 10 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
| 11 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
| 12 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
| 13 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
| 14 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
| 15 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
| 16 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
| 17 | DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER0_TIMER_TCLK_CLK |
| 18 | DEV_TIMER0_TIMER_PWM | Output clock |
Clocks for TIMER1 Device¶
Device: J721E_DEV_TIMER1 (ID = 50)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER1_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER1_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_TIMER1_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT1 | Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK |
| 3 | DEV_TIMER1_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_0_TIMER_PWM | Parent input clock option to DEV_TIMER1_TIMER_TCLK_CLK |
Clocks for TIMER10 Device¶
Device: J721E_DEV_TIMER10 (ID = 60)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER10_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER10_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
| 3 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
| 4 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
| 5 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
| 6 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
| 7 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
| 8 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
| 9 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
| 10 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
| 11 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
| 12 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
| 13 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
| 14 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
| 15 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
| 16 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
| 17 | DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER10_TIMER_TCLK_CLK |
| 18 | DEV_TIMER10_TIMER_PWM | Output clock |
Clocks for TIMER11 Device¶
Device: J721E_DEV_TIMER11 (ID = 62)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER11_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER11_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_TIMER11_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT11 | Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK |
| 3 | DEV_TIMER11_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_10_TIMER_PWM | Parent input clock option to DEV_TIMER11_TIMER_TCLK_CLK |
Clocks for TIMER11_CLKSEL_VD Device¶
Device: J721E_DEV_TIMER11_CLKSEL_VD (ID = 332)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER11_CLKSEL_VD_CLK | Input muxed clock |
| 1 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK |
| 2 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK |
| 3 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK |
| 4 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK |
| 5 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK |
| 6 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK |
| 7 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK |
| 8 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK |
| 9 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK |
| 10 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK |
| 11 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK |
| 12 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK |
| 13 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK |
| 14 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK |
| 15 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK |
| 16 | DEV_TIMER11_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER11_CLKSEL_VD_CLK |
Clocks for TIMER12 Device¶
Device: J721E_DEV_TIMER12 (ID = 63)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER12_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER12_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
| 3 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
| 4 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
| 5 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
| 6 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
| 7 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
| 8 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
| 9 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
| 10 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
| 11 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
| 12 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
| 13 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
| 14 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
| 15 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
| 16 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
| 17 | DEV_TIMER12_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER12_TIMER_TCLK_CLK |
| 18 | DEV_TIMER12_TIMER_PWM | Output clock |
Clocks for TIMER13 Device¶
Device: J721E_DEV_TIMER13 (ID = 64)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER13_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER13_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_TIMER13_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT13 | Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK |
| 3 | DEV_TIMER13_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_12_TIMER_PWM | Parent input clock option to DEV_TIMER13_TIMER_TCLK_CLK |
Clocks for TIMER13_CLKSEL_VD Device¶
Device: J721E_DEV_TIMER13_CLKSEL_VD (ID = 333)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER13_CLKSEL_VD_CLK | Input muxed clock |
| 1 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK |
| 2 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK |
| 3 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK |
| 4 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK |
| 5 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK |
| 6 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK |
| 7 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK |
| 8 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK |
| 9 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK |
| 10 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK |
| 11 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK |
| 12 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK |
| 13 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK |
| 14 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK |
| 15 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK |
| 16 | DEV_TIMER13_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER13_CLKSEL_VD_CLK |
Clocks for TIMER14 Device¶
Device: J721E_DEV_TIMER14 (ID = 65)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER14_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER14_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
| 3 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
| 4 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
| 5 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
| 6 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
| 7 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
| 8 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
| 9 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
| 10 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
| 11 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
| 12 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
| 13 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
| 14 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
| 15 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
| 16 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
| 17 | DEV_TIMER14_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER14_TIMER_TCLK_CLK |
| 18 | DEV_TIMER14_TIMER_PWM | Output clock |
Clocks for TIMER15 Device¶
Device: J721E_DEV_TIMER15 (ID = 66)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER15_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER15_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_TIMER15_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT15 | Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK |
| 3 | DEV_TIMER15_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_14_TIMER_PWM | Parent input clock option to DEV_TIMER15_TIMER_TCLK_CLK |
Clocks for TIMER15_CLKSEL_VD Device¶
Device: J721E_DEV_TIMER15_CLKSEL_VD (ID = 334)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER15_CLKSEL_VD_CLK | Input muxed clock |
| 1 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK |
| 2 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK |
| 3 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK |
| 4 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK |
| 5 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK |
| 6 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK |
| 7 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK |
| 8 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK |
| 9 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK |
| 10 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK |
| 11 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK |
| 12 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK |
| 13 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK |
| 14 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK |
| 15 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK |
| 16 | DEV_TIMER15_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER15_CLKSEL_VD_CLK |
Clocks for TIMER16 Device¶
Device: J721E_DEV_TIMER16 (ID = 67)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER16_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER16_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
| 3 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
| 4 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
| 5 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
| 6 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
| 7 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
| 8 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
| 9 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
| 10 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
| 11 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
| 12 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
| 13 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
| 14 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
| 15 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
| 16 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
| 17 | DEV_TIMER16_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER16_TIMER_TCLK_CLK |
| 18 | DEV_TIMER16_TIMER_PWM | Output clock |
Clocks for TIMER17 Device¶
Device: J721E_DEV_TIMER17 (ID = 68)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER17_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER17_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_TIMER17_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT17 | Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK |
| 3 | DEV_TIMER17_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_16_TIMER_PWM | Parent input clock option to DEV_TIMER17_TIMER_TCLK_CLK |
Clocks for TIMER17_CLKSEL_VD Device¶
Device: J721E_DEV_TIMER17_CLKSEL_VD (ID = 335)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER17_CLKSEL_VD_CLK | Input muxed clock |
| 1 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK |
| 2 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK |
| 3 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK |
| 4 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK |
| 5 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK |
| 6 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK |
| 7 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK |
| 8 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK |
| 9 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK |
| 10 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK |
| 11 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK |
| 12 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK |
| 13 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK |
| 14 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK |
| 15 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK |
| 16 | DEV_TIMER17_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER17_CLKSEL_VD_CLK |
Clocks for TIMER18 Device¶
Device: J721E_DEV_TIMER18 (ID = 69)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER18_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER18_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
| 3 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
| 4 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
| 5 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
| 6 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
| 7 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
| 8 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
| 9 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
| 10 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
| 11 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
| 12 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
| 13 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
| 14 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
| 15 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
| 16 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
| 17 | DEV_TIMER18_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER18_TIMER_TCLK_CLK |
| 18 | DEV_TIMER18_TIMER_PWM | Output clock |
Clocks for TIMER19 Device¶
Device: J721E_DEV_TIMER19 (ID = 70)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER19_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER19_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_TIMER19_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT19 | Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK |
| 3 | DEV_TIMER19_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_18_TIMER_PWM | Parent input clock option to DEV_TIMER19_TIMER_TCLK_CLK |
Clocks for TIMER19_CLKSEL_VD Device¶
Device: J721E_DEV_TIMER19_CLKSEL_VD (ID = 336)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER19_CLKSEL_VD_CLK | Input muxed clock |
| 1 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK |
| 2 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK |
| 3 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK |
| 4 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK |
| 5 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK |
| 6 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK |
| 7 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK |
| 8 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK |
| 9 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK |
| 10 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK |
| 11 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK |
| 12 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK |
| 13 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK |
| 14 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK |
| 15 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK |
| 16 | DEV_TIMER19_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER19_CLKSEL_VD_CLK |
Clocks for TIMER1_CLKSEL_VD Device¶
Device: J721E_DEV_TIMER1_CLKSEL_VD (ID = 327)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER1_CLKSEL_VD_CLK | Input muxed clock |
| 1 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK |
| 2 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK |
| 3 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK |
| 4 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK |
| 5 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK |
| 6 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK |
| 7 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK |
| 8 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK |
| 9 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK |
| 10 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK |
| 11 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK |
| 12 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK |
| 13 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK |
| 14 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK |
| 15 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK |
| 16 | DEV_TIMER1_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER1_CLKSEL_VD_CLK |
Clocks for TIMER2 Device¶
Device: J721E_DEV_TIMER2 (ID = 51)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER2_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER2_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
| 3 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
| 4 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
| 5 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
| 6 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
| 7 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
| 8 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
| 9 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
| 10 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
| 11 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
| 12 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
| 13 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
| 14 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
| 15 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
| 16 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
| 17 | DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER2_TIMER_TCLK_CLK |
| 18 | DEV_TIMER2_TIMER_PWM | Output clock |
Clocks for TIMER3 Device¶
Device: J721E_DEV_TIMER3 (ID = 52)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER3_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER3_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_TIMER3_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT3 | Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK |
| 3 | DEV_TIMER3_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_2_TIMER_PWM | Parent input clock option to DEV_TIMER3_TIMER_TCLK_CLK |
Clocks for TIMER3_CLKSEL_VD Device¶
Device: J721E_DEV_TIMER3_CLKSEL_VD (ID = 328)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER3_CLKSEL_VD_CLK | Input muxed clock |
| 1 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK |
| 2 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK |
| 3 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK |
| 4 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK |
| 5 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK |
| 6 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK |
| 7 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK |
| 8 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK |
| 9 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK |
| 10 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK |
| 11 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK |
| 12 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK |
| 13 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK |
| 14 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK |
| 15 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK |
| 16 | DEV_TIMER3_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER3_CLKSEL_VD_CLK |
Clocks for TIMER4 Device¶
Device: J721E_DEV_TIMER4 (ID = 53)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER4_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER4_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
| 3 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
| 4 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
| 5 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
| 6 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
| 7 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
| 8 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
| 9 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
| 10 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
| 11 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
| 12 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
| 13 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
| 14 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
| 15 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
| 16 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
| 17 | DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER4_TIMER_TCLK_CLK |
| 18 | DEV_TIMER4_TIMER_PWM | Output clock |
Clocks for TIMER5 Device¶
Device: J721E_DEV_TIMER5 (ID = 54)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER5_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER5_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_TIMER5_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT5 | Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK |
| 3 | DEV_TIMER5_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_4_TIMER_PWM | Parent input clock option to DEV_TIMER5_TIMER_TCLK_CLK |
Clocks for TIMER5_CLKSEL_VD Device¶
Device: J721E_DEV_TIMER5_CLKSEL_VD (ID = 329)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER5_CLKSEL_VD_CLK | Input muxed clock |
| 1 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK |
| 2 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK |
| 3 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK |
| 4 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK |
| 5 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK |
| 6 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK |
| 7 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK |
| 8 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK |
| 9 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK |
| 10 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK |
| 11 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK |
| 12 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK |
| 13 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK |
| 14 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK |
| 15 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK |
| 16 | DEV_TIMER5_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER5_CLKSEL_VD_CLK |
Clocks for TIMER6 Device¶
Device: J721E_DEV_TIMER6 (ID = 55)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER6_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER6_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
| 3 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
| 4 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
| 5 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
| 6 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
| 7 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
| 8 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
| 9 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
| 10 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
| 11 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
| 12 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
| 13 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
| 14 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
| 15 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
| 16 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
| 17 | DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER6_TIMER_TCLK_CLK |
| 18 | DEV_TIMER6_TIMER_PWM | Output clock |
Clocks for TIMER7 Device¶
Device: J721E_DEV_TIMER7 (ID = 57)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER7_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER7_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_TIMER7_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT7 | Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK |
| 3 | DEV_TIMER7_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_6_TIMER_PWM | Parent input clock option to DEV_TIMER7_TIMER_TCLK_CLK |
Clocks for TIMER7_CLKSEL_VD Device¶
Device: J721E_DEV_TIMER7_CLKSEL_VD (ID = 330)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER7_CLKSEL_VD_CLK | Input muxed clock |
| 1 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK |
| 2 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK |
| 3 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK |
| 4 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK |
| 5 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK |
| 6 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK |
| 7 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK |
| 8 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK |
| 9 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK |
| 10 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK |
| 11 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK |
| 12 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK |
| 13 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK |
| 14 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK |
| 15 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK |
| 16 | DEV_TIMER7_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER7_CLKSEL_VD_CLK |
Clocks for TIMER8 Device¶
Device: J721E_DEV_TIMER8 (ID = 58)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER8_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER8_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
| 3 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
| 4 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
| 5 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
| 6 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
| 7 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
| 8 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
| 9 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
| 10 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
| 11 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
| 12 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
| 13 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
| 14 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
| 15 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
| 16 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
| 17 | DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER8_TIMER_TCLK_CLK |
| 18 | DEV_TIMER8_TIMER_PWM | Output clock |
Clocks for TIMER9 Device¶
Device: J721E_DEV_TIMER9 (ID = 59)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER9_TIMER_HCLK_CLK | Input clock |
| 1 | DEV_TIMER9_TIMER_TCLK_CLK | Input muxed clock |
| 2 | DEV_TIMER9_TIMER_TCLK_CLK_PARENT_MAIN_TIMER_CLKSEL_OUT9 | Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK |
| 3 | DEV_TIMER9_TIMER_TCLK_CLK_PARENT_DMTIMER_DMC1MS_MAIN_8_TIMER_PWM | Parent input clock option to DEV_TIMER9_TIMER_TCLK_CLK |
Clocks for TIMER9_CLKSEL_VD Device¶
Device: J721E_DEV_TIMER9_CLKSEL_VD (ID = 331)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMER9_CLKSEL_VD_CLK | Input muxed clock |
| 1 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK |
| 2 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK |
| 3 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK | Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK |
| 4 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_J7_WAKEUP_16FF_WKUP_0_WKUP_RCOSC_12P5M_CLK | Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK |
| 5 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK |
| 6 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK |
| 7 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK |
| 8 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_GLUELOGIC_LPXOSC_CLKOUT | Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK |
| 9 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT | Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK |
| 10 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK | Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK |
| 11 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_POSTDIV2_16FFT_MAIN_2_HSDIVOUT6_CLK | Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK |
| 12 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK |
| 13 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF2 | Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK |
| 14 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_NAVSS512L_MAIN_0_CPTS0_GENF3 | Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK |
| 15 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_CPSW_9XUSS_MAIN_0_CPTS_GENF0 | Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK |
| 16 | DEV_TIMER9_CLKSEL_VD_CLK_PARENT_HSDIV3_16FFT_MAIN_15_HSDIVOUT2_CLK | Parent input clock option to DEV_TIMER9_CLKSEL_VD_CLK |
Clocks for TIMESYNC_INTRTR0 Device¶
Device: J721E_DEV_TIMESYNC_INTRTR0 (ID = 136)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_TIMESYNC_INTRTR0_INTR_CLK | Input clock |
Clocks for UART0 Device¶
Device: J721E_DEV_UART0 (ID = 146)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_UART0_FCLK_CLK | Input clock |
| 1 | DEV_UART0_VBUSP_CLK | Input clock |
Clocks for UART1 Device¶
Device: J721E_DEV_UART1 (ID = 278)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_UART1_FCLK_CLK | Input clock |
| 1 | DEV_UART1_VBUSP_CLK | Input clock |
Clocks for UART2 Device¶
Device: J721E_DEV_UART2 (ID = 279)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_UART2_FCLK_CLK | Input clock |
| 1 | DEV_UART2_VBUSP_CLK | Input clock |
Clocks for UART3 Device¶
Device: J721E_DEV_UART3 (ID = 280)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_UART3_FCLK_CLK | Input clock |
| 1 | DEV_UART3_VBUSP_CLK | Input clock |
Clocks for UART4 Device¶
Device: J721E_DEV_UART4 (ID = 281)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_UART4_FCLK_CLK | Input clock |
| 1 | DEV_UART4_VBUSP_CLK | Input clock |
Clocks for UART5 Device¶
Device: J721E_DEV_UART5 (ID = 282)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_UART5_FCLK_CLK | Input clock |
| 1 | DEV_UART5_VBUSP_CLK | Input clock |
Clocks for UART6 Device¶
Device: J721E_DEV_UART6 (ID = 283)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_UART6_FCLK_CLK | Input clock |
| 1 | DEV_UART6_VBUSP_CLK | Input clock |
Clocks for UART7 Device¶
Device: J721E_DEV_UART7 (ID = 284)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_UART7_FCLK_CLK | Input clock |
| 1 | DEV_UART7_VBUSP_CLK | Input clock |
Clocks for UART8 Device¶
Device: J721E_DEV_UART8 (ID = 285)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_UART8_FCLK_CLK | Input clock |
| 1 | DEV_UART8_VBUSP_CLK | Input clock |
Clocks for UART9 Device¶
Device: J721E_DEV_UART9 (ID = 286)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_UART9_FCLK_CLK | Input clock |
| 1 | DEV_UART9_VBUSP_CLK | Input clock |
Clocks for UFS0 Device¶
Device: J721E_DEV_UFS0 (ID = 277)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_UFS0_UFSHCI_HCLK_CLK | Input clock |
| 1 | DEV_UFS0_UFSHCI_MCLK_CLK | Input muxed clock |
| 2 | DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK |
| 3 | DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK |
| 4 | DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT6_CLK | Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK |
| 5 | DEV_UFS0_UFSHCI_MCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | Parent input clock option to DEV_UFS0_UFSHCI_MCLK_CLK |
| 6 | DEV_UFS0_UFSHCI_MPHY_REFCLK | Output clock |
Clocks for USB0 Device¶
Device: J721E_DEV_USB0 (ID = 288)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_USB0_PIPE_REFCLK | Input muxed clock |
| 1 | DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_REFCLK | Parent input clock option to DEV_USB0_PIPE_REFCLK |
| 2 | DEV_USB0_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_REFCLK | Parent input clock option to DEV_USB0_PIPE_REFCLK |
| 3 | DEV_USB0_CLK_LPM_CLK | Input clock |
| 4 | DEV_USB0_BUF_CLK | Input clock |
| 5 | DEV_USB0_USB2_APB_PCLK_CLK | Input clock |
| 6 | DEV_USB0_PIPE_RXCLK | Input muxed clock |
| 7 | DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_RXCLK | Parent input clock option to DEV_USB0_PIPE_RXCLK |
| 8 | DEV_USB0_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_RXCLK | Parent input clock option to DEV_USB0_PIPE_RXCLK |
| 9 | DEV_USB0_PIPE_TXMCLK | Input muxed clock |
| 10 | DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_TXMCLK | Parent input clock option to DEV_USB0_PIPE_TXMCLK |
| 11 | DEV_USB0_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_TXMCLK | Parent input clock option to DEV_USB0_PIPE_TXMCLK |
| 12 | DEV_USB0_PIPE_RXFCLK | Input muxed clock |
| 13 | DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_RXFCLK | Parent input clock option to DEV_USB0_PIPE_RXFCLK |
| 14 | DEV_USB0_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_RXFCLK | Parent input clock option to DEV_USB0_PIPE_RXFCLK |
| 15 | DEV_USB0_USB2_REFCLOCK_CLK | Input muxed clock |
| 16 | DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK |
| 17 | DEV_USB0_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_USB0_USB2_REFCLOCK_CLK |
| 18 | DEV_USB0_PCLK_CLK | Input clock |
| 19 | DEV_USB0_ACLK_CLK | Input clock |
| 20 | DEV_USB0_PIPE_TXFCLK | Input muxed clock |
| 21 | DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_0_IP3_LN1_TXFCLK | Parent input clock option to DEV_USB0_PIPE_TXFCLK |
| 22 | DEV_USB0_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_3_IP3_LN1_TXFCLK | Parent input clock option to DEV_USB0_PIPE_TXFCLK |
| 23 | DEV_USB0_PIPE_TXCLK | Output clock |
Clocks for USB1 Device¶
Device: J721E_DEV_USB1 (ID = 289)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_USB1_PIPE_REFCLK | Input muxed clock |
| 1 | DEV_USB1_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_REFCLK | Parent input clock option to DEV_USB1_PIPE_REFCLK |
| 2 | DEV_USB1_PIPE_REFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_REFCLK | Parent input clock option to DEV_USB1_PIPE_REFCLK |
| 3 | DEV_USB1_CLK_LPM_CLK | Input clock |
| 4 | DEV_USB1_BUF_CLK | Input clock |
| 5 | DEV_USB1_USB2_APB_PCLK_CLK | Input clock |
| 6 | DEV_USB1_PIPE_RXCLK | Input muxed clock |
| 7 | DEV_USB1_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_RXCLK | Parent input clock option to DEV_USB1_PIPE_RXCLK |
| 8 | DEV_USB1_PIPE_RXCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_RXCLK | Parent input clock option to DEV_USB1_PIPE_RXCLK |
| 9 | DEV_USB1_PIPE_TXMCLK | Input muxed clock |
| 10 | DEV_USB1_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_TXMCLK | Parent input clock option to DEV_USB1_PIPE_TXMCLK |
| 11 | DEV_USB1_PIPE_TXMCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_TXMCLK | Parent input clock option to DEV_USB1_PIPE_TXMCLK |
| 12 | DEV_USB1_PIPE_RXFCLK | Input muxed clock |
| 13 | DEV_USB1_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_RXFCLK | Parent input clock option to DEV_USB1_PIPE_RXFCLK |
| 14 | DEV_USB1_PIPE_RXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_RXFCLK | Parent input clock option to DEV_USB1_PIPE_RXFCLK |
| 15 | DEV_USB1_USB2_REFCLOCK_CLK | Input muxed clock |
| 16 | DEV_USB1_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_USB1_USB2_REFCLOCK_CLK |
| 17 | DEV_USB1_USB2_REFCLOCK_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | Parent input clock option to DEV_USB1_USB2_REFCLOCK_CLK |
| 18 | DEV_USB1_PCLK_CLK | Input clock |
| 19 | DEV_USB1_ACLK_CLK | Input clock |
| 20 | DEV_USB1_PIPE_TXFCLK | Input muxed clock |
| 21 | DEV_USB1_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_1_IP3_LN1_TXFCLK | Parent input clock option to DEV_USB1_PIPE_TXFCLK |
| 22 | DEV_USB1_PIPE_TXFCLK_PARENT_WIZ16B4M4CS_MAIN_2_IP3_LN1_TXFCLK | Parent input clock option to DEV_USB1_PIPE_TXFCLK |
| 23 | DEV_USB1_PIPE_TXCLK | Output clock |
Clocks for VPAC0 Device¶
Device: J721E_DEV_VPAC0 (ID = 290)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_VPAC0_CLK | Input clock |
| 1 | DEV_VPAC0_PLL_DCO_CLK | Input clock |
Clocks for VPFE0 Device¶
Device: J721E_DEV_VPFE0 (ID = 291)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_VPFE0_CCD_PCLK_CLK | Input clock |
| 1 | DEV_VPFE0_VPFE_CLK | Input clock |
Clocks for WKUPMCU2MAIN_VD Device¶
This device has no defined clocks.
Clocks for WKUP_DDPA0 Device¶
Device: J721E_DEV_WKUP_DDPA0 (ID = 145)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_WKUP_DDPA0_DDPA_CLK | Input clock |
Clocks for WKUP_DMSC0 Device¶
This device has no defined clocks.
Clocks for WKUP_ESM0 Device¶
Device: J721E_DEV_WKUP_ESM0 (ID = 99)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_WKUP_ESM0_CLK | Input clock |
Clocks for WKUP_GPIO0 Device¶
Device: J721E_DEV_WKUP_GPIO0 (ID = 113)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_WKUP_GPIO0_MMR_CLK | Input clock |
Clocks for WKUP_GPIO1 Device¶
Device: J721E_DEV_WKUP_GPIO1 (ID = 114)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_WKUP_GPIO1_MMR_CLK | Input clock |
Clocks for WKUP_GPIOMUX_INTRTR0 Device¶
Device: J721E_DEV_WKUP_GPIOMUX_INTRTR0 (ID = 137)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_WKUP_GPIOMUX_INTRTR0_INTR_CLK | Input clock |
Clocks for WKUP_I2C0 Device¶
Device: J721E_DEV_WKUP_I2C0 (ID = 197)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_WKUP_I2C0_PISYS_CLK | Input muxed clock |
| 1 | DEV_WKUP_I2C0_PISYS_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK | Parent input clock option to DEV_WKUP_I2C0_PISYS_CLK |
| 2 | DEV_WKUP_I2C0_PISYS_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_WKUP_I2C0_PISYS_CLK |
| 3 | DEV_WKUP_I2C0_PISCL | Input clock |
| 4 | DEV_WKUP_I2C0_CLK | Input clock |
| 5 | DEV_WKUP_I2C0_PORSCL | Output clock |
Clocks for WKUP_PORZ_SYNC0 Device¶
Device: J721E_DEV_WKUP_PORZ_SYNC0 (ID = 132)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_WKUP_PORZ_SYNC0_CLK_12M_RC_CLK | Input clock |
Clocks for WKUP_PSC0 Device¶
Device: J721E_DEV_WKUP_PSC0 (ID = 138)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_WKUP_PSC0_SLOW_CLK | Input clock |
| 1 | DEV_WKUP_PSC0_CLK | Input clock |
Clocks for WKUP_UART0 Device¶
Device: J721E_DEV_WKUP_UART0 (ID = 287)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_WKUP_UART0_FCLK_CLK | Input muxed clock |
| 1 | DEV_WKUP_UART0_FCLK_CLK_PARENT_WKUPUSART_CLK_SEL_OUT0 | Parent input clock option to DEV_WKUP_UART0_FCLK_CLK |
| 2 | DEV_WKUP_UART0_FCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | Parent input clock option to DEV_WKUP_UART0_FCLK_CLK |
| 3 | DEV_WKUP_UART0_VBUSP_CLK | Input clock |
Clocks for WKUP_VTM0 Device¶
Device: J721E_DEV_WKUP_VTM0 (ID = 154)
Following is a mapping of Clocks IDs to function:
| Clock ID | Name | Function |
|---|---|---|
| 0 | DEV_WKUP_VTM0_FIX_REF2_CLK | Input clock |
| 1 | DEV_WKUP_VTM0_VBUSP_CLK | Input clock |
| 2 | DEV_WKUP_VTM0_FIX_REF_CLK | Input clock |