am6 Peripheral Interrupt Source Descriptions

Introduction

This chapter provides information on peripheral interrupt source IDs that are permitted in the am6 SoC. The interrupt source IDs represent outputs from SoC peripherals capable of generating an egress interrupt or event signal. The System Firmware interrupt management TISCI message APIs take interrupt source IDs as input to set and release interrupt routes between source peripherals and destination host processors.

Event-Based Interrupt Source IDs

Device Name	Device ID	Interrupt Source Name	Interrupt Source Index
AM6_DEV_NAVSS0_RINGACC0	187	Ring events	0 to 767
AM6_DEV_NAVSS0_RINGACC0	187	Ring monitor events	1024 to 1055
AM6_DEV_NAVSS0_RINGACC0	187	Ring global error event	2048
AM6_DEV_MCU_NAVSS0_RINGACC0	195	Ring events	0 to 255
AM6_DEV_MCU_NAVSS0_RINGACC0	195	Ring monitor events	1024 to 1055
AM6_DEV_MCU_NAVSS0_RINGACC0	195	Ring global error event	2048
AM6_DEV_NAVSS0_UDMAP0	188	UDMA transmit channel OES events	0 to 151
AM6_DEV_NAVSS0_UDMAP0	188	UDMA transmit channel EOES events	256 to 407
AM6_DEV_NAVSS0_UDMAP0	188	UDMA receive channel OES events	512 to 661
AM6_DEV_NAVSS0_UDMAP0	188	UDMA receive channel EOES events	768 to 917
AM6_DEV_NAVSS0_UDMAP0	188	UDMA global configuration invalid flow event	1024
AM6_DEV_MCU_NAVSS0_UDMAP0	194	UDMA transmit channel OES events	0 to 47
AM6_DEV_MCU_NAVSS0_UDMAP0	194	UDMA transmit channel EOES events	256 to 303
AM6_DEV_MCU_NAVSS0_UDMAP0	194	UDMA receive channel OES events	512 to 559
AM6_DEV_MCU_NAVSS0_UDMAP0	194	UDMA receive channel EOES events	768 to 815
AM6_DEV_MCU_NAVSS0_UDMAP0	194	UDMA global configuration invalid flow event	1024
AM6_DEV_NAVSS0_PROXY0	185	Proxy events	0 to 63
AM6_DEV_MCU_NAVSS0_PROXY0	191	Proxy events	0 to 63

Non-Event Interrupt Source IDs

Device Name	Device ID	Interrupt Source Design Name	Interrupt Source Index
AM6_DEV_CAL0	2	int_cal_l 0	0
AM6_DEV_CBASS0	82	LPSC_per_common_err_intr 0	0
AM6_DEV_CBASS_DEBUG0	83	LPSC_main_debug_err_intr 0	0
AM6_DEV_CBASS_FW0	84	LPSC_main_infra_err_intr 0	0
AM6_DEV_CBASS_INFRA0	85	LPSC_main_infra_err_intr 0	0
AM6_DEV_CCDEBUGSS0	66	aqcmpintr_level 0	0
AM6_DEV_CTRL_MMR0	99	access_err 0	0
AM6_DEV_DCC0	9	intr_done_level 0	0
AM6_DEV_DCC1	10	intr_done_level 0	0
AM6_DEV_DCC2	11	intr_done_level 0	0
AM6_DEV_DCC3	12	intr_done_level 0	0
AM6_DEV_DCC4	13	intr_done_level 0	0
AM6_DEV_DCC5	14	intr_done_level 0	0
AM6_DEV_DCC6	15	intr_done_level 0	0
AM6_DEV_DCC7	16	intr_done_level 0	0
AM6_DEV_DDRSS0	20	ddrss_v2h_other_err_lvl 0	0
AM6_DEV_DEBUGSS0	68	aqcmpintr_level 0	0
AM6_DEV_DEBUGSS0	68	ctm_level 0	1
AM6_DEV_DSS0	67	dispc_intr_req_0 0	0
AM6_DEV_DSS0	67	dispc_intr_req_1 0	1
AM6_DEV_ECAP0	39	ecap_int 0	0
AM6_DEV_EHRPWM0	40	epwm_etint 0	0
AM6_DEV_EHRPWM0	40	epwm_tripzint 0	1
AM6_DEV_EHRPWM1	41	epwm_etint 0	0
AM6_DEV_EHRPWM1	41	epwm_tripzint 0	1
AM6_DEV_EHRPWM2	42	epwm_etint 0	0
AM6_DEV_EHRPWM2	42	epwm_tripzint 0	1
AM6_DEV_EHRPWM3	43	epwm_etint 0	0
AM6_DEV_EHRPWM3	43	epwm_tripzint 0	1
AM6_DEV_EHRPWM4	44	epwm_etint 0	0
AM6_DEV_EHRPWM4	44	epwm_tripzint 0	1
AM6_DEV_EHRPWM5	45	epwm_etint 0	0
AM6_DEV_EHRPWM5	45	epwm_tripzint 0	1
AM6_DEV_ELM0	46	elm_porocpsinterrupt_lvl 0	0
AM6_DEV_EQEP0	49	eqep_int 0	0
AM6_DEV_EQEP1	50	eqep_int 0	0
AM6_DEV_EQEP2	51	eqep_int 0	0
AM6_DEV_GPIO0	57	gpio 0 to 95	0 to 95
AM6_DEV_GPIO0	57	gpio_bank 0 to 5	96 to 101
AM6_DEV_GPIO1	58	gpio 0 to 89	0 to 89
AM6_DEV_GPIO1	58	gpio_bank 0 to 5	90 to 95
AM6_DEV_GPMC0	60	gpmc_sinterrupt 0	0
AM6_DEV_GPU0	65	exp_intr 0	0
AM6_DEV_GPU0	65	gpu_irq 0	1
AM6_DEV_GPU0	65	init_err 0	2
AM6_DEV_GPU0	65	target_err 0	3
AM6_DEV_GTC0	61	gtc_push_event 0	0
AM6_DEV_I2C0	110	pointrpend 0	0
AM6_DEV_I2C1	111	pointrpend 0	0
AM6_DEV_I2C2	112	pointrpend 0	0
AM6_DEV_I2C3	113	pointrpend 0	0
AM6_DEV_MCASP0	104	rec_intr_pend 0	0
AM6_DEV_MCASP0	104	xmit_intr_pend 0	1
AM6_DEV_MCASP1	105	rec_intr_pend 0	0
AM6_DEV_MCASP1	105	xmit_intr_pend 0	1
AM6_DEV_MCASP2	106	rec_intr_pend 0	0
AM6_DEV_MCASP2	106	xmit_intr_pend 0	1
AM6_DEV_MCSPI0	137	intr_spi 0	0
AM6_DEV_MCSPI1	138	intr_spi 0	0
AM6_DEV_MCSPI2	139	intr_spi 0	0
AM6_DEV_MCSPI3	140	intr_spi 0	0
AM6_DEV_MCU_CPSW0	5	cpts_comp 0	0
AM6_DEV_MCU_CPSW0	5	cpts_genf0 0	1
AM6_DEV_MCU_CPSW0	5	cpts_genf1 0	2
AM6_DEV_MCU_CPSW0	5	cpts_sync 0	3
AM6_DEV_MMCSD0	47	emmcsdss_intr 0	0
AM6_DEV_MMCSD1	48	emmcsdss_intr 0	0
AM6_DEV_NAVSS0	118	cpts0_comp 0	0
AM6_DEV_NAVSS0	118	cpts0_genf0 0	1
AM6_DEV_NAVSS0	118	cpts0_genf1 0	2
AM6_DEV_NAVSS0	118	cpts0_genf2 0	3
AM6_DEV_NAVSS0	118	cpts0_genf3 0	4
AM6_DEV_NAVSS0	118	cpts0_genf4 0	5
AM6_DEV_NAVSS0	118	cpts0_genf5 0	6
AM6_DEV_NAVSS0	118	cpts0_sync 0	7
AM6_DEV_PCIE0	120	pcie0_pend 0	0
AM6_DEV_PCIE0	120	pcie10_pend 0	1
AM6_DEV_PCIE0	120	pcie11_pend 0	2
AM6_DEV_PCIE0	120	pcie12_pend 0	3
AM6_DEV_PCIE0	120	pcie13_pend 0	4
AM6_DEV_PCIE0	120	pcie14_pend 0	5
AM6_DEV_PCIE0	120	pcie1_pend 0	6
AM6_DEV_PCIE0	120	pcie2_pend 0	7
AM6_DEV_PCIE0	120	pcie3_pend 0	8
AM6_DEV_PCIE0	120	pcie4_pend 0	9
AM6_DEV_PCIE0	120	pcie5_pend 0	10
AM6_DEV_PCIE0	120	pcie6_pend 0	11
AM6_DEV_PCIE0	120	pcie7_pend 0	12
AM6_DEV_PCIE0	120	pcie8_pend 0	13
AM6_DEV_PCIE0	120	pcie9_pend 0	14
AM6_DEV_PCIE0	120	pcie_cpts_comp 0	15
AM6_DEV_PCIE0	120	pcie_cpts_genf0 0	16
AM6_DEV_PCIE0	120	pcie_cpts_hw1_push 0	17
AM6_DEV_PCIE0	120	pcie_cpts_pend 0	18
AM6_DEV_PCIE0	120	pcie_cpts_sync 0	19
AM6_DEV_PCIE1	121	pcie0_pend 0	0
AM6_DEV_PCIE1	121	pcie10_pend 0	1
AM6_DEV_PCIE1	121	pcie11_pend 0	2
AM6_DEV_PCIE1	121	pcie12_pend 0	3
AM6_DEV_PCIE1	121	pcie13_pend 0	4
AM6_DEV_PCIE1	121	pcie14_pend 0	5
AM6_DEV_PCIE1	121	pcie1_pend 0	6
AM6_DEV_PCIE1	121	pcie2_pend 0	7
AM6_DEV_PCIE1	121	pcie3_pend 0	8
AM6_DEV_PCIE1	121	pcie4_pend 0	9
AM6_DEV_PCIE1	121	pcie5_pend 0	10
AM6_DEV_PCIE1	121	pcie6_pend 0	11
AM6_DEV_PCIE1	121	pcie7_pend 0	12
AM6_DEV_PCIE1	121	pcie8_pend 0	13
AM6_DEV_PCIE1	121	pcie9_pend 0	14
AM6_DEV_PCIE1	121	pcie_cpts_comp 0	15
AM6_DEV_PCIE1	121	pcie_cpts_genf0 0	16
AM6_DEV_PCIE1	121	pcie_cpts_hw1_push 0	17
AM6_DEV_PCIE1	121	pcie_cpts_pend 0	18
AM6_DEV_PCIE1	121	pcie_cpts_sync 0	19
AM6_DEV_PRU_ICSSG0	62	pr1_edc0_sync0_out 0	0
AM6_DEV_PRU_ICSSG0	62	pr1_edc0_sync1_out 0	1
AM6_DEV_PRU_ICSSG0	62	pr1_edc1_sync0_out 0	2
AM6_DEV_PRU_ICSSG0	62	pr1_edc1_sync1_out 0	3
AM6_DEV_PRU_ICSSG0	62	pr1_host_intr_pend 0 to 7	4 to 11
AM6_DEV_PRU_ICSSG0	62	pr1_host_intr_req 0 to 7	12 to 19
AM6_DEV_PRU_ICSSG0	62	pr1_iep0_cmp_intr_req 0 to 15	20 to 35
AM6_DEV_PRU_ICSSG0	62	pr1_iep1_cmp_intr_req 0 to 15	36 to 51
AM6_DEV_PRU_ICSSG0	62	pr1_rx_sof_intr_req 0 to 1	52 to 53
AM6_DEV_PRU_ICSSG0	62	pr1_tx_sof_intr_req 0 to 1	54 to 55
AM6_DEV_PRU_ICSSG1	63	pr1_edc0_sync0_out 0	0
AM6_DEV_PRU_ICSSG1	63	pr1_edc0_sync1_out 0	1
AM6_DEV_PRU_ICSSG1	63	pr1_edc1_sync0_out 0	2
AM6_DEV_PRU_ICSSG1	63	pr1_edc1_sync1_out 0	3
AM6_DEV_PRU_ICSSG1	63	pr1_host_intr_pend 0 to 7	4 to 11
AM6_DEV_PRU_ICSSG1	63	pr1_host_intr_req 0 to 7	12 to 19
AM6_DEV_PRU_ICSSG1	63	pr1_iep0_cmp_intr_req 0 to 15	20 to 35
AM6_DEV_PRU_ICSSG1	63	pr1_iep1_cmp_intr_req 0 to 15	36 to 51
AM6_DEV_PRU_ICSSG1	63	pr1_rx_sof_intr_req 0 to 1	52 to 53
AM6_DEV_PRU_ICSSG1	63	pr1_tx_sof_intr_req 0 to 1	54 to 55
AM6_DEV_PRU_ICSSG2	64	pr1_edc0_sync0_out 0	0
AM6_DEV_PRU_ICSSG2	64	pr1_edc0_sync1_out 0	1
AM6_DEV_PRU_ICSSG2	64	pr1_edc1_sync0_out 0	2
AM6_DEV_PRU_ICSSG2	64	pr1_edc1_sync1_out 0	3
AM6_DEV_PRU_ICSSG2	64	pr1_host_intr_pend 0 to 7	4 to 11
AM6_DEV_PRU_ICSSG2	64	pr1_host_intr_req 0 to 7	12 to 19
AM6_DEV_PRU_ICSSG2	64	pr1_iep0_cmp_intr_req 0 to 15	20 to 35
AM6_DEV_PRU_ICSSG2	64	pr1_iep1_cmp_intr_req 0 to 15	36 to 51
AM6_DEV_PRU_ICSSG2	64	pr1_rx_sof_intr_req 0 to 1	52 to 53
AM6_DEV_PRU_ICSSG2	64	pr1_tx_sof_intr_req 0 to 1	54 to 55
AM6_DEV_SA2_UL0	136	sa_ul_pka 0	0
AM6_DEV_SA2_UL0	136	sa_ul_trng 0	1
AM6_DEV_TIMER0	23	intr_pend 0	0
AM6_DEV_TIMER1	24	intr_pend 0	0
AM6_DEV_TIMER10	25	intr_pend 0	0
AM6_DEV_TIMER11	26	intr_pend 0	0
AM6_DEV_TIMER2	27	intr_pend 0	0
AM6_DEV_TIMER3	28	intr_pend 0	0
AM6_DEV_TIMER4	29	intr_pend 0	0
AM6_DEV_TIMER5	30	intr_pend 0	0
AM6_DEV_TIMER6	31	intr_pend 0	0
AM6_DEV_TIMER7	32	intr_pend 0	0
AM6_DEV_TIMER8	33	intr_pend 0	0
AM6_DEV_TIMER9	34	intr_pend 0	0
AM6_DEV_UART0	146	usart_irq 0	0
AM6_DEV_UART1	147	usart_irq 0	0
AM6_DEV_UART2	148	usart_irq 0	0
AM6_DEV_USB3SS0	151	bc_lvl 0	0
AM6_DEV_USB3SS0	151	i00_lvl 0	1
AM6_DEV_USB3SS0	151	i01_lvl 0	2
AM6_DEV_USB3SS0	151	i02_lvl 0	3
AM6_DEV_USB3SS0	151	i03_lvl 0	4
AM6_DEV_USB3SS0	151	i04_lvl 0	5
AM6_DEV_USB3SS0	151	i05_lvl 0	6
AM6_DEV_USB3SS0	151	i06_lvl 0	7
AM6_DEV_USB3SS0	151	i07_lvl 0	8
AM6_DEV_USB3SS0	151	i08_lvl 0	9
AM6_DEV_USB3SS0	151	i09_lvl 0	10
AM6_DEV_USB3SS0	151	i10_lvl 0	11
AM6_DEV_USB3SS0	151	i11_lvl 0	12
AM6_DEV_USB3SS0	151	i12_lvl 0	13
AM6_DEV_USB3SS0	151	i13_lvl 0	14
AM6_DEV_USB3SS0	151	i14_lvl 0	15
AM6_DEV_USB3SS0	151	i15_lvl 0	16
AM6_DEV_USB3SS0	151	misc_lvl 0	17
AM6_DEV_USB3SS0	151	otg_lvl 0	18
AM6_DEV_USB3SS0	151	pme_gen_lvl 0	19
AM6_DEV_USB3SS1	152	bc_lvl 0	0
AM6_DEV_USB3SS1	152	i00_lvl 0	1
AM6_DEV_USB3SS1	152	i01_lvl 0	2
AM6_DEV_USB3SS1	152	i02_lvl 0	3
AM6_DEV_USB3SS1	152	i03_lvl 0	4
AM6_DEV_USB3SS1	152	i04_lvl 0	5
AM6_DEV_USB3SS1	152	i05_lvl 0	6
AM6_DEV_USB3SS1	152	i06_lvl 0	7
AM6_DEV_USB3SS1	152	i07_lvl 0	8
AM6_DEV_USB3SS1	152	i08_lvl 0	9
AM6_DEV_USB3SS1	152	i09_lvl 0	10
AM6_DEV_USB3SS1	152	i10_lvl 0	11
AM6_DEV_USB3SS1	152	i11_lvl 0	12
AM6_DEV_USB3SS1	152	i12_lvl 0	13
AM6_DEV_USB3SS1	152	i13_lvl 0	14
AM6_DEV_USB3SS1	152	i14_lvl 0	15
AM6_DEV_USB3SS1	152	i15_lvl 0	16
AM6_DEV_USB3SS1	152	misc_lvl 0	17
AM6_DEV_USB3SS1	152	otg_lvl 0	18
AM6_DEV_USB3SS1	152	pme_gen_lvl 0	19
AM6_DEV_WKUP_GPIO0	59	gpio 0 to 55	0 to 55
AM6_DEV_WKUP_GPIO0	59	gpio_bank 0 to 3	56 to 59
AM6_DEV_MCU_NAVSS0_MCRC0	193	dma_event_intr 0 to 3	0 to 3
AM6_DEV_MCU_NAVSS0_MCRC0	193	intaggr_vintr_pend 0	4
AM6_DEV_NAVSS0_CPTS0	163	event_pend_intr 0	0
AM6_DEV_NAVSS0_MAILBOX0_CLUSTER0	164	pend_intr 0 to 3	0 to 3
AM6_DEV_NAVSS0_MAILBOX0_CLUSTER1	165	pend_intr 0 to 3	0 to 3
AM6_DEV_NAVSS0_MAILBOX0_CLUSTER10	174	pend_intr 0 to 3	0 to 3
AM6_DEV_NAVSS0_MAILBOX0_CLUSTER11	175	pend_intr 0 to 3	0 to 3
AM6_DEV_NAVSS0_MAILBOX0_CLUSTER2	166	pend_intr 0 to 3	0 to 3
AM6_DEV_NAVSS0_MAILBOX0_CLUSTER3	167	pend_intr 0 to 3	0 to 3
AM6_DEV_NAVSS0_MAILBOX0_CLUSTER4	168	pend_intr 0 to 3	0 to 3
AM6_DEV_NAVSS0_MAILBOX0_CLUSTER5	169	pend_intr 0 to 3	0 to 3
AM6_DEV_NAVSS0_MAILBOX0_CLUSTER6	170	pend_intr 0 to 3	0 to 3
AM6_DEV_NAVSS0_MAILBOX0_CLUSTER7	171	pend_intr 0 to 3	0 to 3
AM6_DEV_NAVSS0_MAILBOX0_CLUSTER8	172	pend_intr 0 to 3	0 to 3
AM6_DEV_NAVSS0_MAILBOX0_CLUSTER9	173	pend_intr 0 to 3	0 to 3
AM6_DEV_NAVSS0_MCRC0	176	dma_event_intr 0 to 3	0 to 3
AM6_DEV_NAVSS0_MCRC0	176	intaggr_vintr_pend 0	4
AM6_DEV_NAVSS0_PVU0	177	exp_intr 0	0