am6 Peripheral Interrupt Destination Descriptions¶
Introduction¶
This chapter provides information on processor interrupt destination IDs that are permitted in the am6 SoC. The interrupt destination IDs represent inputs to SoC processor interrupt controllers or the processors themselves. The System Firmware interrupt management TISCI message APIs take interrupt destination IDs as input to set and release interrupt routes between source peripherals and destination processors.
Warning
Resources marked as reserved for use by DMSC cannot be assigned to a host within the RM Board Configuration resource assignment array. The RM Board Configuration is rejected if an overlap with a reserved resource is detected.
Interrupt Destination IDs¶
| Destination Device Name | Destination Device ID | Interrupt Destination Description | Interrupt Destination Input Index |
|---|---|---|---|
| AM6_DEV_MCU_ARMSS0_CPU1 (Reserved by System Firmware) | 245 | AM6_DEV_MCU_ARMSS0_CPU1 inputs from mcu_navss0_intr_router_0 | 64 to 67 |
| AM6_DEV_MCU_ARMSS0_CPU1 | 245 | AM6_DEV_MCU_ARMSS0_CPU1 inputs from mcu_navss0_intr_router_0 | 68 to 95 |
| AM6_DEV_MCU_ARMSS0_CPU1 | 245 | AM6_DEV_MCU_ARMSS0_CPU1 inputs from WKUP_GPIOMUX_INTRTR0 | 124 to 139 |
| AM6_DEV_MCU_ARMSS0_CPU1 | 245 | AM6_DEV_MCU_ARMSS0_CPU1 inputs from MAIN2MCU_LVL_INTRTR0 | 160 to 223 |
| AM6_DEV_MCU_ARMSS0_CPU1 | 245 | AM6_DEV_MCU_ARMSS0_CPU1 inputs from MAIN2MCU_PLS_INTRTR0 | 224 to 271 |
| AM6_DEV_GIC0 (Reserved by System Firmware) | 56 | AM6_DEV_GIC0 inputs from navss0_intr_router_0 | 64 to 79 |
| AM6_DEV_GIC0 | 56 | AM6_DEV_GIC0 inputs from navss0_intr_router_0 | 80 to 127 |
| AM6_DEV_GIC0 | 56 | AM6_DEV_GIC0 inputs from GPIOMUX_INTRTR0 | 392 to 423 |
| AM6_DEV_GIC0 | 56 | AM6_DEV_GIC0 inputs from navss0_intr_router_0 | 448 to 503 |
| AM6_DEV_GIC0 | 56 | AM6_DEV_GIC0 inputs from CMPEVENT_INTRTR0 | 544 to 559 |
| AM6_DEV_GIC0 | 56 | AM6_DEV_GIC0 inputs from WKUP_GPIOMUX_INTRTR0 | 712 to 727 |
| AM6_DEV_MCU_ARMSS0_CPU0 (Reserved by System Firmware) | 159 | AM6_DEV_MCU_ARMSS0_CPU0 inputs from mcu_navss0_intr_router_0 | 64 to 67 |
| AM6_DEV_MCU_ARMSS0_CPU0 | 159 | AM6_DEV_MCU_ARMSS0_CPU0 inputs from mcu_navss0_intr_router_0 | 68 to 95 |
| AM6_DEV_MCU_ARMSS0_CPU0 | 159 | AM6_DEV_MCU_ARMSS0_CPU0 inputs from WKUP_GPIOMUX_INTRTR0 | 124 to 139 |
| AM6_DEV_MCU_ARMSS0_CPU0 | 159 | AM6_DEV_MCU_ARMSS0_CPU0 inputs from MAIN2MCU_LVL_INTRTR0 | 160 to 223 |
| AM6_DEV_MCU_ARMSS0_CPU0 | 159 | AM6_DEV_MCU_ARMSS0_CPU0 inputs from MAIN2MCU_PLS_INTRTR0 | 224 to 271 |
| AM6_DEV_NAVSS0 | 118 | AM6_DEV_NAVSS0 inputs from TIMESYNC_INTRTR0 | 0 |
| AM6_DEV_NAVSS0 | 118 | AM6_DEV_NAVSS0 inputs from TIMESYNC_INTRTR0 | 1 |
| AM6_DEV_NAVSS0 | 118 | AM6_DEV_NAVSS0 inputs from TIMESYNC_INTRTR0 | 2 |
| AM6_DEV_NAVSS0 | 118 | AM6_DEV_NAVSS0 inputs from TIMESYNC_INTRTR0 | 3 |
| AM6_DEV_NAVSS0 | 118 | AM6_DEV_NAVSS0 inputs from TIMESYNC_INTRTR0 | 4 |
| AM6_DEV_NAVSS0 | 118 | AM6_DEV_NAVSS0 inputs from TIMESYNC_INTRTR0 | 5 |
| AM6_DEV_NAVSS0 | 118 | AM6_DEV_NAVSS0 inputs from TIMESYNC_INTRTR0 | 6 |
| AM6_DEV_ESM0 | 52 | AM6_DEV_ESM0 inputs from GPIOMUX_INTRTR0 | 248 to 255 |
| AM6_DEV_ESM0 | 52 | AM6_DEV_ESM0 inputs from GPIOMUX_INTRTR0 | 256 to 263 |
| AM6_DEV_ESM0 | 52 | AM6_DEV_ESM0 inputs from GPIOMUX_INTRTR0 | 264 to 271 |
| AM6_DEV_PDMA1 | 124 | AM6_DEV_PDMA1 inputs from TIMESYNC_INTRTR0 | 0 to 7 |
| AM6_DEV_PDMA1 | 124 | AM6_DEV_PDMA1 inputs from CMPEVENT_INTRTR0 | 8 to 15 |
| AM6_DEV_PRU_ICSSG0 | 62 | AM6_DEV_PRU_ICSSG0 inputs from TIMESYNC_INTRTR0 | 0 |
| AM6_DEV_PRU_ICSSG0 | 62 | AM6_DEV_PRU_ICSSG0 inputs from TIMESYNC_INTRTR0 | 1 |
| AM6_DEV_PRU_ICSSG0 | 62 | AM6_DEV_PRU_ICSSG0 inputs from TIMESYNC_INTRTR0 | 2 |
| AM6_DEV_PRU_ICSSG0 | 62 | AM6_DEV_PRU_ICSSG0 inputs from TIMESYNC_INTRTR0 | 3 |
| AM6_DEV_PRU_ICSSG0 | 62 | AM6_DEV_PRU_ICSSG0 inputs from GPIOMUX_INTRTR0 | 4 to 9 |
| AM6_DEV_PRU_ICSSG0 | 62 | AM6_DEV_PRU_ICSSG0 inputs from GPIOMUX_INTRTR0 | 10 to 15 |
| AM6_DEV_PRU_ICSSG0 | 62 | AM6_DEV_PRU_ICSSG0 inputs from navss0_intr_router_0 | 46 to 53 |
| AM6_DEV_PRU_ICSSG0 | 62 | AM6_DEV_PRU_ICSSG0 inputs from GPIOMUX_INTRTR0 | 88 to 95 |
| AM6_DEV_MCU_CPSW0 | 5 | AM6_DEV_MCU_CPSW0 inputs from TIMESYNC_INTRTR0 | 0 |
| AM6_DEV_PRU_ICSSG2 | 64 | AM6_DEV_PRU_ICSSG2 inputs from TIMESYNC_INTRTR0 | 0 |
| AM6_DEV_PRU_ICSSG2 | 64 | AM6_DEV_PRU_ICSSG2 inputs from TIMESYNC_INTRTR0 | 1 |
| AM6_DEV_PRU_ICSSG2 | 64 | AM6_DEV_PRU_ICSSG2 inputs from TIMESYNC_INTRTR0 | 2 |
| AM6_DEV_PRU_ICSSG2 | 64 | AM6_DEV_PRU_ICSSG2 inputs from TIMESYNC_INTRTR0 | 3 |
| AM6_DEV_PRU_ICSSG2 | 64 | AM6_DEV_PRU_ICSSG2 inputs from GPIOMUX_INTRTR0 | 4 to 9 |
| AM6_DEV_PRU_ICSSG2 | 64 | AM6_DEV_PRU_ICSSG2 inputs from GPIOMUX_INTRTR0 | 10 to 15 |
| AM6_DEV_PRU_ICSSG2 | 64 | AM6_DEV_PRU_ICSSG2 inputs from navss0_intr_router_0 | 46 to 53 |
| AM6_DEV_PRU_ICSSG2 | 64 | AM6_DEV_PRU_ICSSG2 inputs from GPIOMUX_INTRTR0 | 88 to 95 |
| AM6_DEV_WKUP_ESM0 | 54 | AM6_DEV_WKUP_ESM0 inputs from WKUP_GPIOMUX_INTRTR0 | 88 to 95 |
| AM6_DEV_WKUP_ESM0 | 54 | AM6_DEV_WKUP_ESM0 inputs from WKUP_GPIOMUX_INTRTR0 | 96 to 103 |
| AM6_DEV_WKUP_ESM0 | 54 | AM6_DEV_WKUP_ESM0 inputs from WKUP_GPIOMUX_INTRTR0 | 104 to 111 |
| AM6_DEV_WKUP_DMSC0_CORTEX_M3_0 | 161 | AM6_DEV_WKUP_DMSC0_CORTEX_M3_0 inputs from WKUP_GPIOMUX_INTRTR0 | 184 to 195 |
| AM6_DEV_PRU_ICSSG1 | 63 | AM6_DEV_PRU_ICSSG1 inputs from TIMESYNC_INTRTR0 | 0 |
| AM6_DEV_PRU_ICSSG1 | 63 | AM6_DEV_PRU_ICSSG1 inputs from TIMESYNC_INTRTR0 | 1 |
| AM6_DEV_PRU_ICSSG1 | 63 | AM6_DEV_PRU_ICSSG1 inputs from TIMESYNC_INTRTR0 | 2 |
| AM6_DEV_PRU_ICSSG1 | 63 | AM6_DEV_PRU_ICSSG1 inputs from TIMESYNC_INTRTR0 | 3 |
| AM6_DEV_PRU_ICSSG1 | 63 | AM6_DEV_PRU_ICSSG1 inputs from GPIOMUX_INTRTR0 | 4 to 9 |
| AM6_DEV_PRU_ICSSG1 | 63 | AM6_DEV_PRU_ICSSG1 inputs from GPIOMUX_INTRTR0 | 10 to 15 |
| AM6_DEV_PRU_ICSSG1 | 63 | AM6_DEV_PRU_ICSSG1 inputs from navss0_intr_router_0 | 46 to 53 |
| AM6_DEV_PRU_ICSSG1 | 63 | AM6_DEV_PRU_ICSSG1 inputs from GPIOMUX_INTRTR0 | 88 to 95 |