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Macros | |
#define | ONEWIRE_O_CS 0x00000000 |
#define | ONEWIRE_O_TIM 0x00000004 |
#define | ONEWIRE_O_DATW 0x00000008 |
#define | ONEWIRE_O_DATR 0x0000000C |
#define | ONEWIRE_O_IM 0x00000100 |
#define | ONEWIRE_O_RIS 0x00000104 |
#define | ONEWIRE_O_MIS 0x00000108 |
#define | ONEWIRE_O_ICR 0x0000010C |
#define | ONEWIRE_O_DMA 0x00000120 |
#define | ONEWIRE_O_PP 0x00000FC0 |
#define | ONEWIRE_CS_USEALT 0x80000000 |
#define | ONEWIRE_CS_ALTP 0x40000000 |
#define | ONEWIRE_CS_BSIZE_M 0x00070000 |
#define | ONEWIRE_CS_BSIZE_8 0x00000000 |
#define | ONEWIRE_CS_BSIZE_1 0x00010000 |
#define | ONEWIRE_CS_BSIZE_2 0x00020000 |
#define | ONEWIRE_CS_BSIZE_3 0x00030000 |
#define | ONEWIRE_CS_BSIZE_4 0x00040000 |
#define | ONEWIRE_CS_BSIZE_5 0x00050000 |
#define | ONEWIRE_CS_BSIZE_6 0x00060000 |
#define | ONEWIRE_CS_BSIZE_7 0x00070000 |
#define | ONEWIRE_CS_STUCK 0x00000400 |
#define | ONEWIRE_CS_NOATR 0x00000200 |
#define | ONEWIRE_CS_BUSY 0x00000100 |
#define | ONEWIRE_CS_SKATR 0x00000080 |
#define | ONEWIRE_CS_LSAM 0x00000040 |
#define | ONEWIRE_CS_ODRV 0x00000020 |
#define | ONEWIRE_CS_SZ_M 0x00000018 |
#define | ONEWIRE_CS_OP_M 0x00000006 |
#define | ONEWIRE_CS_OP_NONE 0x00000000 |
#define | ONEWIRE_CS_OP_RD 0x00000002 |
#define | ONEWIRE_CS_OP_WR 0x00000004 |
#define | ONEWIRE_CS_OP_WRRD 0x00000006 |
#define | ONEWIRE_CS_RST 0x00000001 |
#define | ONEWIRE_CS_SZ_S 3 |
#define | ONEWIRE_TIM_W1TIM_M 0xF0000000 |
#define | ONEWIRE_TIM_W0TIM_M 0x0F800000 |
#define | ONEWIRE_TIM_W0REST_M 0x00780000 |
#define | ONEWIRE_TIM_W1SAM_M 0x00078000 |
#define | ONEWIRE_TIM_ATRSAM_M 0x00007800 |
#define | ONEWIRE_TIM_ATRTIM_M 0x000007C0 |
#define | ONEWIRE_TIM_RSTTIM_M 0x0000003F |
#define | ONEWIRE_TIM_W1TIM_S 28 |
#define | ONEWIRE_TIM_W0TIM_S 23 |
#define | ONEWIRE_TIM_W0REST_S 19 |
#define | ONEWIRE_TIM_W1SAM_S 15 |
#define | ONEWIRE_TIM_ATRSAM_S 11 |
#define | ONEWIRE_TIM_ATRTIM_S 6 |
#define | ONEWIRE_TIM_RSTTIM_S 0 |
#define | ONEWIRE_DATW_B3_M 0xFF000000 |
#define | ONEWIRE_DATW_B2_M 0x00FF0000 |
#define | ONEWIRE_DATW_B1_M 0x0000FF00 |
#define | ONEWIRE_DATW_B0_M 0x000000FF |
#define | ONEWIRE_DATW_B3_S 24 |
#define | ONEWIRE_DATW_B2_S 16 |
#define | ONEWIRE_DATW_B1_S 8 |
#define | ONEWIRE_DATW_B0_S 0 |
#define | ONEWIRE_DATR_B3_M 0xFF000000 |
#define | ONEWIRE_DATR_B2_M 0x00FF0000 |
#define | ONEWIRE_DATR_B1_M 0x0000FF00 |
#define | ONEWIRE_DATR_B0_M 0x000000FF |
#define | ONEWIRE_DATR_B3_S 24 |
#define | ONEWIRE_DATR_B2_S 16 |
#define | ONEWIRE_DATR_B1_S 8 |
#define | ONEWIRE_DATR_B0_S 0 |
#define | ONEWIRE_IM_DMA 0x00000010 |
#define | ONEWIRE_IM_STUCK 0x00000008 |
#define | ONEWIRE_IM_NOATR 0x00000004 |
#define | ONEWIRE_IM_OPC 0x00000002 |
#define | ONEWIRE_IM_RST 0x00000001 |
#define | ONEWIRE_RIS_DMA 0x00000010 |
#define | ONEWIRE_RIS_STUCK 0x00000008 |
#define | ONEWIRE_RIS_NOATR 0x00000004 |
#define | ONEWIRE_RIS_OPC 0x00000002 |
#define | ONEWIRE_RIS_RST 0x00000001 |
#define | ONEWIRE_MIS_DMA 0x00000010 |
#define | ONEWIRE_MIS_STUCK 0x00000008 |
#define | ONEWIRE_MIS_NOATR 0x00000004 |
#define | ONEWIRE_MIS_OPC 0x00000002 |
#define | ONEWIRE_MIS_RST 0x00000001 |
#define | ONEWIRE_ICR_DMA 0x00000010 |
#define | ONEWIRE_ICR_STUCK 0x00000008 |
#define | ONEWIRE_ICR_NOATR 0x00000004 |
#define | ONEWIRE_ICR_OPC 0x00000002 |
#define | ONEWIRE_ICR_RST 0x00000001 |
#define | ONEWIRE_DMA_SG 0x00000008 |
#define | ONEWIRE_DMA_DMAOP_M 0x00000006 |
#define | ONEWIRE_DMA_DMAOP_DIS 0x00000000 |
#define | ONEWIRE_DMA_DMAOP_RDSNG 0x00000002 |
#define | ONEWIRE_DMA_DMAOP_WRMUL 0x00000004 |
#define | ONEWIRE_DMA_DMAOP_RDMUL 0x00000006 |
#define | ONEWIRE_DMA_RST 0x00000001 |
#define | ONEWIRE_PP_DMAP 0x00000010 |
#define | ONEWIRE_PP_CNT_M 0x00000003 |
#define | ONEWIRE_PP_CNT_S 0 |
#define ONEWIRE_O_CS 0x00000000 |
#define ONEWIRE_O_TIM 0x00000004 |
#define ONEWIRE_O_DATW 0x00000008 |
Referenced by OneWireDMAEnable(), and OneWireTransaction().
#define ONEWIRE_O_DATR 0x0000000C |
Referenced by OneWireDataGet(), and OneWireDataGetNonBlocking().
#define ONEWIRE_O_IM 0x00000100 |
Referenced by OneWireIntDisable(), and OneWireIntEnable().
#define ONEWIRE_O_RIS 0x00000104 |
Referenced by OneWireIntStatus().
#define ONEWIRE_O_MIS 0x00000108 |
Referenced by OneWireIntStatus().
#define ONEWIRE_O_ICR 0x0000010C |
Referenced by OneWireIntClear().
#define ONEWIRE_O_DMA 0x00000120 |
Referenced by OneWireDMADisable(), and OneWireDMAEnable().
#define ONEWIRE_O_PP 0x00000FC0 |
#define ONEWIRE_CS_USEALT 0x80000000 |
#define ONEWIRE_CS_ALTP 0x40000000 |
#define ONEWIRE_CS_BSIZE_M 0x00070000 |
#define ONEWIRE_CS_BSIZE_8 0x00000000 |
#define ONEWIRE_CS_BSIZE_1 0x00010000 |
#define ONEWIRE_CS_BSIZE_2 0x00020000 |
#define ONEWIRE_CS_BSIZE_3 0x00030000 |
#define ONEWIRE_CS_BSIZE_4 0x00040000 |
#define ONEWIRE_CS_BSIZE_5 0x00050000 |
#define ONEWIRE_CS_BSIZE_6 0x00060000 |
#define ONEWIRE_CS_BSIZE_7 0x00070000 |
#define ONEWIRE_CS_STUCK 0x00000400 |
Referenced by OneWireBusStatus().
#define ONEWIRE_CS_NOATR 0x00000200 |
Referenced by OneWireBusStatus().
#define ONEWIRE_CS_BUSY 0x00000100 |
Referenced by OneWireBusStatus(), OneWireDataGet(), and OneWireDataGetNonBlocking().
#define ONEWIRE_CS_SKATR 0x00000080 |
#define ONEWIRE_CS_LSAM 0x00000040 |
#define ONEWIRE_CS_ODRV 0x00000020 |
#define ONEWIRE_CS_SZ_M 0x00000018 |
#define ONEWIRE_CS_OP_M 0x00000006 |
#define ONEWIRE_CS_OP_NONE 0x00000000 |
#define ONEWIRE_CS_OP_RD 0x00000002 |
Referenced by OneWireTransaction().
#define ONEWIRE_CS_OP_WR 0x00000004 |
Referenced by OneWireTransaction().
#define ONEWIRE_CS_OP_WRRD 0x00000006 |
#define ONEWIRE_CS_RST 0x00000001 |
Referenced by OneWireBusReset().
#define ONEWIRE_CS_SZ_S 3 |
#define ONEWIRE_TIM_W1TIM_M 0xF0000000 |
#define ONEWIRE_TIM_W0TIM_M 0x0F800000 |
#define ONEWIRE_TIM_W0REST_M 0x00780000 |
#define ONEWIRE_TIM_W1SAM_M 0x00078000 |
#define ONEWIRE_TIM_ATRSAM_M 0x00007800 |
#define ONEWIRE_TIM_ATRTIM_M 0x000007C0 |
#define ONEWIRE_TIM_RSTTIM_M 0x0000003F |
#define ONEWIRE_TIM_W1TIM_S 28 |
#define ONEWIRE_TIM_W0TIM_S 23 |
#define ONEWIRE_TIM_W0REST_S 19 |
#define ONEWIRE_TIM_W1SAM_S 15 |
#define ONEWIRE_TIM_ATRSAM_S 11 |
#define ONEWIRE_TIM_ATRTIM_S 6 |
#define ONEWIRE_TIM_RSTTIM_S 0 |
#define ONEWIRE_DATW_B3_M 0xFF000000 |
#define ONEWIRE_DATW_B2_M 0x00FF0000 |
#define ONEWIRE_DATW_B1_M 0x0000FF00 |
#define ONEWIRE_DATW_B0_M 0x000000FF |
#define ONEWIRE_DATW_B3_S 24 |
#define ONEWIRE_DATW_B2_S 16 |
#define ONEWIRE_DATW_B1_S 8 |
#define ONEWIRE_DATW_B0_S 0 |
#define ONEWIRE_DATR_B3_M 0xFF000000 |
#define ONEWIRE_DATR_B2_M 0x00FF0000 |
#define ONEWIRE_DATR_B1_M 0x0000FF00 |
#define ONEWIRE_DATR_B0_M 0x000000FF |
#define ONEWIRE_DATR_B3_S 24 |
#define ONEWIRE_DATR_B2_S 16 |
#define ONEWIRE_DATR_B1_S 8 |
#define ONEWIRE_DATR_B0_S 0 |
#define ONEWIRE_IM_DMA 0x00000010 |
Referenced by OneWireIntClear(), OneWireIntDisable(), and OneWireIntEnable().
#define ONEWIRE_IM_STUCK 0x00000008 |
Referenced by OneWireIntClear(), OneWireIntDisable(), and OneWireIntEnable().
#define ONEWIRE_IM_NOATR 0x00000004 |
Referenced by OneWireIntClear(), OneWireIntDisable(), and OneWireIntEnable().
#define ONEWIRE_IM_OPC 0x00000002 |
Referenced by OneWireIntClear(), OneWireIntDisable(), and OneWireIntEnable().
#define ONEWIRE_IM_RST 0x00000001 |
Referenced by OneWireIntClear(), OneWireIntDisable(), and OneWireIntEnable().
#define ONEWIRE_RIS_DMA 0x00000010 |
#define ONEWIRE_RIS_STUCK 0x00000008 |
#define ONEWIRE_RIS_NOATR 0x00000004 |
#define ONEWIRE_RIS_OPC 0x00000002 |
#define ONEWIRE_RIS_RST 0x00000001 |
#define ONEWIRE_MIS_DMA 0x00000010 |
#define ONEWIRE_MIS_STUCK 0x00000008 |
#define ONEWIRE_MIS_NOATR 0x00000004 |
#define ONEWIRE_MIS_OPC 0x00000002 |
#define ONEWIRE_MIS_RST 0x00000001 |
#define ONEWIRE_ICR_DMA 0x00000010 |
#define ONEWIRE_ICR_STUCK 0x00000008 |
#define ONEWIRE_ICR_NOATR 0x00000004 |
#define ONEWIRE_ICR_OPC 0x00000002 |
#define ONEWIRE_ICR_RST 0x00000001 |
#define ONEWIRE_DMA_SG 0x00000008 |
Referenced by OneWireDMAEnable().
#define ONEWIRE_DMA_DMAOP_M 0x00000006 |
#define ONEWIRE_DMA_DMAOP_DIS 0x00000000 |
#define ONEWIRE_DMA_DMAOP_RDSNG 0x00000002 |
Referenced by OneWireDMAEnable().
#define ONEWIRE_DMA_DMAOP_WRMUL 0x00000004 |
#define ONEWIRE_DMA_DMAOP_RDMUL 0x00000006 |
Referenced by OneWireDMAEnable().
#define ONEWIRE_DMA_RST 0x00000001 |
#define ONEWIRE_PP_DMAP 0x00000010 |
#define ONEWIRE_PP_CNT_M 0x00000003 |
#define ONEWIRE_PP_CNT_S 0 |