Macros
hw_emac.h File Reference

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Macros

#define EMAC_O_CFG   0x00000000
 
#define EMAC_O_FRAMEFLTR   0x00000004
 
#define EMAC_O_HASHTBLH   0x00000008
 
#define EMAC_O_HASHTBLL   0x0000000C
 
#define EMAC_O_MIIADDR   0x00000010
 
#define EMAC_O_MIIDATA   0x00000014
 
#define EMAC_O_FLOWCTL   0x00000018
 
#define EMAC_O_VLANTG   0x0000001C
 
#define EMAC_O_STATUS   0x00000024
 
#define EMAC_O_RWUFF   0x00000028
 
#define EMAC_O_PMTCTLSTAT   0x0000002C
 
#define EMAC_O_LPICTLSTAT   0x00000030
 
#define EMAC_O_LPITIMERCTL   0x00000034
 
#define EMAC_O_RIS   0x00000038
 
#define EMAC_O_IM   0x0000003C
 
#define EMAC_O_ADDR0H   0x00000040
 
#define EMAC_O_ADDR0L   0x00000044
 
#define EMAC_O_ADDR1H   0x00000048
 
#define EMAC_O_ADDR1L   0x0000004C
 
#define EMAC_O_ADDR2H   0x00000050
 
#define EMAC_O_ADDR2L   0x00000054
 
#define EMAC_O_ADDR3H   0x00000058
 
#define EMAC_O_ADDR3L   0x0000005C
 
#define EMAC_O_WDOGTO   0x000000DC
 
#define EMAC_O_MMCCTRL   0x00000100
 
#define EMAC_O_MMCRXRIS   0x00000104
 
#define EMAC_O_MMCTXRIS   0x00000108
 
#define EMAC_O_MMCRXIM   0x0000010C
 
#define EMAC_O_MMCTXIM   0x00000110
 
#define EMAC_O_TXCNTGB   0x00000118
 
#define EMAC_O_TXCNTSCOL   0x0000014C
 
#define EMAC_O_TXCNTMCOL   0x00000150
 
#define EMAC_O_TXOCTCNTG   0x00000164
 
#define EMAC_O_RXCNTGB   0x00000180
 
#define EMAC_O_RXCNTCRCERR   0x00000194
 
#define EMAC_O_RXCNTALGNERR   0x00000198
 
#define EMAC_O_RXCNTGUNI   0x000001C4
 
#define EMAC_O_VLNINCREP   0x00000584
 
#define EMAC_O_VLANHASH   0x00000588
 
#define EMAC_O_TIMSTCTRL   0x00000700
 
#define EMAC_O_SUBSECINC   0x00000704
 
#define EMAC_O_TIMSEC   0x00000708
 
#define EMAC_O_TIMNANO   0x0000070C
 
#define EMAC_O_TIMSECU   0x00000710
 
#define EMAC_O_TIMNANOU   0x00000714
 
#define EMAC_O_TIMADD   0x00000718
 
#define EMAC_O_TARGSEC   0x0000071C
 
#define EMAC_O_TARGNANO   0x00000720
 
#define EMAC_O_HWORDSEC   0x00000724
 
#define EMAC_O_TIMSTAT   0x00000728
 
#define EMAC_O_PPSCTRL   0x0000072C
 
#define EMAC_O_PPS0INTVL   0x00000760
 
#define EMAC_O_PPS0WIDTH   0x00000764
 
#define EMAC_O_DMABUSMOD   0x00000C00
 
#define EMAC_O_TXPOLLD   0x00000C04
 
#define EMAC_O_RXPOLLD   0x00000C08
 
#define EMAC_O_RXDLADDR   0x00000C0C
 
#define EMAC_O_TXDLADDR   0x00000C10
 
#define EMAC_O_DMARIS   0x00000C14
 
#define EMAC_O_DMAOPMODE   0x00000C18
 
#define EMAC_O_DMAIM   0x00000C1C
 
#define EMAC_O_MFBOC   0x00000C20
 
#define EMAC_O_RXINTWDT   0x00000C24
 
#define EMAC_O_HOSTXDESC   0x00000C48
 
#define EMAC_O_HOSRXDESC   0x00000C4C
 
#define EMAC_O_HOSTXBA   0x00000C50
 
#define EMAC_O_HOSRXBA   0x00000C54
 
#define EMAC_O_PP   0x00000FC0
 
#define EMAC_O_PC   0x00000FC4
 
#define EMAC_O_CC   0x00000FC8
 
#define EMAC_O_EPHYRIS   0x00000FD0
 
#define EMAC_O_EPHYIM   0x00000FD4
 
#define EMAC_O_EPHYMISC   0x00000FD8
 
#define EMAC_CFG_TWOKPEN   0x08000000
 
#define EMAC_CFG_CST   0x02000000
 
#define EMAC_CFG_WDDIS   0x00800000
 
#define EMAC_CFG_JD   0x00400000
 
#define EMAC_CFG_JFEN   0x00100000
 
#define EMAC_CFG_IFG_M   0x000E0000
 
#define EMAC_CFG_IFG_96   0x00000000
 
#define EMAC_CFG_IFG_88   0x00020000
 
#define EMAC_CFG_IFG_80   0x00040000
 
#define EMAC_CFG_IFG_72   0x00060000
 
#define EMAC_CFG_IFG_64   0x00080000
 
#define EMAC_CFG_IFG_56   0x000A0000
 
#define EMAC_CFG_IFG_48   0x000C0000
 
#define EMAC_CFG_IFG_40   0x000E0000
 
#define EMAC_CFG_DISCRS   0x00010000
 
#define EMAC_CFG_PS   0x00008000
 
#define EMAC_CFG_FES   0x00004000
 
#define EMAC_CFG_DRO   0x00002000
 
#define EMAC_CFG_LOOPBM   0x00001000
 
#define EMAC_CFG_DUPM   0x00000800
 
#define EMAC_CFG_IPC   0x00000400
 
#define EMAC_CFG_DR   0x00000200
 
#define EMAC_CFG_ACS   0x00000080
 
#define EMAC_CFG_BL_M   0x00000060
 
#define EMAC_CFG_BL_1024   0x00000000
 
#define EMAC_CFG_BL_256   0x00000020
 
#define EMAC_CFG_BL_8   0x00000040
 
#define EMAC_CFG_BL_2   0x00000060
 
#define EMAC_CFG_DC   0x00000010
 
#define EMAC_CFG_TE   0x00000008
 
#define EMAC_CFG_RE   0x00000004
 
#define EMAC_CFG_PRELEN_M   0x00000003
 
#define EMAC_CFG_PRELEN_7   0x00000000
 
#define EMAC_CFG_PRELEN_5   0x00000001
 
#define EMAC_CFG_PRELEN_3   0x00000002
 
#define EMAC_FRAMEFLTR_RA   0x80000000
 
#define EMAC_FRAMEFLTR_VTFE   0x00010000
 
#define EMAC_FRAMEFLTR_HPF   0x00000400
 
#define EMAC_FRAMEFLTR_SAF   0x00000200
 
#define EMAC_FRAMEFLTR_SAIF   0x00000100
 
#define EMAC_FRAMEFLTR_PCF_M   0x000000C0
 
#define EMAC_FRAMEFLTR_PCF_ALL   0x00000000
 
#define EMAC_FRAMEFLTR_PCF_PAUSE   0x00000040
 
#define EMAC_FRAMEFLTR_PCF_NONE   0x00000080
 
#define EMAC_FRAMEFLTR_PCF_ADDR   0x000000C0
 
#define EMAC_FRAMEFLTR_DBF   0x00000020
 
#define EMAC_FRAMEFLTR_PM   0x00000010
 
#define EMAC_FRAMEFLTR_DAIF   0x00000008
 
#define EMAC_FRAMEFLTR_HMC   0x00000004
 
#define EMAC_FRAMEFLTR_HUC   0x00000002
 
#define EMAC_FRAMEFLTR_PR   0x00000001
 
#define EMAC_HASHTBLH_HTH_M   0xFFFFFFFF
 
#define EMAC_HASHTBLH_HTH_S   0
 
#define EMAC_HASHTBLL_HTL_M   0xFFFFFFFF
 
#define EMAC_HASHTBLL_HTL_S   0
 
#define EMAC_MIIADDR_PLA_M   0x0000F800
 
#define EMAC_MIIADDR_MII_M   0x000007C0
 
#define EMAC_MIIADDR_CR_M   0x0000003C
 
#define EMAC_MIIADDR_CR_60_100   0x00000000
 
#define EMAC_MIIADDR_CR_100_150   0x00000004
 
#define EMAC_MIIADDR_CR_20_35   0x00000008
 
#define EMAC_MIIADDR_CR_35_60   0x0000000C
 
#define EMAC_MIIADDR_MIIW   0x00000002
 
#define EMAC_MIIADDR_MIIB   0x00000001
 
#define EMAC_MIIADDR_PLA_S   11
 
#define EMAC_MIIADDR_MII_S   6
 
#define EMAC_MIIDATA_DATA_M   0x0000FFFF
 
#define EMAC_MIIDATA_DATA_S   0
 
#define EMAC_FLOWCTL_PT_M   0xFFFF0000
 
#define EMAC_FLOWCTL_DZQP   0x00000080
 
#define EMAC_FLOWCTL_UP   0x00000008
 
#define EMAC_FLOWCTL_RFE   0x00000004
 
#define EMAC_FLOWCTL_TFE   0x00000002
 
#define EMAC_FLOWCTL_FCBBPA   0x00000001
 
#define EMAC_FLOWCTL_PT_S   16
 
#define EMAC_VLANTG_VTHM   0x00080000
 
#define EMAC_VLANTG_ESVL   0x00040000
 
#define EMAC_VLANTG_VTIM   0x00020000
 
#define EMAC_VLANTG_ETV   0x00010000
 
#define EMAC_VLANTG_VL_M   0x0000FFFF
 
#define EMAC_VLANTG_VL_S   0
 
#define EMAC_STATUS_TXFF   0x02000000
 
#define EMAC_STATUS_TXFE   0x01000000
 
#define EMAC_STATUS_TWC   0x00400000
 
#define EMAC_STATUS_TRC_M   0x00300000
 
#define EMAC_STATUS_TRC_IDLE   0x00000000
 
#define EMAC_STATUS_TRC_READ   0x00100000
 
#define EMAC_STATUS_TRC_WAIT   0x00200000
 
#define EMAC_STATUS_TRC_WRFLUSH   0x00300000
 
#define EMAC_STATUS_TXPAUSED   0x00080000
 
#define EMAC_STATUS_TFC_M   0x00060000
 
#define EMAC_STATUS_TFC_IDLE   0x00000000
 
#define EMAC_STATUS_TFC_STATUS   0x00020000
 
#define EMAC_STATUS_TFC_PAUSE   0x00040000
 
#define EMAC_STATUS_TFC_INPUT   0x00060000
 
#define EMAC_STATUS_TPE   0x00010000
 
#define EMAC_STATUS_RXF_M   0x00000300
 
#define EMAC_STATUS_RXF_EMPTY   0x00000000
 
#define EMAC_STATUS_RXF_BELOW   0x00000100
 
#define EMAC_STATUS_RXF_ABOVE   0x00000200
 
#define EMAC_STATUS_RXF_FULL   0x00000300
 
#define EMAC_STATUS_RRC_M   0x00000060
 
#define EMAC_STATUS_RRC_IDLE   0x00000000
 
#define EMAC_STATUS_RRC_STATUS   0x00000020
 
#define EMAC_STATUS_RRC_DATA   0x00000040
 
#define EMAC_STATUS_RRC_FLUSH   0x00000060
 
#define EMAC_STATUS_RWC   0x00000010
 
#define EMAC_STATUS_RFCFC_M   0x00000006
 
#define EMAC_STATUS_RPE   0x00000001
 
#define EMAC_STATUS_RFCFC_S   1
 
#define EMAC_RWUFF_WAKEUPFIL_M   0xFFFFFFFF
 
#define EMAC_RWUFF_WAKEUPFIL_S   0
 
#define EMAC_PMTCTLSTAT_WUPFRRST   0x80000000
 
#define EMAC_PMTCTLSTAT_RWKPTR_M   0x07000000
 
#define EMAC_PMTCTLSTAT_GLBLUCAST   0x00000200
 
#define EMAC_PMTCTLSTAT_WUPRX   0x00000040
 
#define EMAC_PMTCTLSTAT_MGKPRX   0x00000020
 
#define EMAC_PMTCTLSTAT_WUPFREN   0x00000004
 
#define EMAC_PMTCTLSTAT_MGKPKTEN   0x00000002
 
#define EMAC_PMTCTLSTAT_PWRDWN   0x00000001
 
#define EMAC_PMTCTLSTAT_RWKPTR_S   24
 
#define EMAC_LPICTLSTAT_LPITXA   0x00080000
 
#define EMAC_LPICTLSTAT_PLSEN   0x00040000
 
#define EMAC_LPICTLSTAT_PLS   0x00020000
 
#define EMAC_LPICTLSTAT_LPIEN   0x00010000
 
#define EMAC_LPICTLSTAT_RLPIST   0x00000200
 
#define EMAC_LPICTLSTAT_TLPIST   0x00000100
 
#define EMAC_LPICTLSTAT_RLPIEX   0x00000008
 
#define EMAC_LPICTLSTAT_RLPIEN   0x00000004
 
#define EMAC_LPICTLSTAT_TLPIEX   0x00000002
 
#define EMAC_LPICTLSTAT_TLPIEN   0x00000001
 
#define EMAC_LPITIMERCTL_LST_M   0x03FF0000
 
#define EMAC_LPITIMERCTL_LST_S   16
 
#define EMAC_LPITIMERCTL_TWT_M   0x0000FFFF
 
#define EMAC_LPITIMERCTL_TWT_S   0
 
#define EMAC_RIS_LPI   0x00000400
 
#define EMAC_RIS_TS   0x00000200
 
#define EMAC_RIS_MMCTX   0x00000040
 
#define EMAC_RIS_MMCRX   0x00000020
 
#define EMAC_RIS_MMC   0x00000010
 
#define EMAC_RIS_PMT   0x00000008
 
#define EMAC_IM_LPI   0x00000400
 
#define EMAC_IM_TSI   0x00000200
 
#define EMAC_IM_PMT   0x00000008
 
#define EMAC_ADDR0H_AE   0x80000000
 
#define EMAC_ADDR0H_ADDRHI_M   0x0000FFFF
 
#define EMAC_ADDR0H_ADDRHI_S   0
 
#define EMAC_ADDR0L_ADDRLO_M   0xFFFFFFFF
 
#define EMAC_ADDR0L_ADDRLO_S   0
 
#define EMAC_ADDR1H_AE   0x80000000
 
#define EMAC_ADDR1H_SA   0x40000000
 
#define EMAC_ADDR1H_MBC_M   0x3F000000
 
#define EMAC_ADDR1H_ADDRHI_M   0x0000FFFF
 
#define EMAC_ADDR1H_MBC_S   24
 
#define EMAC_ADDR1H_ADDRHI_S   0
 
#define EMAC_ADDR1L_ADDRLO_M   0xFFFFFFFF
 
#define EMAC_ADDR1L_ADDRLO_S   0
 
#define EMAC_ADDR2H_AE   0x80000000
 
#define EMAC_ADDR2H_SA   0x40000000
 
#define EMAC_ADDR2H_MBC_M   0x3F000000
 
#define EMAC_ADDR2H_ADDRHI_M   0x0000FFFF
 
#define EMAC_ADDR2H_MBC_S   24
 
#define EMAC_ADDR2H_ADDRHI_S   0
 
#define EMAC_ADDR2L_ADDRLO_M   0xFFFFFFFF
 
#define EMAC_ADDR2L_ADDRLO_S   0
 
#define EMAC_ADDR3H_AE   0x80000000
 
#define EMAC_ADDR3H_SA   0x40000000
 
#define EMAC_ADDR3H_MBC_M   0x3F000000
 
#define EMAC_ADDR3H_ADDRHI_M   0x0000FFFF
 
#define EMAC_ADDR3H_MBC_S   24
 
#define EMAC_ADDR3H_ADDRHI_S   0
 
#define EMAC_ADDR3L_ADDRLO_M   0xFFFFFFFF
 
#define EMAC_ADDR3L_ADDRLO_S   0
 
#define EMAC_WDOGTO_PWE   0x00010000
 
#define EMAC_WDOGTO_WTO_M   0x00003FFF
 
#define EMAC_WDOGTO_WTO_S   0
 
#define EMAC_MMCCTRL_UCDBC   0x00000100
 
#define EMAC_MMCCTRL_CNTPRSTLVL   0x00000020
 
#define EMAC_MMCCTRL_CNTPRST   0x00000010
 
#define EMAC_MMCCTRL_CNTFREEZ   0x00000008
 
#define EMAC_MMCCTRL_RSTONRD   0x00000004
 
#define EMAC_MMCCTRL_CNTSTPRO   0x00000002
 
#define EMAC_MMCCTRL_CNTRST   0x00000001
 
#define EMAC_MMCRXRIS_UCGF   0x00020000
 
#define EMAC_MMCRXRIS_ALGNERR   0x00000040
 
#define EMAC_MMCRXRIS_CRCERR   0x00000020
 
#define EMAC_MMCRXRIS_GBF   0x00000001
 
#define EMAC_MMCTXRIS_OCTCNT   0x00100000
 
#define EMAC_MMCTXRIS_MCOLLGF   0x00008000
 
#define EMAC_MMCTXRIS_SCOLLGF   0x00004000
 
#define EMAC_MMCTXRIS_GBF   0x00000002
 
#define EMAC_MMCRXIM_UCGF   0x00020000
 
#define EMAC_MMCRXIM_ALGNERR   0x00000040
 
#define EMAC_MMCRXIM_CRCERR   0x00000020
 
#define EMAC_MMCRXIM_GBF   0x00000001
 
#define EMAC_MMCTXIM_OCTCNT   0x00100000
 
#define EMAC_MMCTXIM_MCOLLGF   0x00008000
 
#define EMAC_MMCTXIM_SCOLLGF   0x00004000
 
#define EMAC_MMCTXIM_GBF   0x00000002
 
#define EMAC_TXCNTGB_TXFRMGB_M   0xFFFFFFFF
 
#define EMAC_TXCNTGB_TXFRMGB_S   0
 
#define EMAC_TXCNTSCOL_TXSNGLCOLG_M   0xFFFFFFFF
 
#define EMAC_TXCNTSCOL_TXSNGLCOLG_S   0
 
#define EMAC_TXCNTMCOL_TXMULTCOLG_M   0xFFFFFFFF
 
#define EMAC_TXCNTMCOL_TXMULTCOLG_S   0
 
#define EMAC_TXOCTCNTG_TXOCTG_M   0xFFFFFFFF
 
#define EMAC_TXOCTCNTG_TXOCTG_S   0
 
#define EMAC_RXCNTGB_RXFRMGB_M   0xFFFFFFFF
 
#define EMAC_RXCNTGB_RXFRMGB_S   0
 
#define EMAC_RXCNTCRCERR_RXCRCERR_M   0xFFFFFFFF
 
#define EMAC_RXCNTCRCERR_RXCRCERR_S   0
 
#define EMAC_RXCNTALGNERR_RXALGNERR_M   0xFFFFFFFF
 
#define EMAC_RXCNTALGNERR_RXALGNERR_S   0
 
#define EMAC_RXCNTGUNI_RXUCASTG_M   0xFFFFFFFF
 
#define EMAC_RXCNTGUNI_RXUCASTG_S   0
 
#define EMAC_VLNINCREP_CSVL   0x00080000
 
#define EMAC_VLNINCREP_VLP   0x00040000
 
#define EMAC_VLNINCREP_VLC_M   0x00030000
 
#define EMAC_VLNINCREP_VLC_NONE   0x00000000
 
#define EMAC_VLNINCREP_VLC_TAGDEL   0x00010000
 
#define EMAC_VLNINCREP_VLC_TAGINS   0x00020000
 
#define EMAC_VLNINCREP_VLC_TAGREP   0x00030000
 
#define EMAC_VLNINCREP_VLT_M   0x0000FFFF
 
#define EMAC_VLNINCREP_VLT_S   0
 
#define EMAC_VLANHASH_VLHT_M   0x0000FFFF
 
#define EMAC_VLANHASH_VLHT_S   0
 
#define EMAC_TIMSTCTRL_PTPFLTR   0x00040000
 
#define EMAC_TIMSTCTRL_SELPTP_M   0x00030000
 
#define EMAC_TIMSTCTRL_TSMAST   0x00008000
 
#define EMAC_TIMSTCTRL_TSEVNT   0x00004000
 
#define EMAC_TIMSTCTRL_PTPIPV4   0x00002000
 
#define EMAC_TIMSTCTRL_PTPIPV6   0x00001000
 
#define EMAC_TIMSTCTRL_PTPETH   0x00000800
 
#define EMAC_TIMSTCTRL_PTPVER2   0x00000400
 
#define EMAC_TIMSTCTRL_DGTLBIN   0x00000200
 
#define EMAC_TIMSTCTRL_ALLF   0x00000100
 
#define EMAC_TIMSTCTRL_ADDREGUP   0x00000020
 
#define EMAC_TIMSTCTRL_INTTRIG   0x00000010
 
#define EMAC_TIMSTCTRL_TSUPDT   0x00000008
 
#define EMAC_TIMSTCTRL_TSINIT   0x00000004
 
#define EMAC_TIMSTCTRL_TSFCUPDT   0x00000002
 
#define EMAC_TIMSTCTRL_TSEN   0x00000001
 
#define EMAC_TIMSTCTRL_SELPTP_S   16
 
#define EMAC_SUBSECINC_SSINC_M   0x000000FF
 
#define EMAC_SUBSECINC_SSINC_S   0
 
#define EMAC_TIMSEC_TSS_M   0xFFFFFFFF
 
#define EMAC_TIMSEC_TSS_S   0
 
#define EMAC_TIMNANO_TSSS_M   0x7FFFFFFF
 
#define EMAC_TIMNANO_TSSS_S   0
 
#define EMAC_TIMSECU_TSS_M   0xFFFFFFFF
 
#define EMAC_TIMSECU_TSS_S   0
 
#define EMAC_TIMNANOU_ADDSUB   0x80000000
 
#define EMAC_TIMNANOU_TSSS_M   0x7FFFFFFF
 
#define EMAC_TIMNANOU_TSSS_S   0
 
#define EMAC_TIMADD_TSAR_M   0xFFFFFFFF
 
#define EMAC_TIMADD_TSAR_S   0
 
#define EMAC_TARGSEC_TSTR_M   0xFFFFFFFF
 
#define EMAC_TARGSEC_TSTR_S   0
 
#define EMAC_TARGNANO_TRGTBUSY   0x80000000
 
#define EMAC_TARGNANO_TTSLO_M   0x7FFFFFFF
 
#define EMAC_TARGNANO_TTSLO_S   0
 
#define EMAC_HWORDSEC_TSHWR_M   0x0000FFFF
 
#define EMAC_HWORDSEC_TSHWR_S   0
 
#define EMAC_TIMSTAT_TSTARGT   0x00000002
 
#define EMAC_TIMSTAT_TSSOVF   0x00000001
 
#define EMAC_PPSCTRL_TRGMODS0_M   0x00000060
 
#define EMAC_PPSCTRL_TRGMODS0_INTONLY   0x00000000
 
#define EMAC_PPSCTRL_TRGMODS0_INTPPS0   0x00000040
 
#define EMAC_PPSCTRL_TRGMODS0_PPS0ONLY   0x00000060
 
#define EMAC_PPSCTRL_PPSEN0   0x00000010
 
#define EMAC_PPSCTRL_PPSCTRL_M   0x0000000F
 
#define EMAC_PPS0INTVL_PPS0INT_M   0xFFFFFFFF
 
#define EMAC_PPS0INTVL_PPS0INT_S   0
 
#define EMAC_PPS0WIDTH_M   0xFFFFFFFF
 
#define EMAC_PPS0WIDTH_S   0
 
#define EMAC_DMABUSMOD_RIB   0x80000000
 
#define EMAC_DMABUSMOD_TXPR   0x08000000
 
#define EMAC_DMABUSMOD_MB   0x04000000
 
#define EMAC_DMABUSMOD_AAL   0x02000000
 
#define EMAC_DMABUSMOD_8XPBL   0x01000000
 
#define EMAC_DMABUSMOD_USP   0x00800000
 
#define EMAC_DMABUSMOD_RPBL_M   0x007E0000
 
#define EMAC_DMABUSMOD_FB   0x00010000
 
#define EMAC_DMABUSMOD_PR_M   0x0000C000
 
#define EMAC_DMABUSMOD_PBL_M   0x00003F00
 
#define EMAC_DMABUSMOD_ATDS   0x00000080
 
#define EMAC_DMABUSMOD_DSL_M   0x0000007C
 
#define EMAC_DMABUSMOD_DA   0x00000002
 
#define EMAC_DMABUSMOD_SWR   0x00000001
 
#define EMAC_DMABUSMOD_RPBL_S   17
 
#define EMAC_DMABUSMOD_PR_S   14
 
#define EMAC_DMABUSMOD_PBL_S   8
 
#define EMAC_DMABUSMOD_DSL_S   2
 
#define EMAC_TXPOLLD_TPD_M   0xFFFFFFFF
 
#define EMAC_TXPOLLD_TPD_S   0
 
#define EMAC_RXPOLLD_RPD_M   0xFFFFFFFF
 
#define EMAC_RXPOLLD_RPD_S   0
 
#define EMAC_RXDLADDR_STRXLIST_M   0xFFFFFFFC
 
#define EMAC_RXDLADDR_STRXLIST_S   2
 
#define EMAC_TXDLADDR_TXDLADDR_M   0xFFFFFFFC
 
#define EMAC_TXDLADDR_TXDLADDR_S   2
 
#define EMAC_DMARIS_LPI   0x40000000
 
#define EMAC_DMARIS_TT   0x20000000
 
#define EMAC_DMARIS_PMT   0x10000000
 
#define EMAC_DMARIS_MMC   0x08000000
 
#define EMAC_DMARIS_AE_M   0x03800000
 
#define EMAC_DMARIS_AE_RXDMAWD   0x00000000
 
#define EMAC_DMARIS_AE_TXDMARD   0x01800000
 
#define EMAC_DMARIS_AE_RXDMADW   0x02000000
 
#define EMAC_DMARIS_AE_TXDMADW   0x02800000
 
#define EMAC_DMARIS_AE_RXDMADR   0x03000000
 
#define EMAC_DMARIS_AE_TXDMADR   0x03800000
 
#define EMAC_DMARIS_TS_M   0x00700000
 
#define EMAC_DMARIS_TS_STOP   0x00000000
 
#define EMAC_DMARIS_TS_RUNTXTD   0x00100000
 
#define EMAC_DMARIS_TS_STATUS   0x00200000
 
#define EMAC_DMARIS_TS_RUNTX   0x00300000
 
#define EMAC_DMARIS_TS_TSTAMP   0x00400000
 
#define EMAC_DMARIS_TS_SUSPEND   0x00600000
 
#define EMAC_DMARIS_TS_RUNCTD   0x00700000
 
#define EMAC_DMARIS_RS_M   0x000E0000
 
#define EMAC_DMARIS_RS_STOP   0x00000000
 
#define EMAC_DMARIS_RS_RUNRXTD   0x00020000
 
#define EMAC_DMARIS_RS_RUNRXD   0x00060000
 
#define EMAC_DMARIS_RS_SUSPEND   0x00080000
 
#define EMAC_DMARIS_RS_RUNCRD   0x000A0000
 
#define EMAC_DMARIS_RS_TSWS   0x000C0000
 
#define EMAC_DMARIS_RS_RUNTXD   0x000E0000
 
#define EMAC_DMARIS_NIS   0x00010000
 
#define EMAC_DMARIS_AIS   0x00008000
 
#define EMAC_DMARIS_ERI   0x00004000
 
#define EMAC_DMARIS_FBI   0x00002000
 
#define EMAC_DMARIS_ETI   0x00000400
 
#define EMAC_DMARIS_RWT   0x00000200
 
#define EMAC_DMARIS_RPS   0x00000100
 
#define EMAC_DMARIS_RU   0x00000080
 
#define EMAC_DMARIS_RI   0x00000040
 
#define EMAC_DMARIS_UNF   0x00000020
 
#define EMAC_DMARIS_OVF   0x00000010
 
#define EMAC_DMARIS_TJT   0x00000008
 
#define EMAC_DMARIS_TU   0x00000004
 
#define EMAC_DMARIS_TPS   0x00000002
 
#define EMAC_DMARIS_TI   0x00000001
 
#define EMAC_DMAOPMODE_DT   0x04000000
 
#define EMAC_DMAOPMODE_RSF   0x02000000
 
#define EMAC_DMAOPMODE_DFF   0x01000000
 
#define EMAC_DMAOPMODE_TSF   0x00200000
 
#define EMAC_DMAOPMODE_FTF   0x00100000
 
#define EMAC_DMAOPMODE_TTC_M   0x0001C000
 
#define EMAC_DMAOPMODE_TTC_64   0x00000000
 
#define EMAC_DMAOPMODE_TTC_128   0x00004000
 
#define EMAC_DMAOPMODE_TTC_192   0x00008000
 
#define EMAC_DMAOPMODE_TTC_256   0x0000C000
 
#define EMAC_DMAOPMODE_TTC_40   0x00010000
 
#define EMAC_DMAOPMODE_TTC_32   0x00014000
 
#define EMAC_DMAOPMODE_TTC_24   0x00018000
 
#define EMAC_DMAOPMODE_TTC_16   0x0001C000
 
#define EMAC_DMAOPMODE_ST   0x00002000
 
#define EMAC_DMAOPMODE_FEF   0x00000080
 
#define EMAC_DMAOPMODE_FUF   0x00000040
 
#define EMAC_DMAOPMODE_DGF   0x00000020
 
#define EMAC_DMAOPMODE_RTC_M   0x00000018
 
#define EMAC_DMAOPMODE_RTC_64   0x00000000
 
#define EMAC_DMAOPMODE_RTC_32   0x00000008
 
#define EMAC_DMAOPMODE_RTC_96   0x00000010
 
#define EMAC_DMAOPMODE_RTC_128   0x00000018
 
#define EMAC_DMAOPMODE_OSF   0x00000004
 
#define EMAC_DMAOPMODE_SR   0x00000002
 
#define EMAC_DMAIM_NIE   0x00010000
 
#define EMAC_DMAIM_AIE   0x00008000
 
#define EMAC_DMAIM_ERE   0x00004000
 
#define EMAC_DMAIM_FBE   0x00002000
 
#define EMAC_DMAIM_ETE   0x00000400
 
#define EMAC_DMAIM_RWE   0x00000200
 
#define EMAC_DMAIM_RSE   0x00000100
 
#define EMAC_DMAIM_RUE   0x00000080
 
#define EMAC_DMAIM_RIE   0x00000040
 
#define EMAC_DMAIM_UNE   0x00000020
 
#define EMAC_DMAIM_OVE   0x00000010
 
#define EMAC_DMAIM_TJE   0x00000008
 
#define EMAC_DMAIM_TUE   0x00000004
 
#define EMAC_DMAIM_TSE   0x00000002
 
#define EMAC_DMAIM_TIE   0x00000001
 
#define EMAC_MFBOC_OVFCNTOVF   0x10000000
 
#define EMAC_MFBOC_OVFFRMCNT_M   0x0FFE0000
 
#define EMAC_MFBOC_MISCNTOVF   0x00010000
 
#define EMAC_MFBOC_MISFRMCNT_M   0x0000FFFF
 
#define EMAC_MFBOC_OVFFRMCNT_S   17
 
#define EMAC_MFBOC_MISFRMCNT_S   0
 
#define EMAC_RXINTWDT_RIWT_M   0x000000FF
 
#define EMAC_RXINTWDT_RIWT_S   0
 
#define EMAC_HOSTXDESC_CURTXDESC_M   0xFFFFFFFF
 
#define EMAC_HOSTXDESC_CURTXDESC_S   0
 
#define EMAC_HOSRXDESC_CURRXDESC_M   0xFFFFFFFF
 
#define EMAC_HOSRXDESC_CURRXDESC_S   0
 
#define EMAC_HOSTXBA_CURTXBUFA_M   0xFFFFFFFF
 
#define EMAC_HOSTXBA_CURTXBUFA_S   0
 
#define EMAC_HOSRXBA_CURRXBUFA_M   0xFFFFFFFF
 
#define EMAC_HOSRXBA_CURRXBUFA_S   0
 
#define EMAC_PP_MACTYPE_M   0x00000700
 
#define EMAC_PP_MACTYPE_1   0x00000100
 
#define EMAC_PP_PHYTYPE_M   0x00000007
 
#define EMAC_PP_PHYTYPE_NONE   0x00000000
 
#define EMAC_PP_PHYTYPE_1   0x00000003
 
#define EMAC_PC_PHYEXT   0x80000000
 
#define EMAC_PC_PINTFS_M   0x70000000
 
#define EMAC_PC_PINTFS_IMII   0x00000000
 
#define EMAC_PC_PINTFS_RMII   0x40000000
 
#define EMAC_PC_DIGRESTART   0x02000000
 
#define EMAC_PC_NIBDETDIS   0x01000000
 
#define EMAC_PC_RXERIDLE   0x00800000
 
#define EMAC_PC_ISOMIILL   0x00400000
 
#define EMAC_PC_LRR   0x00200000
 
#define EMAC_PC_TDRRUN   0x00100000
 
#define EMAC_PC_FASTLDMODE_M   0x000F8000
 
#define EMAC_PC_POLSWAP   0x00004000
 
#define EMAC_PC_MDISWAP   0x00002000
 
#define EMAC_PC_RBSTMDIX   0x00001000
 
#define EMAC_PC_FASTMDIX   0x00000800
 
#define EMAC_PC_MDIXEN   0x00000400
 
#define EMAC_PC_FASTRXDV   0x00000200
 
#define EMAC_PC_FASTLUPD   0x00000100
 
#define EMAC_PC_EXTFD   0x00000080
 
#define EMAC_PC_FASTANEN   0x00000040
 
#define EMAC_PC_FASTANSEL_M   0x00000030
 
#define EMAC_PC_ANEN   0x00000008
 
#define EMAC_PC_ANMODE_M   0x00000006
 
#define EMAC_PC_ANMODE_10HD   0x00000000
 
#define EMAC_PC_ANMODE_10FD   0x00000002
 
#define EMAC_PC_ANMODE_100HD   0x00000004
 
#define EMAC_PC_ANMODE_100FD   0x00000006
 
#define EMAC_PC_PHYHOLD   0x00000001
 
#define EMAC_PC_FASTLDMODE_S   15
 
#define EMAC_PC_FASTANSEL_S   4
 
#define EMAC_CC_PTPCEN   0x00040000
 
#define EMAC_CC_POL   0x00020000
 
#define EMAC_CC_CLKEN   0x00010000
 
#define EMAC_EPHYRIS_INT   0x00000001
 
#define EMAC_EPHYIM_INT   0x00000001
 
#define EMAC_EPHYMISC_INT   0x00000001
 
#define EPHY_BMCR   0x00000000
 
#define EPHY_BMSR   0x00000001
 
#define EPHY_ID1   0x00000002
 
#define EPHY_ID2   0x00000003
 
#define EPHY_ANA   0x00000004
 
#define EPHY_ANLPA   0x00000005
 
#define EPHY_ANER   0x00000006
 
#define EPHY_ANNPTR   0x00000007
 
#define EPHY_ANLNPTR   0x00000008
 
#define EPHY_CFG1   0x00000009
 
#define EPHY_CFG2   0x0000000A
 
#define EPHY_CFG3   0x0000000B
 
#define EPHY_REGCTL   0x0000000D
 
#define EPHY_ADDAR   0x0000000E
 
#define EPHY_STS   0x00000010
 
#define EPHY_SCR   0x00000011
 
#define EPHY_MISR1   0x00000012
 
#define EPHY_MISR2   0x00000013
 
#define EPHY_FCSCR   0x00000014
 
#define EPHY_RXERCNT   0x00000015
 
#define EPHY_BISTCR   0x00000016
 
#define EPHY_LEDCR   0x00000018
 
#define EPHY_CTL   0x00000019
 
#define EPHY_10BTSC   0x0000001A
 
#define EPHY_BICSR1   0x0000001B
 
#define EPHY_BICSR2   0x0000001C
 
#define EPHY_CDCR   0x0000001E
 
#define EPHY_RCR   0x0000001F
 
#define EPHY_LEDCFG   0x00000025
 
#define EPHY_BMCR_MIIRESET   0x00008000
 
#define EPHY_BMCR_MIILOOPBK   0x00004000
 
#define EPHY_BMCR_SPEED   0x00002000
 
#define EPHY_BMCR_ANEN   0x00001000
 
#define EPHY_BMCR_PWRDWN   0x00000800
 
#define EPHY_BMCR_ISOLATE   0x00000400
 
#define EPHY_BMCR_RESTARTAN   0x00000200
 
#define EPHY_BMCR_DUPLEXM   0x00000100
 
#define EPHY_BMCR_COLLTST   0x00000080
 
#define EPHY_BMSR_100BTXFD   0x00004000
 
#define EPHY_BMSR_100BTXHD   0x00002000
 
#define EPHY_BMSR_10BTFD   0x00001000
 
#define EPHY_BMSR_10BTHD   0x00000800
 
#define EPHY_BMSR_MFPRESUP   0x00000040
 
#define EPHY_BMSR_ANC   0x00000020
 
#define EPHY_BMSR_RFAULT   0x00000010
 
#define EPHY_BMSR_ANEN   0x00000008
 
#define EPHY_BMSR_LINKSTAT   0x00000004
 
#define EPHY_BMSR_JABBER   0x00000002
 
#define EPHY_BMSR_EXTEN   0x00000001
 
#define EPHY_ID1_OUIMSB_M   0x0000FFFF
 
#define EPHY_ID1_OUIMSB_S   0
 
#define EPHY_ID2_OUILSB_M   0x0000FC00
 
#define EPHY_ID2_VNDRMDL_M   0x000003F0
 
#define EPHY_ID2_MDLREV_M   0x0000000F
 
#define EPHY_ID2_OUILSB_S   10
 
#define EPHY_ID2_VNDRMDL_S   4
 
#define EPHY_ID2_MDLREV_S   0
 
#define EPHY_ANA_NP   0x00008000
 
#define EPHY_ANA_RF   0x00002000
 
#define EPHY_ANA_ASMDUP   0x00000800
 
#define EPHY_ANA_PAUSE   0x00000400
 
#define EPHY_ANA_100BT4   0x00000200
 
#define EPHY_ANA_100BTXFD   0x00000100
 
#define EPHY_ANA_100BTX   0x00000080
 
#define EPHY_ANA_10BTFD   0x00000040
 
#define EPHY_ANA_10BT   0x00000020
 
#define EPHY_ANA_SELECT_M   0x0000001F
 
#define EPHY_ANA_SELECT_S   0
 
#define EPHY_ANLPA_NP   0x00008000
 
#define EPHY_ANLPA_ACK   0x00004000
 
#define EPHY_ANLPA_RF   0x00002000
 
#define EPHY_ANLPA_ASMDUP   0x00000800
 
#define EPHY_ANLPA_PAUSE   0x00000400
 
#define EPHY_ANLPA_100BT4   0x00000200
 
#define EPHY_ANLPA_100BTXFD   0x00000100
 
#define EPHY_ANLPA_100BTX   0x00000080
 
#define EPHY_ANLPA_10BTFD   0x00000040
 
#define EPHY_ANLPA_10BT   0x00000020
 
#define EPHY_ANLPA_SELECT_M   0x0000001F
 
#define EPHY_ANLPA_SELECT_S   0
 
#define EPHY_ANER_PDF   0x00000010
 
#define EPHY_ANER_LPNPABLE   0x00000008
 
#define EPHY_ANER_NPABLE   0x00000004
 
#define EPHY_ANER_PAGERX   0x00000002
 
#define EPHY_ANER_LPANABLE   0x00000001
 
#define EPHY_ANNPTR_NP   0x00008000
 
#define EPHY_ANNPTR_MP   0x00002000
 
#define EPHY_ANNPTR_ACK2   0x00001000
 
#define EPHY_ANNPTR_TOGTX   0x00000800
 
#define EPHY_ANNPTR_CODE_M   0x000007FF
 
#define EPHY_ANNPTR_CODE_S   0
 
#define EPHY_ANLNPTR_NP   0x00008000
 
#define EPHY_ANLNPTR_ACK   0x00004000
 
#define EPHY_ANLNPTR_MP   0x00002000
 
#define EPHY_ANLNPTR_ACK2   0x00001000
 
#define EPHY_ANLNPTR_TOG   0x00000800
 
#define EPHY_ANLNPTR_CODE_M   0x000007FF
 
#define EPHY_ANLNPTR_CODE_S   0
 
#define EPHY_CFG1_DONE   0x00008000
 
#define EPHY_CFG1_TDRAR   0x00000100
 
#define EPHY_CFG1_LLR   0x00000080
 
#define EPHY_CFG1_FAMDIX   0x00000040
 
#define EPHY_CFG1_RAMDIX   0x00000020
 
#define EPHY_CFG1_FASTANEN   0x00000010
 
#define EPHY_CFG1_FANSEL_M   0x0000000C
 
#define EPHY_CFG1_FANSEL_BLT80   0x00000000
 
#define EPHY_CFG1_FANSEL_BLT120   0x00000004
 
#define EPHY_CFG1_FANSEL_BLT240   0x00000008
 
#define EPHY_CFG1_FRXDVDET   0x00000002
 
#define EPHY_CFG2_FLUPPD   0x00000040
 
#define EPHY_CFG2_EXTFD   0x00000020
 
#define EPHY_CFG2_ENLEDLINK   0x00000010
 
#define EPHY_CFG2_ISOMIILL   0x00000008
 
#define EPHY_CFG2_RXERRIDLE   0x00000004
 
#define EPHY_CFG2_ODDNDETDIS   0x00000002
 
#define EPHY_CFG3_POLSWAP   0x00000080
 
#define EPHY_CFG3_MDIMDIXS   0x00000040
 
#define EPHY_CFG3_FLDWNM_M   0x0000001F
 
#define EPHY_CFG3_FLDWNM_S   0
 
#define EPHY_REGCTL_FUNC_M   0x0000C000
 
#define EPHY_REGCTL_FUNC_ADDR   0x00000000
 
#define EPHY_REGCTL_FUNC_DATANI   0x00004000
 
#define EPHY_REGCTL_FUNC_DATAPIRW   0x00008000
 
#define EPHY_REGCTL_FUNC_DATAPIWO   0x0000C000
 
#define EPHY_REGCTL_DEVAD_M   0x0000001F
 
#define EPHY_REGCTL_DEVAD_S   0
 
#define EPHY_ADDAR_ADDRDATA_M   0x0000FFFF
 
#define EPHY_ADDAR_ADDRDATA_S   0
 
#define EPHY_STS_MDIXM   0x00004000
 
#define EPHY_STS_RXLERR   0x00002000
 
#define EPHY_STS_POLSTAT   0x00001000
 
#define EPHY_STS_FCSL   0x00000800
 
#define EPHY_STS_SD   0x00000400
 
#define EPHY_STS_DL   0x00000200
 
#define EPHY_STS_PAGERX   0x00000100
 
#define EPHY_STS_MIIREQ   0x00000080
 
#define EPHY_STS_RF   0x00000040
 
#define EPHY_STS_JD   0x00000020
 
#define EPHY_STS_ANS   0x00000010
 
#define EPHY_STS_MIILB   0x00000008
 
#define EPHY_STS_DUPLEX   0x00000004
 
#define EPHY_STS_SPEED   0x00000002
 
#define EPHY_STS_LINK   0x00000001
 
#define EPHY_SCR_DISCLK   0x00008000
 
#define EPHY_SCR_PSEN   0x00004000
 
#define EPHY_SCR_PSMODE_M   0x00003000
 
#define EPHY_SCR_PSMODE_NORMAL   0x00000000
 
#define EPHY_SCR_PSMODE_LOWPWR   0x00001000
 
#define EPHY_SCR_PSMODE_ACTWOL   0x00002000
 
#define EPHY_SCR_PSMODE_PASWOL   0x00003000
 
#define EPHY_SCR_SBPYASS   0x00000800
 
#define EPHY_SCR_LBFIFO_M   0x00000300
 
#define EPHY_SCR_LBFIFO_4   0x00000000
 
#define EPHY_SCR_LBFIFO_5   0x00000100
 
#define EPHY_SCR_LBFIFO_6   0x00000200
 
#define EPHY_SCR_LBFIFO_8   0x00000300
 
#define EPHY_SCR_COLFDM   0x00000010
 
#define EPHY_SCR_TINT   0x00000004
 
#define EPHY_SCR_INTEN   0x00000002
 
#define EPHY_MISR1_LINKSTAT   0x00002000
 
#define EPHY_MISR1_SPEED   0x00001000
 
#define EPHY_MISR1_DUPLEXM   0x00000800
 
#define EPHY_MISR1_ANC   0x00000400
 
#define EPHY_MISR1_FCHF   0x00000200
 
#define EPHY_MISR1_RXHF   0x00000100
 
#define EPHY_MISR1_LINKSTATEN   0x00000020
 
#define EPHY_MISR1_SPEEDEN   0x00000010
 
#define EPHY_MISR1_DUPLEXMEN   0x00000008
 
#define EPHY_MISR1_ANCEN   0x00000004
 
#define EPHY_MISR1_FCHFEN   0x00000002
 
#define EPHY_MISR1_RXHFEN   0x00000001
 
#define EPHY_MISR2_ANERR   0x00004000
 
#define EPHY_MISR2_PAGERX   0x00002000
 
#define EPHY_MISR2_LBFIFO   0x00001000
 
#define EPHY_MISR2_MDICO   0x00000800
 
#define EPHY_MISR2_SLEEP   0x00000400
 
#define EPHY_MISR2_POLINT   0x00000200
 
#define EPHY_MISR2_JABBER   0x00000100
 
#define EPHY_MISR2_ANERREN   0x00000040
 
#define EPHY_MISR2_PAGERXEN   0x00000020
 
#define EPHY_MISR2_LBFIFOEN   0x00000010
 
#define EPHY_MISR2_MDICOEN   0x00000008
 
#define EPHY_MISR2_SLEEPEN   0x00000004
 
#define EPHY_MISR2_POLINTEN   0x00000002
 
#define EPHY_MISR2_JABBEREN   0x00000001
 
#define EPHY_FCSCR_FCSCNT_M   0x000000FF
 
#define EPHY_FCSCR_FCSCNT_S   0
 
#define EPHY_RXERCNT_RXERRCNT_M   0x0000FFFF
 
#define EPHY_RXERCNT_RXERRCNT_S   0
 
#define EPHY_BISTCR_PRBSM   0x00004000
 
#define EPHY_BISTCR_PRBSPKT   0x00002000
 
#define EPHY_BISTCR_PKTEN   0x00001000
 
#define EPHY_BISTCR_PRBSCHKLK   0x00000800
 
#define EPHY_BISTCR_PRBSCHKSYNC   0x00000400
 
#define EPHY_BISTCR_PKTGENSTAT   0x00000200
 
#define EPHY_BISTCR_PWRMODE   0x00000100
 
#define EPHY_BISTCR_TXMIILB   0x00000040
 
#define EPHY_BISTCR_LBMODE_M   0x0000001F
 
#define EPHY_BISTCR_LBMODE_NPCSIN   0x00000001
 
#define EPHY_BISTCR_LBMODE_NPCSOUT   0x00000002
 
#define EPHY_BISTCR_LBMODE_NDIG   0x00000004
 
#define EPHY_BISTCR_LBMODE_NANA   0x00000008
 
#define EPHY_BISTCR_LBMODE_FREV   0x00000010
 
#define EPHY_LEDCR_BLINKRATE_M   0x00000600
 
#define EPHY_LEDCR_BLINKRATE_20HZ   0x00000000
 
#define EPHY_LEDCR_BLINKRATE_10HZ   0x00000200
 
#define EPHY_LEDCR_BLINKRATE_5HZ   0x00000400
 
#define EPHY_LEDCR_BLINKRATE_2HZ   0x00000600
 
#define EPHY_CTL_AUTOMDI   0x00008000
 
#define EPHY_CTL_FORCEMDI   0x00004000
 
#define EPHY_CTL_PAUSERX   0x00002000
 
#define EPHY_CTL_PAUSETX   0x00001000
 
#define EPHY_CTL_MIILNKSTAT   0x00000800
 
#define EPHY_CTL_BYPLEDSTRCH   0x00000080
 
#define EPHY_10BTSC_RXTHEN   0x00002000
 
#define EPHY_10BTSC_SQUELCH_M   0x00001E00
 
#define EPHY_10BTSC_NLPDIS   0x00000080
 
#define EPHY_10BTSC_POLSTAT   0x00000010
 
#define EPHY_10BTSC_JABBERD   0x00000001
 
#define EPHY_10BTSC_SQUELCH_S   9
 
#define EPHY_BICSR1_ERRCNT_M   0x0000FF00
 
#define EPHY_BICSR1_IPGLENGTH_M   0x000000FF
 
#define EPHY_BICSR1_ERRCNT_S   8
 
#define EPHY_BICSR1_IPGLENGTH_S   0
 
#define EPHY_BICSR2_PKTLENGTH_M   0x000007FF
 
#define EPHY_BICSR2_PKTLENGTH_S   0
 
#define EPHY_CDCR_START   0x00008000
 
#define EPHY_CDCR_LINKQUAL_M   0x00000300
 
#define EPHY_CDCR_LINKQUAL_GOOD   0x00000100
 
#define EPHY_CDCR_LINKQUAL_MILD   0x00000200
 
#define EPHY_CDCR_LINKQUAL_POOR   0x00000300
 
#define EPHY_CDCR_DONE   0x00000002
 
#define EPHY_CDCR_FAIL   0x00000001
 
#define EPHY_RCR_SWRST   0x00008000
 
#define EPHY_RCR_SWRESTART   0x00004000
 
#define EPHY_LEDCFG_LED2_M   0x00000F00
 
#define EPHY_LEDCFG_LED2_LINK   0x00000000
 
#define EPHY_LEDCFG_LED2_RXTX   0x00000100
 
#define EPHY_LEDCFG_LED2_TX   0x00000200
 
#define EPHY_LEDCFG_LED2_RX   0x00000300
 
#define EPHY_LEDCFG_LED2_COL   0x00000400
 
#define EPHY_LEDCFG_LED2_100BT   0x00000500
 
#define EPHY_LEDCFG_LED2_10BT   0x00000600
 
#define EPHY_LEDCFG_LED2_FD   0x00000700
 
#define EPHY_LEDCFG_LED2_LINKTXRX   0x00000800
 
#define EPHY_LEDCFG_LED1_M   0x000000F0
 
#define EPHY_LEDCFG_LED1_LINK   0x00000000
 
#define EPHY_LEDCFG_LED1_RXTX   0x00000010
 
#define EPHY_LEDCFG_LED1_TX   0x00000020
 
#define EPHY_LEDCFG_LED1_RX   0x00000030
 
#define EPHY_LEDCFG_LED1_COL   0x00000040
 
#define EPHY_LEDCFG_LED1_100BT   0x00000050
 
#define EPHY_LEDCFG_LED1_10BT   0x00000060
 
#define EPHY_LEDCFG_LED1_FD   0x00000070
 
#define EPHY_LEDCFG_LED1_LINKTXRX   0x00000080
 
#define EPHY_LEDCFG_LED0_M   0x0000000F
 
#define EPHY_LEDCFG_LED0_LINK   0x00000000
 
#define EPHY_LEDCFG_LED0_RXTX   0x00000001
 
#define EPHY_LEDCFG_LED0_TX   0x00000002
 
#define EPHY_LEDCFG_LED0_RX   0x00000003
 
#define EPHY_LEDCFG_LED0_COL   0x00000004
 
#define EPHY_LEDCFG_LED0_100BT   0x00000005
 
#define EPHY_LEDCFG_LED0_10BT   0x00000006
 
#define EPHY_LEDCFG_LED0_FD   0x00000007
 
#define EPHY_LEDCFG_LED0_LINKTXRX   0x00000008
 
#define EMAC_PPSCTRL_PPSCTRL_1HZ   0x00000000
 
#define EMAC_PPSCTRL_PPSCTRL_2HZ   0x00000001
 
#define EMAC_PPSCTRL_PPSCTRL_4HZ   0x00000002
 
#define EMAC_PPSCTRL_PPSCTRL_8HZ   0x00000003
 
#define EMAC_PPSCTRL_PPSCTRL_16HZ   0x00000004
 
#define EMAC_PPSCTRL_PPSCTRL_32HZ   0x00000005
 
#define EMAC_PPSCTRL_PPSCTRL_64HZ   0x00000006
 
#define EMAC_PPSCTRL_PPSCTRL_128HZ   0x00000007
 
#define EMAC_PPSCTRL_PPSCTRL_256HZ   0x00000008
 
#define EMAC_PPSCTRL_PPSCTRL_512HZ   0x00000009
 
#define EMAC_PPSCTRL_PPSCTRL_1024HZ   0x0000000A
 
#define EMAC_PPSCTRL_PPSCTRL_2048HZ   0x0000000B
 
#define EMAC_PPSCTRL_PPSCTRL_4096HZ   0x0000000C
 
#define EMAC_PPSCTRL_PPSCTRL_8192HZ   0x0000000D
 
#define EMAC_PPSCTRL_PPSCTRL_16384HZ   0x0000000E
 
#define EMAC_PPSCTRL_PPSCTRL_32768HZ   0x0000000F
 
#define EMAC_CC_CS_PA7   0x00000001
 

Macro Definition Documentation

§ EMAC_O_CFG

#define EMAC_O_CFG   0x00000000

§ EMAC_O_FRAMEFLTR

#define EMAC_O_FRAMEFLTR   0x00000004

§ EMAC_O_HASHTBLH

#define EMAC_O_HASHTBLH   0x00000008

§ EMAC_O_HASHTBLL

#define EMAC_O_HASHTBLL   0x0000000C

§ EMAC_O_MIIADDR

#define EMAC_O_MIIADDR   0x00000010

Referenced by EMACPHYRead(), and EMACPHYWrite().

§ EMAC_O_MIIDATA

#define EMAC_O_MIIDATA   0x00000014

Referenced by EMACPHYRead(), and EMACPHYWrite().

§ EMAC_O_FLOWCTL

#define EMAC_O_FLOWCTL   0x00000018

§ EMAC_O_VLANTG

#define EMAC_O_VLANTG   0x0000001C

§ EMAC_O_STATUS

#define EMAC_O_STATUS   0x00000024

§ EMAC_O_RWUFF

#define EMAC_O_RWUFF   0x00000028

§ EMAC_O_PMTCTLSTAT

#define EMAC_O_PMTCTLSTAT   0x0000002C

§ EMAC_O_LPICTLSTAT

#define EMAC_O_LPICTLSTAT   0x00000030

§ EMAC_O_LPITIMERCTL

#define EMAC_O_LPITIMERCTL   0x00000034

Referenced by EMACLPIConfig().

§ EMAC_O_RIS

#define EMAC_O_RIS   0x00000038

§ EMAC_O_IM

#define EMAC_O_IM   0x0000003C

§ EMAC_O_ADDR0H

#define EMAC_O_ADDR0H   0x00000040

§ EMAC_O_ADDR0L

#define EMAC_O_ADDR0L   0x00000044

§ EMAC_O_ADDR1H

#define EMAC_O_ADDR1H   0x00000048

§ EMAC_O_ADDR1L

#define EMAC_O_ADDR1L   0x0000004C

§ EMAC_O_ADDR2H

#define EMAC_O_ADDR2H   0x00000050

§ EMAC_O_ADDR2L

#define EMAC_O_ADDR2L   0x00000054

§ EMAC_O_ADDR3H

#define EMAC_O_ADDR3H   0x00000058

§ EMAC_O_ADDR3L

#define EMAC_O_ADDR3L   0x0000005C

§ EMAC_O_WDOGTO

#define EMAC_O_WDOGTO   0x000000DC

Referenced by EMACConfigGet(), and EMACConfigSet().

§ EMAC_O_MMCCTRL

#define EMAC_O_MMCCTRL   0x00000100

§ EMAC_O_MMCRXRIS

#define EMAC_O_MMCRXRIS   0x00000104

§ EMAC_O_MMCTXRIS

#define EMAC_O_MMCTXRIS   0x00000108

§ EMAC_O_MMCRXIM

#define EMAC_O_MMCRXIM   0x0000010C

§ EMAC_O_MMCTXIM

#define EMAC_O_MMCTXIM   0x00000110

§ EMAC_O_TXCNTGB

#define EMAC_O_TXCNTGB   0x00000118

§ EMAC_O_TXCNTSCOL

#define EMAC_O_TXCNTSCOL   0x0000014C

§ EMAC_O_TXCNTMCOL

#define EMAC_O_TXCNTMCOL   0x00000150

§ EMAC_O_TXOCTCNTG

#define EMAC_O_TXOCTCNTG   0x00000164

§ EMAC_O_RXCNTGB

#define EMAC_O_RXCNTGB   0x00000180

§ EMAC_O_RXCNTCRCERR

#define EMAC_O_RXCNTCRCERR   0x00000194

§ EMAC_O_RXCNTALGNERR

#define EMAC_O_RXCNTALGNERR   0x00000198

§ EMAC_O_RXCNTGUNI

#define EMAC_O_RXCNTGUNI   0x000001C4

§ EMAC_O_VLNINCREP

#define EMAC_O_VLNINCREP   0x00000584

§ EMAC_O_VLANHASH

#define EMAC_O_VLANHASH   0x00000588

§ EMAC_O_TIMSTCTRL

#define EMAC_O_TIMSTCTRL   0x00000700

§ EMAC_O_SUBSECINC

#define EMAC_O_SUBSECINC   0x00000704

§ EMAC_O_TIMSEC

#define EMAC_O_TIMSEC   0x00000708

Referenced by EMACTimestampSysTimeGet().

§ EMAC_O_TIMNANO

#define EMAC_O_TIMNANO   0x0000070C

Referenced by EMACTimestampSysTimeGet().

§ EMAC_O_TIMSECU

#define EMAC_O_TIMSECU   0x00000710

§ EMAC_O_TIMNANOU

#define EMAC_O_TIMNANOU   0x00000714

§ EMAC_O_TIMADD

#define EMAC_O_TIMADD   0x00000718

Referenced by EMACTimestampAddendSet().

§ EMAC_O_TARGSEC

#define EMAC_O_TARGSEC   0x0000071C

Referenced by EMACTimestampTargetSet().

§ EMAC_O_TARGNANO

#define EMAC_O_TARGNANO   0x00000720

Referenced by EMACTimestampTargetSet().

§ EMAC_O_HWORDSEC

#define EMAC_O_HWORDSEC   0x00000724

§ EMAC_O_TIMSTAT

#define EMAC_O_TIMSTAT   0x00000728

Referenced by EMACTimestampIntStatus().

§ EMAC_O_PPSCTRL

#define EMAC_O_PPSCTRL   0x0000072C

§ EMAC_O_PPS0INTVL

#define EMAC_O_PPS0INTVL   0x00000760

§ EMAC_O_PPS0WIDTH

#define EMAC_O_PPS0WIDTH   0x00000764

§ EMAC_O_DMABUSMOD

#define EMAC_O_DMABUSMOD   0x00000C00

Referenced by EMACInit(), and EMACReset().

§ EMAC_O_TXPOLLD

#define EMAC_O_TXPOLLD   0x00000C04

Referenced by EMACTxDMAPollDemand().

§ EMAC_O_RXPOLLD

#define EMAC_O_RXPOLLD   0x00000C08

Referenced by EMACRxDMAPollDemand().

§ EMAC_O_RXDLADDR

#define EMAC_O_RXDLADDR   0x00000C0C

§ EMAC_O_TXDLADDR

#define EMAC_O_TXDLADDR   0x00000C10

§ EMAC_O_DMARIS

#define EMAC_O_DMARIS   0x00000C14

§ EMAC_O_DMAOPMODE

#define EMAC_O_DMAOPMODE   0x00000C18

§ EMAC_O_DMAIM

#define EMAC_O_DMAIM   0x00000C1C

§ EMAC_O_MFBOC

#define EMAC_O_MFBOC   0x00000C20

§ EMAC_O_RXINTWDT

#define EMAC_O_RXINTWDT   0x00000C24

Referenced by EMACRxWatchdogTimerSet().

§ EMAC_O_HOSTXDESC

#define EMAC_O_HOSTXDESC   0x00000C48

§ EMAC_O_HOSRXDESC

#define EMAC_O_HOSRXDESC   0x00000C4C

§ EMAC_O_HOSTXBA

#define EMAC_O_HOSTXBA   0x00000C50

§ EMAC_O_HOSRXBA

#define EMAC_O_HOSRXBA   0x00000C54

§ EMAC_O_PP

#define EMAC_O_PP   0x00000FC0

§ EMAC_O_PC

#define EMAC_O_PC   0x00000FC4

Referenced by EMACPHYConfigSet().

§ EMAC_O_CC

#define EMAC_O_CC   0x00000FC8

§ EMAC_O_EPHYRIS

#define EMAC_O_EPHYRIS   0x00000FD0

Referenced by EMACIntStatus().

§ EMAC_O_EPHYIM

#define EMAC_O_EPHYIM   0x00000FD4

Referenced by EMACIntDisable(), and EMACIntEnable().

§ EMAC_O_EPHYMISC

#define EMAC_O_EPHYMISC   0x00000FD8

Referenced by EMACIntClear(), and EMACIntStatus().

§ EMAC_CFG_TWOKPEN

#define EMAC_CFG_TWOKPEN   0x08000000

§ EMAC_CFG_CST

#define EMAC_CFG_CST   0x02000000

§ EMAC_CFG_WDDIS

#define EMAC_CFG_WDDIS   0x00800000

§ EMAC_CFG_JD

#define EMAC_CFG_JD   0x00400000

§ EMAC_CFG_JFEN

#define EMAC_CFG_JFEN   0x00100000

Referenced by EMACConfigGet().

§ EMAC_CFG_IFG_M

#define EMAC_CFG_IFG_M   0x000E0000

§ EMAC_CFG_IFG_96

#define EMAC_CFG_IFG_96   0x00000000

§ EMAC_CFG_IFG_88

#define EMAC_CFG_IFG_88   0x00020000

§ EMAC_CFG_IFG_80

#define EMAC_CFG_IFG_80   0x00040000

§ EMAC_CFG_IFG_72

#define EMAC_CFG_IFG_72   0x00060000

§ EMAC_CFG_IFG_64

#define EMAC_CFG_IFG_64   0x00080000

§ EMAC_CFG_IFG_56

#define EMAC_CFG_IFG_56   0x000A0000

§ EMAC_CFG_IFG_48

#define EMAC_CFG_IFG_48   0x000C0000

§ EMAC_CFG_IFG_40

#define EMAC_CFG_IFG_40   0x000E0000

§ EMAC_CFG_DISCRS

#define EMAC_CFG_DISCRS   0x00010000

§ EMAC_CFG_PS

#define EMAC_CFG_PS   0x00008000

Referenced by EMACConfigSet().

§ EMAC_CFG_FES

#define EMAC_CFG_FES   0x00004000

§ EMAC_CFG_DRO

#define EMAC_CFG_DRO   0x00002000

§ EMAC_CFG_LOOPBM

#define EMAC_CFG_LOOPBM   0x00001000

§ EMAC_CFG_DUPM

#define EMAC_CFG_DUPM   0x00000800

§ EMAC_CFG_IPC

#define EMAC_CFG_IPC   0x00000400

§ EMAC_CFG_DR

#define EMAC_CFG_DR   0x00000200

§ EMAC_CFG_ACS

#define EMAC_CFG_ACS   0x00000080

§ EMAC_CFG_BL_M

#define EMAC_CFG_BL_M   0x00000060

§ EMAC_CFG_BL_1024

#define EMAC_CFG_BL_1024   0x00000000

§ EMAC_CFG_BL_256

#define EMAC_CFG_BL_256   0x00000020

§ EMAC_CFG_BL_8

#define EMAC_CFG_BL_8   0x00000040

§ EMAC_CFG_BL_2

#define EMAC_CFG_BL_2   0x00000060

§ EMAC_CFG_DC

#define EMAC_CFG_DC   0x00000010

§ EMAC_CFG_TE

#define EMAC_CFG_TE   0x00000008

§ EMAC_CFG_RE

#define EMAC_CFG_RE   0x00000004

Referenced by EMACRxDisable(), and EMACRxEnable().

§ EMAC_CFG_PRELEN_M

#define EMAC_CFG_PRELEN_M   0x00000003

§ EMAC_CFG_PRELEN_7

#define EMAC_CFG_PRELEN_7   0x00000000

§ EMAC_CFG_PRELEN_5

#define EMAC_CFG_PRELEN_5   0x00000001

§ EMAC_CFG_PRELEN_3

#define EMAC_CFG_PRELEN_3   0x00000002

§ EMAC_FRAMEFLTR_RA

#define EMAC_FRAMEFLTR_RA   0x80000000

§ EMAC_FRAMEFLTR_VTFE

#define EMAC_FRAMEFLTR_VTFE   0x00010000

§ EMAC_FRAMEFLTR_HPF

#define EMAC_FRAMEFLTR_HPF   0x00000400

§ EMAC_FRAMEFLTR_SAF

#define EMAC_FRAMEFLTR_SAF   0x00000200

§ EMAC_FRAMEFLTR_SAIF

#define EMAC_FRAMEFLTR_SAIF   0x00000100

§ EMAC_FRAMEFLTR_PCF_M

#define EMAC_FRAMEFLTR_PCF_M   0x000000C0

§ EMAC_FRAMEFLTR_PCF_ALL

#define EMAC_FRAMEFLTR_PCF_ALL   0x00000000

§ EMAC_FRAMEFLTR_PCF_PAUSE

#define EMAC_FRAMEFLTR_PCF_PAUSE   0x00000040

§ EMAC_FRAMEFLTR_PCF_NONE

#define EMAC_FRAMEFLTR_PCF_NONE   0x00000080

§ EMAC_FRAMEFLTR_PCF_ADDR

#define EMAC_FRAMEFLTR_PCF_ADDR   0x000000C0

§ EMAC_FRAMEFLTR_DBF

#define EMAC_FRAMEFLTR_DBF   0x00000020

§ EMAC_FRAMEFLTR_PM

#define EMAC_FRAMEFLTR_PM   0x00000010

§ EMAC_FRAMEFLTR_DAIF

#define EMAC_FRAMEFLTR_DAIF   0x00000008

§ EMAC_FRAMEFLTR_HMC

#define EMAC_FRAMEFLTR_HMC   0x00000004

§ EMAC_FRAMEFLTR_HUC

#define EMAC_FRAMEFLTR_HUC   0x00000002

§ EMAC_FRAMEFLTR_PR

#define EMAC_FRAMEFLTR_PR   0x00000001

§ EMAC_HASHTBLH_HTH_M

#define EMAC_HASHTBLH_HTH_M   0xFFFFFFFF

§ EMAC_HASHTBLH_HTH_S

#define EMAC_HASHTBLH_HTH_S   0

§ EMAC_HASHTBLL_HTL_M

#define EMAC_HASHTBLL_HTL_M   0xFFFFFFFF

§ EMAC_HASHTBLL_HTL_S

#define EMAC_HASHTBLL_HTL_S   0

§ EMAC_MIIADDR_PLA_M

#define EMAC_MIIADDR_PLA_M   0x0000F800

§ EMAC_MIIADDR_MII_M

#define EMAC_MIIADDR_MII_M   0x000007C0

§ EMAC_MIIADDR_CR_M

#define EMAC_MIIADDR_CR_M   0x0000003C

Referenced by EMACPHYRead(), and EMACPHYWrite().

§ EMAC_MIIADDR_CR_60_100

#define EMAC_MIIADDR_CR_60_100   0x00000000

§ EMAC_MIIADDR_CR_100_150

#define EMAC_MIIADDR_CR_100_150   0x00000004

§ EMAC_MIIADDR_CR_20_35

#define EMAC_MIIADDR_CR_20_35   0x00000008

§ EMAC_MIIADDR_CR_35_60

#define EMAC_MIIADDR_CR_35_60   0x0000000C

§ EMAC_MIIADDR_MIIW

#define EMAC_MIIADDR_MIIW   0x00000002

Referenced by EMACPHYWrite().

§ EMAC_MIIADDR_MIIB

#define EMAC_MIIADDR_MIIB   0x00000001

Referenced by EMACPHYRead(), and EMACPHYWrite().

§ EMAC_MIIADDR_PLA_S

#define EMAC_MIIADDR_PLA_S   11

Referenced by EMACPHYRead(), and EMACPHYWrite().

§ EMAC_MIIADDR_MII_S

#define EMAC_MIIADDR_MII_S   6

Referenced by EMACPHYRead(), and EMACPHYWrite().

§ EMAC_MIIDATA_DATA_M

#define EMAC_MIIDATA_DATA_M   0x0000FFFF

Referenced by EMACPHYRead().

§ EMAC_MIIDATA_DATA_S

#define EMAC_MIIDATA_DATA_S   0

§ EMAC_FLOWCTL_PT_M

#define EMAC_FLOWCTL_PT_M   0xFFFF0000

§ EMAC_FLOWCTL_DZQP

#define EMAC_FLOWCTL_DZQP   0x00000080

§ EMAC_FLOWCTL_UP

#define EMAC_FLOWCTL_UP   0x00000008

§ EMAC_FLOWCTL_RFE

#define EMAC_FLOWCTL_RFE   0x00000004

§ EMAC_FLOWCTL_TFE

#define EMAC_FLOWCTL_TFE   0x00000002

§ EMAC_FLOWCTL_FCBBPA

#define EMAC_FLOWCTL_FCBBPA   0x00000001

§ EMAC_FLOWCTL_PT_S

#define EMAC_FLOWCTL_PT_S   16

§ EMAC_VLANTG_VTHM

#define EMAC_VLANTG_VTHM   0x00080000

§ EMAC_VLANTG_ESVL

#define EMAC_VLANTG_ESVL   0x00040000

§ EMAC_VLANTG_VTIM

#define EMAC_VLANTG_VTIM   0x00020000

§ EMAC_VLANTG_ETV

#define EMAC_VLANTG_ETV   0x00010000

§ EMAC_VLANTG_VL_M

#define EMAC_VLANTG_VL_M   0x0000FFFF

Referenced by EMACVLANRxConfigGet().

§ EMAC_VLANTG_VL_S

#define EMAC_VLANTG_VL_S   0

§ EMAC_STATUS_TXFF

#define EMAC_STATUS_TXFF   0x02000000

§ EMAC_STATUS_TXFE

#define EMAC_STATUS_TXFE   0x01000000

Referenced by EMACTxFlush().

§ EMAC_STATUS_TWC

#define EMAC_STATUS_TWC   0x00400000

§ EMAC_STATUS_TRC_M

#define EMAC_STATUS_TRC_M   0x00300000

§ EMAC_STATUS_TRC_IDLE

#define EMAC_STATUS_TRC_IDLE   0x00000000

§ EMAC_STATUS_TRC_READ

#define EMAC_STATUS_TRC_READ   0x00100000

§ EMAC_STATUS_TRC_WAIT

#define EMAC_STATUS_TRC_WAIT   0x00200000

§ EMAC_STATUS_TRC_WRFLUSH

#define EMAC_STATUS_TRC_WRFLUSH   0x00300000

§ EMAC_STATUS_TXPAUSED

#define EMAC_STATUS_TXPAUSED   0x00080000

§ EMAC_STATUS_TFC_M

#define EMAC_STATUS_TFC_M   0x00060000

§ EMAC_STATUS_TFC_IDLE

#define EMAC_STATUS_TFC_IDLE   0x00000000

§ EMAC_STATUS_TFC_STATUS

#define EMAC_STATUS_TFC_STATUS   0x00020000

§ EMAC_STATUS_TFC_PAUSE

#define EMAC_STATUS_TFC_PAUSE   0x00040000

§ EMAC_STATUS_TFC_INPUT

#define EMAC_STATUS_TFC_INPUT   0x00060000

§ EMAC_STATUS_TPE

#define EMAC_STATUS_TPE   0x00010000

§ EMAC_STATUS_RXF_M

#define EMAC_STATUS_RXF_M   0x00000300

§ EMAC_STATUS_RXF_EMPTY

#define EMAC_STATUS_RXF_EMPTY   0x00000000

§ EMAC_STATUS_RXF_BELOW

#define EMAC_STATUS_RXF_BELOW   0x00000100

§ EMAC_STATUS_RXF_ABOVE

#define EMAC_STATUS_RXF_ABOVE   0x00000200

§ EMAC_STATUS_RXF_FULL

#define EMAC_STATUS_RXF_FULL   0x00000300

§ EMAC_STATUS_RRC_M

#define EMAC_STATUS_RRC_M   0x00000060

§ EMAC_STATUS_RRC_IDLE

#define EMAC_STATUS_RRC_IDLE   0x00000000

§ EMAC_STATUS_RRC_STATUS

#define EMAC_STATUS_RRC_STATUS   0x00000020

§ EMAC_STATUS_RRC_DATA

#define EMAC_STATUS_RRC_DATA   0x00000040

§ EMAC_STATUS_RRC_FLUSH

#define EMAC_STATUS_RRC_FLUSH   0x00000060

§ EMAC_STATUS_RWC

#define EMAC_STATUS_RWC   0x00000010

§ EMAC_STATUS_RFCFC_M

#define EMAC_STATUS_RFCFC_M   0x00000006

§ EMAC_STATUS_RPE

#define EMAC_STATUS_RPE   0x00000001

§ EMAC_STATUS_RFCFC_S

#define EMAC_STATUS_RFCFC_S   1

§ EMAC_RWUFF_WAKEUPFIL_M

#define EMAC_RWUFF_WAKEUPFIL_M   0xFFFFFFFF

§ EMAC_RWUFF_WAKEUPFIL_S

#define EMAC_RWUFF_WAKEUPFIL_S   0

§ EMAC_PMTCTLSTAT_WUPFRRST

#define EMAC_PMTCTLSTAT_WUPFRRST   0x80000000

§ EMAC_PMTCTLSTAT_RWKPTR_M

#define EMAC_PMTCTLSTAT_RWKPTR_M   0x07000000

§ EMAC_PMTCTLSTAT_GLBLUCAST

#define EMAC_PMTCTLSTAT_GLBLUCAST   0x00000200

§ EMAC_PMTCTLSTAT_WUPRX

#define EMAC_PMTCTLSTAT_WUPRX   0x00000040

§ EMAC_PMTCTLSTAT_MGKPRX

#define EMAC_PMTCTLSTAT_MGKPRX   0x00000020

§ EMAC_PMTCTLSTAT_WUPFREN

#define EMAC_PMTCTLSTAT_WUPFREN   0x00000004

§ EMAC_PMTCTLSTAT_MGKPKTEN

#define EMAC_PMTCTLSTAT_MGKPKTEN   0x00000002

§ EMAC_PMTCTLSTAT_PWRDWN

#define EMAC_PMTCTLSTAT_PWRDWN   0x00000001

§ EMAC_PMTCTLSTAT_RWKPTR_S

#define EMAC_PMTCTLSTAT_RWKPTR_S   24

§ EMAC_LPICTLSTAT_LPITXA

#define EMAC_LPICTLSTAT_LPITXA   0x00080000

Referenced by EMACLPIConfig().

§ EMAC_LPICTLSTAT_PLSEN

#define EMAC_LPICTLSTAT_PLSEN   0x00040000

§ EMAC_LPICTLSTAT_PLS

#define EMAC_LPICTLSTAT_PLS   0x00020000

Referenced by EMACLPILinkClear(), and EMACLPILinkSet().

§ EMAC_LPICTLSTAT_LPIEN

#define EMAC_LPICTLSTAT_LPIEN   0x00010000

Referenced by EMACLPIEnter().

§ EMAC_LPICTLSTAT_RLPIST

#define EMAC_LPICTLSTAT_RLPIST   0x00000200

§ EMAC_LPICTLSTAT_TLPIST

#define EMAC_LPICTLSTAT_TLPIST   0x00000100

§ EMAC_LPICTLSTAT_RLPIEX

#define EMAC_LPICTLSTAT_RLPIEX   0x00000008

§ EMAC_LPICTLSTAT_RLPIEN

#define EMAC_LPICTLSTAT_RLPIEN   0x00000004

§ EMAC_LPICTLSTAT_TLPIEX

#define EMAC_LPICTLSTAT_TLPIEX   0x00000002

§ EMAC_LPICTLSTAT_TLPIEN

#define EMAC_LPICTLSTAT_TLPIEN   0x00000001

§ EMAC_LPITIMERCTL_LST_M

#define EMAC_LPITIMERCTL_LST_M   0x03FF0000

Referenced by EMACLPIConfig().

§ EMAC_LPITIMERCTL_LST_S

#define EMAC_LPITIMERCTL_LST_S   16

Referenced by EMACLPIConfig().

§ EMAC_LPITIMERCTL_TWT_M

#define EMAC_LPITIMERCTL_TWT_M   0x0000FFFF

Referenced by EMACLPIConfig().

§ EMAC_LPITIMERCTL_TWT_S

#define EMAC_LPITIMERCTL_TWT_S   0

§ EMAC_RIS_LPI

#define EMAC_RIS_LPI   0x00000400

§ EMAC_RIS_TS

#define EMAC_RIS_TS   0x00000200

§ EMAC_RIS_MMCTX

#define EMAC_RIS_MMCTX   0x00000040

§ EMAC_RIS_MMCRX

#define EMAC_RIS_MMCRX   0x00000020

§ EMAC_RIS_MMC

#define EMAC_RIS_MMC   0x00000010

§ EMAC_RIS_PMT

#define EMAC_RIS_PMT   0x00000008

§ EMAC_IM_LPI

#define EMAC_IM_LPI   0x00000400

§ EMAC_IM_TSI

#define EMAC_IM_TSI   0x00000200

§ EMAC_IM_PMT

#define EMAC_IM_PMT   0x00000008

§ EMAC_ADDR0H_AE

#define EMAC_ADDR0H_AE   0x80000000

§ EMAC_ADDR0H_ADDRHI_M

#define EMAC_ADDR0H_ADDRHI_M   0x0000FFFF

§ EMAC_ADDR0H_ADDRHI_S

#define EMAC_ADDR0H_ADDRHI_S   0

§ EMAC_ADDR0L_ADDRLO_M

#define EMAC_ADDR0L_ADDRLO_M   0xFFFFFFFF

§ EMAC_ADDR0L_ADDRLO_S

#define EMAC_ADDR0L_ADDRLO_S   0

§ EMAC_ADDR1H_AE

#define EMAC_ADDR1H_AE   0x80000000

§ EMAC_ADDR1H_SA

#define EMAC_ADDR1H_SA   0x40000000

§ EMAC_ADDR1H_MBC_M

#define EMAC_ADDR1H_MBC_M   0x3F000000

§ EMAC_ADDR1H_ADDRHI_M

#define EMAC_ADDR1H_ADDRHI_M   0x0000FFFF

§ EMAC_ADDR1H_MBC_S

#define EMAC_ADDR1H_MBC_S   24

§ EMAC_ADDR1H_ADDRHI_S

#define EMAC_ADDR1H_ADDRHI_S   0

§ EMAC_ADDR1L_ADDRLO_M

#define EMAC_ADDR1L_ADDRLO_M   0xFFFFFFFF

§ EMAC_ADDR1L_ADDRLO_S

#define EMAC_ADDR1L_ADDRLO_S   0

§ EMAC_ADDR2H_AE

#define EMAC_ADDR2H_AE   0x80000000

§ EMAC_ADDR2H_SA

#define EMAC_ADDR2H_SA   0x40000000

§ EMAC_ADDR2H_MBC_M

#define EMAC_ADDR2H_MBC_M   0x3F000000

§ EMAC_ADDR2H_ADDRHI_M

#define EMAC_ADDR2H_ADDRHI_M   0x0000FFFF

§ EMAC_ADDR2H_MBC_S

#define EMAC_ADDR2H_MBC_S   24

§ EMAC_ADDR2H_ADDRHI_S

#define EMAC_ADDR2H_ADDRHI_S   0

§ EMAC_ADDR2L_ADDRLO_M

#define EMAC_ADDR2L_ADDRLO_M   0xFFFFFFFF

§ EMAC_ADDR2L_ADDRLO_S

#define EMAC_ADDR2L_ADDRLO_S   0

§ EMAC_ADDR3H_AE

#define EMAC_ADDR3H_AE   0x80000000

§ EMAC_ADDR3H_SA

#define EMAC_ADDR3H_SA   0x40000000

§ EMAC_ADDR3H_MBC_M

#define EMAC_ADDR3H_MBC_M   0x3F000000

§ EMAC_ADDR3H_ADDRHI_M

#define EMAC_ADDR3H_ADDRHI_M   0x0000FFFF

§ EMAC_ADDR3H_MBC_S

#define EMAC_ADDR3H_MBC_S   24

§ EMAC_ADDR3H_ADDRHI_S

#define EMAC_ADDR3H_ADDRHI_S   0

§ EMAC_ADDR3L_ADDRLO_M

#define EMAC_ADDR3L_ADDRLO_M   0xFFFFFFFF

§ EMAC_ADDR3L_ADDRLO_S

#define EMAC_ADDR3L_ADDRLO_S   0

§ EMAC_WDOGTO_PWE

#define EMAC_WDOGTO_PWE   0x00010000

Referenced by EMACConfigGet(), and EMACConfigSet().

§ EMAC_WDOGTO_WTO_M

#define EMAC_WDOGTO_WTO_M   0x00003FFF

Referenced by EMACConfigGet().

§ EMAC_WDOGTO_WTO_S

#define EMAC_WDOGTO_WTO_S   0

§ EMAC_MMCCTRL_UCDBC

#define EMAC_MMCCTRL_UCDBC   0x00000100

§ EMAC_MMCCTRL_CNTPRSTLVL

#define EMAC_MMCCTRL_CNTPRSTLVL   0x00000020

§ EMAC_MMCCTRL_CNTPRST

#define EMAC_MMCCTRL_CNTPRST   0x00000010

§ EMAC_MMCCTRL_CNTFREEZ

#define EMAC_MMCCTRL_CNTFREEZ   0x00000008

§ EMAC_MMCCTRL_RSTONRD

#define EMAC_MMCCTRL_RSTONRD   0x00000004

§ EMAC_MMCCTRL_CNTSTPRO

#define EMAC_MMCCTRL_CNTSTPRO   0x00000002

§ EMAC_MMCCTRL_CNTRST

#define EMAC_MMCCTRL_CNTRST   0x00000001

§ EMAC_MMCRXRIS_UCGF

#define EMAC_MMCRXRIS_UCGF   0x00020000

§ EMAC_MMCRXRIS_ALGNERR

#define EMAC_MMCRXRIS_ALGNERR   0x00000040

§ EMAC_MMCRXRIS_CRCERR

#define EMAC_MMCRXRIS_CRCERR   0x00000020

§ EMAC_MMCRXRIS_GBF

#define EMAC_MMCRXRIS_GBF   0x00000001

§ EMAC_MMCTXRIS_OCTCNT

#define EMAC_MMCTXRIS_OCTCNT   0x00100000

§ EMAC_MMCTXRIS_MCOLLGF

#define EMAC_MMCTXRIS_MCOLLGF   0x00008000

§ EMAC_MMCTXRIS_SCOLLGF

#define EMAC_MMCTXRIS_SCOLLGF   0x00004000

§ EMAC_MMCTXRIS_GBF

#define EMAC_MMCTXRIS_GBF   0x00000002

§ EMAC_MMCRXIM_UCGF

#define EMAC_MMCRXIM_UCGF   0x00020000

§ EMAC_MMCRXIM_ALGNERR

#define EMAC_MMCRXIM_ALGNERR   0x00000040

§ EMAC_MMCRXIM_CRCERR

#define EMAC_MMCRXIM_CRCERR   0x00000020

§ EMAC_MMCRXIM_GBF

#define EMAC_MMCRXIM_GBF   0x00000001

§ EMAC_MMCTXIM_OCTCNT

#define EMAC_MMCTXIM_OCTCNT   0x00100000

§ EMAC_MMCTXIM_MCOLLGF

#define EMAC_MMCTXIM_MCOLLGF   0x00008000

§ EMAC_MMCTXIM_SCOLLGF

#define EMAC_MMCTXIM_SCOLLGF   0x00004000

§ EMAC_MMCTXIM_GBF

#define EMAC_MMCTXIM_GBF   0x00000002

§ EMAC_TXCNTGB_TXFRMGB_M

#define EMAC_TXCNTGB_TXFRMGB_M   0xFFFFFFFF

§ EMAC_TXCNTGB_TXFRMGB_S

#define EMAC_TXCNTGB_TXFRMGB_S   0

§ EMAC_TXCNTSCOL_TXSNGLCOLG_M

#define EMAC_TXCNTSCOL_TXSNGLCOLG_M   0xFFFFFFFF

§ EMAC_TXCNTSCOL_TXSNGLCOLG_S

#define EMAC_TXCNTSCOL_TXSNGLCOLG_S   0

§ EMAC_TXCNTMCOL_TXMULTCOLG_M

#define EMAC_TXCNTMCOL_TXMULTCOLG_M   0xFFFFFFFF

§ EMAC_TXCNTMCOL_TXMULTCOLG_S

#define EMAC_TXCNTMCOL_TXMULTCOLG_S   0

§ EMAC_TXOCTCNTG_TXOCTG_M

#define EMAC_TXOCTCNTG_TXOCTG_M   0xFFFFFFFF

§ EMAC_TXOCTCNTG_TXOCTG_S

#define EMAC_TXOCTCNTG_TXOCTG_S   0

§ EMAC_RXCNTGB_RXFRMGB_M

#define EMAC_RXCNTGB_RXFRMGB_M   0xFFFFFFFF

§ EMAC_RXCNTGB_RXFRMGB_S

#define EMAC_RXCNTGB_RXFRMGB_S   0

§ EMAC_RXCNTCRCERR_RXCRCERR_M

#define EMAC_RXCNTCRCERR_RXCRCERR_M   0xFFFFFFFF

§ EMAC_RXCNTCRCERR_RXCRCERR_S

#define EMAC_RXCNTCRCERR_RXCRCERR_S   0

§ EMAC_RXCNTALGNERR_RXALGNERR_M

#define EMAC_RXCNTALGNERR_RXALGNERR_M   0xFFFFFFFF

§ EMAC_RXCNTALGNERR_RXALGNERR_S

#define EMAC_RXCNTALGNERR_RXALGNERR_S   0

§ EMAC_RXCNTGUNI_RXUCASTG_M

#define EMAC_RXCNTGUNI_RXUCASTG_M   0xFFFFFFFF

§ EMAC_RXCNTGUNI_RXUCASTG_S

#define EMAC_RXCNTGUNI_RXUCASTG_S   0

§ EMAC_VLNINCREP_CSVL

#define EMAC_VLNINCREP_CSVL   0x00080000

§ EMAC_VLNINCREP_VLP

#define EMAC_VLNINCREP_VLP   0x00040000

§ EMAC_VLNINCREP_VLC_M

#define EMAC_VLNINCREP_VLC_M   0x00030000

§ EMAC_VLNINCREP_VLC_NONE

#define EMAC_VLNINCREP_VLC_NONE   0x00000000

§ EMAC_VLNINCREP_VLC_TAGDEL

#define EMAC_VLNINCREP_VLC_TAGDEL   0x00010000

§ EMAC_VLNINCREP_VLC_TAGINS

#define EMAC_VLNINCREP_VLC_TAGINS   0x00020000

§ EMAC_VLNINCREP_VLC_TAGREP

#define EMAC_VLNINCREP_VLC_TAGREP   0x00030000

§ EMAC_VLNINCREP_VLT_M

#define EMAC_VLNINCREP_VLT_M   0x0000FFFF

Referenced by EMACVLANTxConfigGet().

§ EMAC_VLNINCREP_VLT_S

#define EMAC_VLNINCREP_VLT_S   0

§ EMAC_VLANHASH_VLHT_M

#define EMAC_VLANHASH_VLHT_M   0x0000FFFF

§ EMAC_VLANHASH_VLHT_S

#define EMAC_VLANHASH_VLHT_S   0

§ EMAC_TIMSTCTRL_PTPFLTR

#define EMAC_TIMSTCTRL_PTPFLTR   0x00040000

§ EMAC_TIMSTCTRL_SELPTP_M

#define EMAC_TIMSTCTRL_SELPTP_M   0x00030000

§ EMAC_TIMSTCTRL_TSMAST

#define EMAC_TIMSTCTRL_TSMAST   0x00008000

§ EMAC_TIMSTCTRL_TSEVNT

#define EMAC_TIMSTCTRL_TSEVNT   0x00004000

§ EMAC_TIMSTCTRL_PTPIPV4

#define EMAC_TIMSTCTRL_PTPIPV4   0x00002000

§ EMAC_TIMSTCTRL_PTPIPV6

#define EMAC_TIMSTCTRL_PTPIPV6   0x00001000

§ EMAC_TIMSTCTRL_PTPETH

#define EMAC_TIMSTCTRL_PTPETH   0x00000800

§ EMAC_TIMSTCTRL_PTPVER2

#define EMAC_TIMSTCTRL_PTPVER2   0x00000400

§ EMAC_TIMSTCTRL_DGTLBIN

#define EMAC_TIMSTCTRL_DGTLBIN   0x00000200

§ EMAC_TIMSTCTRL_ALLF

#define EMAC_TIMSTCTRL_ALLF   0x00000100

§ EMAC_TIMSTCTRL_ADDREGUP

#define EMAC_TIMSTCTRL_ADDREGUP   0x00000020

Referenced by EMACTimestampAddendSet().

§ EMAC_TIMSTCTRL_INTTRIG

#define EMAC_TIMSTCTRL_INTTRIG   0x00000010

§ EMAC_TIMSTCTRL_TSUPDT

#define EMAC_TIMSTCTRL_TSUPDT   0x00000008

§ EMAC_TIMSTCTRL_TSINIT

#define EMAC_TIMSTCTRL_TSINIT   0x00000004

§ EMAC_TIMSTCTRL_TSFCUPDT

#define EMAC_TIMSTCTRL_TSFCUPDT   0x00000002

§ EMAC_TIMSTCTRL_TSEN

#define EMAC_TIMSTCTRL_TSEN   0x00000001

§ EMAC_TIMSTCTRL_SELPTP_S

#define EMAC_TIMSTCTRL_SELPTP_S   16

§ EMAC_SUBSECINC_SSINC_M

#define EMAC_SUBSECINC_SSINC_M   0x000000FF

§ EMAC_SUBSECINC_SSINC_S

#define EMAC_SUBSECINC_SSINC_S   0

§ EMAC_TIMSEC_TSS_M

#define EMAC_TIMSEC_TSS_M   0xFFFFFFFF

§ EMAC_TIMSEC_TSS_S

#define EMAC_TIMSEC_TSS_S   0

§ EMAC_TIMNANO_TSSS_M

#define EMAC_TIMNANO_TSSS_M   0x7FFFFFFF

§ EMAC_TIMNANO_TSSS_S

#define EMAC_TIMNANO_TSSS_S   0

§ EMAC_TIMSECU_TSS_M

#define EMAC_TIMSECU_TSS_M   0xFFFFFFFF

§ EMAC_TIMSECU_TSS_S

#define EMAC_TIMSECU_TSS_S   0

§ EMAC_TIMNANOU_ADDSUB

#define EMAC_TIMNANOU_ADDSUB   0x80000000

§ EMAC_TIMNANOU_TSSS_M

#define EMAC_TIMNANOU_TSSS_M   0x7FFFFFFF

§ EMAC_TIMNANOU_TSSS_S

#define EMAC_TIMNANOU_TSSS_S   0

§ EMAC_TIMADD_TSAR_M

#define EMAC_TIMADD_TSAR_M   0xFFFFFFFF

§ EMAC_TIMADD_TSAR_S

#define EMAC_TIMADD_TSAR_S   0

§ EMAC_TARGSEC_TSTR_M

#define EMAC_TARGSEC_TSTR_M   0xFFFFFFFF

§ EMAC_TARGSEC_TSTR_S

#define EMAC_TARGSEC_TSTR_S   0

§ EMAC_TARGNANO_TRGTBUSY

#define EMAC_TARGNANO_TRGTBUSY   0x80000000

Referenced by EMACTimestampTargetSet().

§ EMAC_TARGNANO_TTSLO_M

#define EMAC_TARGNANO_TTSLO_M   0x7FFFFFFF

§ EMAC_TARGNANO_TTSLO_S

#define EMAC_TARGNANO_TTSLO_S   0

§ EMAC_HWORDSEC_TSHWR_M

#define EMAC_HWORDSEC_TSHWR_M   0x0000FFFF

§ EMAC_HWORDSEC_TSHWR_S

#define EMAC_HWORDSEC_TSHWR_S   0

§ EMAC_TIMSTAT_TSTARGT

#define EMAC_TIMSTAT_TSTARGT   0x00000002

§ EMAC_TIMSTAT_TSSOVF

#define EMAC_TIMSTAT_TSSOVF   0x00000001

§ EMAC_PPSCTRL_TRGMODS0_M

#define EMAC_PPSCTRL_TRGMODS0_M   0x00000060

§ EMAC_PPSCTRL_TRGMODS0_INTONLY

#define EMAC_PPSCTRL_TRGMODS0_INTONLY   0x00000000

§ EMAC_PPSCTRL_TRGMODS0_INTPPS0

#define EMAC_PPSCTRL_TRGMODS0_INTPPS0   0x00000040

§ EMAC_PPSCTRL_TRGMODS0_PPS0ONLY

#define EMAC_PPSCTRL_TRGMODS0_PPS0ONLY   0x00000060

§ EMAC_PPSCTRL_PPSEN0

#define EMAC_PPSCTRL_PPSEN0   0x00000010

§ EMAC_PPSCTRL_PPSCTRL_M

#define EMAC_PPSCTRL_PPSCTRL_M   0x0000000F

§ EMAC_PPS0INTVL_PPS0INT_M

#define EMAC_PPS0INTVL_PPS0INT_M   0xFFFFFFFF

§ EMAC_PPS0INTVL_PPS0INT_S

#define EMAC_PPS0INTVL_PPS0INT_S   0

§ EMAC_PPS0WIDTH_M

#define EMAC_PPS0WIDTH_M   0xFFFFFFFF

§ EMAC_PPS0WIDTH_S

#define EMAC_PPS0WIDTH_S   0

§ EMAC_DMABUSMOD_RIB

#define EMAC_DMABUSMOD_RIB   0x80000000

§ EMAC_DMABUSMOD_TXPR

#define EMAC_DMABUSMOD_TXPR   0x08000000

§ EMAC_DMABUSMOD_MB

#define EMAC_DMABUSMOD_MB   0x04000000

§ EMAC_DMABUSMOD_AAL

#define EMAC_DMABUSMOD_AAL   0x02000000

§ EMAC_DMABUSMOD_8XPBL

#define EMAC_DMABUSMOD_8XPBL   0x01000000

Referenced by EMACInit().

§ EMAC_DMABUSMOD_USP

#define EMAC_DMABUSMOD_USP   0x00800000

Referenced by EMACInit().

§ EMAC_DMABUSMOD_RPBL_M

#define EMAC_DMABUSMOD_RPBL_M   0x007E0000

§ EMAC_DMABUSMOD_FB

#define EMAC_DMABUSMOD_FB   0x00010000

§ EMAC_DMABUSMOD_PR_M

#define EMAC_DMABUSMOD_PR_M   0x0000C000

§ EMAC_DMABUSMOD_PBL_M

#define EMAC_DMABUSMOD_PBL_M   0x00003F00

§ EMAC_DMABUSMOD_ATDS

#define EMAC_DMABUSMOD_ATDS   0x00000080

Referenced by EMACInit().

§ EMAC_DMABUSMOD_DSL_M

#define EMAC_DMABUSMOD_DSL_M   0x0000007C

§ EMAC_DMABUSMOD_DA

#define EMAC_DMABUSMOD_DA   0x00000002

§ EMAC_DMABUSMOD_SWR

#define EMAC_DMABUSMOD_SWR   0x00000001

Referenced by EMACInit(), and EMACReset().

§ EMAC_DMABUSMOD_RPBL_S

#define EMAC_DMABUSMOD_RPBL_S   17

Referenced by EMACInit().

§ EMAC_DMABUSMOD_PR_S

#define EMAC_DMABUSMOD_PR_S   14

§ EMAC_DMABUSMOD_PBL_S

#define EMAC_DMABUSMOD_PBL_S   8

Referenced by EMACInit().

§ EMAC_DMABUSMOD_DSL_S

#define EMAC_DMABUSMOD_DSL_S   2

Referenced by EMACInit().

§ EMAC_TXPOLLD_TPD_M

#define EMAC_TXPOLLD_TPD_M   0xFFFFFFFF

§ EMAC_TXPOLLD_TPD_S

#define EMAC_TXPOLLD_TPD_S   0

§ EMAC_RXPOLLD_RPD_M

#define EMAC_RXPOLLD_RPD_M   0xFFFFFFFF

§ EMAC_RXPOLLD_RPD_S

#define EMAC_RXPOLLD_RPD_S   0

§ EMAC_RXDLADDR_STRXLIST_M

#define EMAC_RXDLADDR_STRXLIST_M   0xFFFFFFFC

§ EMAC_RXDLADDR_STRXLIST_S

#define EMAC_RXDLADDR_STRXLIST_S   2

§ EMAC_TXDLADDR_TXDLADDR_M

#define EMAC_TXDLADDR_TXDLADDR_M   0xFFFFFFFC

§ EMAC_TXDLADDR_TXDLADDR_S

#define EMAC_TXDLADDR_TXDLADDR_S   2

§ EMAC_DMARIS_LPI

#define EMAC_DMARIS_LPI   0x40000000

§ EMAC_DMARIS_TT

#define EMAC_DMARIS_TT   0x20000000

§ EMAC_DMARIS_PMT

#define EMAC_DMARIS_PMT   0x10000000

§ EMAC_DMARIS_MMC

#define EMAC_DMARIS_MMC   0x08000000

§ EMAC_DMARIS_AE_M

#define EMAC_DMARIS_AE_M   0x03800000

Referenced by EMACDMAStateGet(), and EMACIntStatus().

§ EMAC_DMARIS_AE_RXDMAWD

#define EMAC_DMARIS_AE_RXDMAWD   0x00000000

§ EMAC_DMARIS_AE_TXDMARD

#define EMAC_DMARIS_AE_TXDMARD   0x01800000

§ EMAC_DMARIS_AE_RXDMADW

#define EMAC_DMARIS_AE_RXDMADW   0x02000000

§ EMAC_DMARIS_AE_TXDMADW

#define EMAC_DMARIS_AE_TXDMADW   0x02800000

§ EMAC_DMARIS_AE_RXDMADR

#define EMAC_DMARIS_AE_RXDMADR   0x03000000

§ EMAC_DMARIS_AE_TXDMADR

#define EMAC_DMARIS_AE_TXDMADR   0x03800000

§ EMAC_DMARIS_TS_M

#define EMAC_DMARIS_TS_M   0x00700000

Referenced by EMACDMAStateGet(), and EMACIntStatus().

§ EMAC_DMARIS_TS_STOP

#define EMAC_DMARIS_TS_STOP   0x00000000

§ EMAC_DMARIS_TS_RUNTXTD

#define EMAC_DMARIS_TS_RUNTXTD   0x00100000

§ EMAC_DMARIS_TS_STATUS

#define EMAC_DMARIS_TS_STATUS   0x00200000

§ EMAC_DMARIS_TS_RUNTX

#define EMAC_DMARIS_TS_RUNTX   0x00300000

§ EMAC_DMARIS_TS_TSTAMP

#define EMAC_DMARIS_TS_TSTAMP   0x00400000

§ EMAC_DMARIS_TS_SUSPEND

#define EMAC_DMARIS_TS_SUSPEND   0x00600000

§ EMAC_DMARIS_TS_RUNCTD

#define EMAC_DMARIS_TS_RUNCTD   0x00700000

§ EMAC_DMARIS_RS_M

#define EMAC_DMARIS_RS_M   0x000E0000

Referenced by EMACDMAStateGet(), and EMACIntStatus().

§ EMAC_DMARIS_RS_STOP

#define EMAC_DMARIS_RS_STOP   0x00000000

§ EMAC_DMARIS_RS_RUNRXTD

#define EMAC_DMARIS_RS_RUNRXTD   0x00020000

§ EMAC_DMARIS_RS_RUNRXD

#define EMAC_DMARIS_RS_RUNRXD   0x00060000

§ EMAC_DMARIS_RS_SUSPEND

#define EMAC_DMARIS_RS_SUSPEND   0x00080000

§ EMAC_DMARIS_RS_RUNCRD

#define EMAC_DMARIS_RS_RUNCRD   0x000A0000

§ EMAC_DMARIS_RS_TSWS

#define EMAC_DMARIS_RS_TSWS   0x000C0000

§ EMAC_DMARIS_RS_RUNTXD

#define EMAC_DMARIS_RS_RUNTXD   0x000E0000

§ EMAC_DMARIS_NIS

#define EMAC_DMARIS_NIS   0x00010000

§ EMAC_DMARIS_AIS

#define EMAC_DMARIS_AIS   0x00008000

§ EMAC_DMARIS_ERI

#define EMAC_DMARIS_ERI   0x00004000

§ EMAC_DMARIS_FBI

#define EMAC_DMARIS_FBI   0x00002000

Referenced by EMACDMAStateGet().

§ EMAC_DMARIS_ETI

#define EMAC_DMARIS_ETI   0x00000400

§ EMAC_DMARIS_RWT

#define EMAC_DMARIS_RWT   0x00000200

§ EMAC_DMARIS_RPS

#define EMAC_DMARIS_RPS   0x00000100

§ EMAC_DMARIS_RU

#define EMAC_DMARIS_RU   0x00000080

§ EMAC_DMARIS_RI

#define EMAC_DMARIS_RI   0x00000040

§ EMAC_DMARIS_UNF

#define EMAC_DMARIS_UNF   0x00000020

§ EMAC_DMARIS_OVF

#define EMAC_DMARIS_OVF   0x00000010

§ EMAC_DMARIS_TJT

#define EMAC_DMARIS_TJT   0x00000008

§ EMAC_DMARIS_TU

#define EMAC_DMARIS_TU   0x00000004

§ EMAC_DMARIS_TPS

#define EMAC_DMARIS_TPS   0x00000002

§ EMAC_DMARIS_TI

#define EMAC_DMARIS_TI   0x00000001

Referenced by EMACWoLEnter().

§ EMAC_DMAOPMODE_DT

#define EMAC_DMAOPMODE_DT   0x04000000

§ EMAC_DMAOPMODE_RSF

#define EMAC_DMAOPMODE_RSF   0x02000000

§ EMAC_DMAOPMODE_DFF

#define EMAC_DMAOPMODE_DFF   0x01000000

§ EMAC_DMAOPMODE_TSF

#define EMAC_DMAOPMODE_TSF   0x00200000

§ EMAC_DMAOPMODE_FTF

#define EMAC_DMAOPMODE_FTF   0x00100000

Referenced by EMACTxFlush().

§ EMAC_DMAOPMODE_TTC_M

#define EMAC_DMAOPMODE_TTC_M   0x0001C000

§ EMAC_DMAOPMODE_TTC_64

#define EMAC_DMAOPMODE_TTC_64   0x00000000

§ EMAC_DMAOPMODE_TTC_128

#define EMAC_DMAOPMODE_TTC_128   0x00004000

§ EMAC_DMAOPMODE_TTC_192

#define EMAC_DMAOPMODE_TTC_192   0x00008000

§ EMAC_DMAOPMODE_TTC_256

#define EMAC_DMAOPMODE_TTC_256   0x0000C000

§ EMAC_DMAOPMODE_TTC_40

#define EMAC_DMAOPMODE_TTC_40   0x00010000

§ EMAC_DMAOPMODE_TTC_32

#define EMAC_DMAOPMODE_TTC_32   0x00014000

§ EMAC_DMAOPMODE_TTC_24

#define EMAC_DMAOPMODE_TTC_24   0x00018000

§ EMAC_DMAOPMODE_TTC_16

#define EMAC_DMAOPMODE_TTC_16   0x0001C000

§ EMAC_DMAOPMODE_ST

#define EMAC_DMAOPMODE_ST   0x00002000

§ EMAC_DMAOPMODE_FEF

#define EMAC_DMAOPMODE_FEF   0x00000080

§ EMAC_DMAOPMODE_FUF

#define EMAC_DMAOPMODE_FUF   0x00000040

§ EMAC_DMAOPMODE_DGF

#define EMAC_DMAOPMODE_DGF   0x00000020

§ EMAC_DMAOPMODE_RTC_M

#define EMAC_DMAOPMODE_RTC_M   0x00000018

§ EMAC_DMAOPMODE_RTC_64

#define EMAC_DMAOPMODE_RTC_64   0x00000000

§ EMAC_DMAOPMODE_RTC_32

#define EMAC_DMAOPMODE_RTC_32   0x00000008

§ EMAC_DMAOPMODE_RTC_96

#define EMAC_DMAOPMODE_RTC_96   0x00000010

§ EMAC_DMAOPMODE_RTC_128

#define EMAC_DMAOPMODE_RTC_128   0x00000018

§ EMAC_DMAOPMODE_OSF

#define EMAC_DMAOPMODE_OSF   0x00000004

§ EMAC_DMAOPMODE_SR

#define EMAC_DMAOPMODE_SR   0x00000002

§ EMAC_DMAIM_NIE

#define EMAC_DMAIM_NIE   0x00010000

§ EMAC_DMAIM_AIE

#define EMAC_DMAIM_AIE   0x00008000

§ EMAC_DMAIM_ERE

#define EMAC_DMAIM_ERE   0x00004000

§ EMAC_DMAIM_FBE

#define EMAC_DMAIM_FBE   0x00002000

§ EMAC_DMAIM_ETE

#define EMAC_DMAIM_ETE   0x00000400

§ EMAC_DMAIM_RWE

#define EMAC_DMAIM_RWE   0x00000200

§ EMAC_DMAIM_RSE

#define EMAC_DMAIM_RSE   0x00000100

§ EMAC_DMAIM_RUE

#define EMAC_DMAIM_RUE   0x00000080

§ EMAC_DMAIM_RIE

#define EMAC_DMAIM_RIE   0x00000040

§ EMAC_DMAIM_UNE

#define EMAC_DMAIM_UNE   0x00000020

§ EMAC_DMAIM_OVE

#define EMAC_DMAIM_OVE   0x00000010

§ EMAC_DMAIM_TJE

#define EMAC_DMAIM_TJE   0x00000008

§ EMAC_DMAIM_TUE

#define EMAC_DMAIM_TUE   0x00000004

§ EMAC_DMAIM_TSE

#define EMAC_DMAIM_TSE   0x00000002

§ EMAC_DMAIM_TIE

#define EMAC_DMAIM_TIE   0x00000001

§ EMAC_MFBOC_OVFCNTOVF

#define EMAC_MFBOC_OVFCNTOVF   0x10000000

§ EMAC_MFBOC_OVFFRMCNT_M

#define EMAC_MFBOC_OVFFRMCNT_M   0x0FFE0000

§ EMAC_MFBOC_MISCNTOVF

#define EMAC_MFBOC_MISCNTOVF   0x00010000

§ EMAC_MFBOC_MISFRMCNT_M

#define EMAC_MFBOC_MISFRMCNT_M   0x0000FFFF

§ EMAC_MFBOC_OVFFRMCNT_S

#define EMAC_MFBOC_OVFFRMCNT_S   17

§ EMAC_MFBOC_MISFRMCNT_S

#define EMAC_MFBOC_MISFRMCNT_S   0

§ EMAC_RXINTWDT_RIWT_M

#define EMAC_RXINTWDT_RIWT_M   0x000000FF

§ EMAC_RXINTWDT_RIWT_S

#define EMAC_RXINTWDT_RIWT_S   0

§ EMAC_HOSTXDESC_CURTXDESC_M

#define EMAC_HOSTXDESC_CURTXDESC_M   0xFFFFFFFF

§ EMAC_HOSTXDESC_CURTXDESC_S

#define EMAC_HOSTXDESC_CURTXDESC_S   0

§ EMAC_HOSRXDESC_CURRXDESC_M

#define EMAC_HOSRXDESC_CURRXDESC_M   0xFFFFFFFF

§ EMAC_HOSRXDESC_CURRXDESC_S

#define EMAC_HOSRXDESC_CURRXDESC_S   0

§ EMAC_HOSTXBA_CURTXBUFA_M

#define EMAC_HOSTXBA_CURTXBUFA_M   0xFFFFFFFF

§ EMAC_HOSTXBA_CURTXBUFA_S

#define EMAC_HOSTXBA_CURTXBUFA_S   0

§ EMAC_HOSRXBA_CURRXBUFA_M

#define EMAC_HOSRXBA_CURRXBUFA_M   0xFFFFFFFF

§ EMAC_HOSRXBA_CURRXBUFA_S

#define EMAC_HOSRXBA_CURRXBUFA_S   0

§ EMAC_PP_MACTYPE_M

#define EMAC_PP_MACTYPE_M   0x00000700

§ EMAC_PP_MACTYPE_1

#define EMAC_PP_MACTYPE_1   0x00000100

§ EMAC_PP_PHYTYPE_M

#define EMAC_PP_PHYTYPE_M   0x00000007

§ EMAC_PP_PHYTYPE_NONE

#define EMAC_PP_PHYTYPE_NONE   0x00000000

§ EMAC_PP_PHYTYPE_1

#define EMAC_PP_PHYTYPE_1   0x00000003

§ EMAC_PC_PHYEXT

#define EMAC_PC_PHYEXT   0x80000000

§ EMAC_PC_PINTFS_M

#define EMAC_PC_PINTFS_M   0x70000000

§ EMAC_PC_PINTFS_IMII

#define EMAC_PC_PINTFS_IMII   0x00000000

§ EMAC_PC_PINTFS_RMII

#define EMAC_PC_PINTFS_RMII   0x40000000

§ EMAC_PC_DIGRESTART

#define EMAC_PC_DIGRESTART   0x02000000

§ EMAC_PC_NIBDETDIS

#define EMAC_PC_NIBDETDIS   0x01000000

§ EMAC_PC_RXERIDLE

#define EMAC_PC_RXERIDLE   0x00800000

§ EMAC_PC_ISOMIILL

#define EMAC_PC_ISOMIILL   0x00400000

§ EMAC_PC_LRR

#define EMAC_PC_LRR   0x00200000

§ EMAC_PC_TDRRUN

#define EMAC_PC_TDRRUN   0x00100000

§ EMAC_PC_FASTLDMODE_M

#define EMAC_PC_FASTLDMODE_M   0x000F8000

§ EMAC_PC_POLSWAP

#define EMAC_PC_POLSWAP   0x00004000

§ EMAC_PC_MDISWAP

#define EMAC_PC_MDISWAP   0x00002000

§ EMAC_PC_RBSTMDIX

#define EMAC_PC_RBSTMDIX   0x00001000

§ EMAC_PC_FASTMDIX

#define EMAC_PC_FASTMDIX   0x00000800

§ EMAC_PC_MDIXEN

#define EMAC_PC_MDIXEN   0x00000400

§ EMAC_PC_FASTRXDV

#define EMAC_PC_FASTRXDV   0x00000200

§ EMAC_PC_FASTLUPD

#define EMAC_PC_FASTLUPD   0x00000100

§ EMAC_PC_EXTFD

#define EMAC_PC_EXTFD   0x00000080

§ EMAC_PC_FASTANEN

#define EMAC_PC_FASTANEN   0x00000040

§ EMAC_PC_FASTANSEL_M

#define EMAC_PC_FASTANSEL_M   0x00000030

§ EMAC_PC_ANEN

#define EMAC_PC_ANEN   0x00000008

§ EMAC_PC_ANMODE_M

#define EMAC_PC_ANMODE_M   0x00000006

§ EMAC_PC_ANMODE_10HD

#define EMAC_PC_ANMODE_10HD   0x00000000

§ EMAC_PC_ANMODE_10FD

#define EMAC_PC_ANMODE_10FD   0x00000002

§ EMAC_PC_ANMODE_100HD

#define EMAC_PC_ANMODE_100HD   0x00000004

§ EMAC_PC_ANMODE_100FD

#define EMAC_PC_ANMODE_100FD   0x00000006

§ EMAC_PC_PHYHOLD

#define EMAC_PC_PHYHOLD   0x00000001

§ EMAC_PC_FASTLDMODE_S

#define EMAC_PC_FASTLDMODE_S   15

§ EMAC_PC_FASTANSEL_S

#define EMAC_PC_FASTANSEL_S   4

§ EMAC_CC_PTPCEN

#define EMAC_CC_PTPCEN   0x00040000

Referenced by EMACTimestampConfigSet().

§ EMAC_CC_POL

#define EMAC_CC_POL   0x00020000

§ EMAC_CC_CLKEN

#define EMAC_CC_CLKEN   0x00010000

Referenced by EMACPHYConfigSet().

§ EMAC_EPHYRIS_INT

#define EMAC_EPHYRIS_INT   0x00000001

§ EMAC_EPHYIM_INT

#define EMAC_EPHYIM_INT   0x00000001

Referenced by EMACIntDisable(), and EMACIntEnable().

§ EMAC_EPHYMISC_INT

#define EMAC_EPHYMISC_INT   0x00000001

Referenced by EMACIntClear(), and EMACIntStatus().

§ EPHY_BMCR

#define EPHY_BMCR   0x00000000

Referenced by EMACPHYPowerOff(), and EMACPHYPowerOn().

§ EPHY_BMSR

#define EPHY_BMSR   0x00000001

§ EPHY_ID1

#define EPHY_ID1   0x00000002

§ EPHY_ID2

#define EPHY_ID2   0x00000003

§ EPHY_ANA

#define EPHY_ANA   0x00000004

§ EPHY_ANLPA

#define EPHY_ANLPA   0x00000005

§ EPHY_ANER

#define EPHY_ANER   0x00000006

§ EPHY_ANNPTR

#define EPHY_ANNPTR   0x00000007

§ EPHY_ANLNPTR

#define EPHY_ANLNPTR   0x00000008

§ EPHY_CFG1

#define EPHY_CFG1   0x00000009

§ EPHY_CFG2

#define EPHY_CFG2   0x0000000A

§ EPHY_CFG3

#define EPHY_CFG3   0x0000000B

§ EPHY_REGCTL

#define EPHY_REGCTL   0x0000000D

§ EPHY_ADDAR

#define EPHY_ADDAR   0x0000000E

§ EPHY_STS

#define EPHY_STS   0x00000010

§ EPHY_SCR

#define EPHY_SCR   0x00000011

§ EPHY_MISR1

#define EPHY_MISR1   0x00000012

§ EPHY_MISR2

#define EPHY_MISR2   0x00000013

§ EPHY_FCSCR

#define EPHY_FCSCR   0x00000014

§ EPHY_RXERCNT

#define EPHY_RXERCNT   0x00000015

§ EPHY_BISTCR

#define EPHY_BISTCR   0x00000016

§ EPHY_LEDCR

#define EPHY_LEDCR   0x00000018

§ EPHY_CTL

#define EPHY_CTL   0x00000019

§ EPHY_10BTSC

#define EPHY_10BTSC   0x0000001A

§ EPHY_BICSR1

#define EPHY_BICSR1   0x0000001B

§ EPHY_BICSR2

#define EPHY_BICSR2   0x0000001C

§ EPHY_CDCR

#define EPHY_CDCR   0x0000001E

§ EPHY_RCR

#define EPHY_RCR   0x0000001F

§ EPHY_LEDCFG

#define EPHY_LEDCFG   0x00000025

§ EPHY_BMCR_MIIRESET

#define EPHY_BMCR_MIIRESET   0x00008000

§ EPHY_BMCR_MIILOOPBK

#define EPHY_BMCR_MIILOOPBK   0x00004000

§ EPHY_BMCR_SPEED

#define EPHY_BMCR_SPEED   0x00002000

§ EPHY_BMCR_ANEN

#define EPHY_BMCR_ANEN   0x00001000

Referenced by EMACPHYPowerOff(), and EMACPHYPowerOn().

§ EPHY_BMCR_PWRDWN

#define EPHY_BMCR_PWRDWN   0x00000800

Referenced by EMACPHYPowerOff(), and EMACPHYPowerOn().

§ EPHY_BMCR_ISOLATE

#define EPHY_BMCR_ISOLATE   0x00000400

§ EPHY_BMCR_RESTARTAN

#define EPHY_BMCR_RESTARTAN   0x00000200

§ EPHY_BMCR_DUPLEXM

#define EPHY_BMCR_DUPLEXM   0x00000100

§ EPHY_BMCR_COLLTST

#define EPHY_BMCR_COLLTST   0x00000080

§ EPHY_BMSR_100BTXFD

#define EPHY_BMSR_100BTXFD   0x00004000

§ EPHY_BMSR_100BTXHD

#define EPHY_BMSR_100BTXHD   0x00002000

§ EPHY_BMSR_10BTFD

#define EPHY_BMSR_10BTFD   0x00001000

§ EPHY_BMSR_10BTHD

#define EPHY_BMSR_10BTHD   0x00000800

§ EPHY_BMSR_MFPRESUP

#define EPHY_BMSR_MFPRESUP   0x00000040

§ EPHY_BMSR_ANC

#define EPHY_BMSR_ANC   0x00000020

§ EPHY_BMSR_RFAULT

#define EPHY_BMSR_RFAULT   0x00000010

§ EPHY_BMSR_ANEN

#define EPHY_BMSR_ANEN   0x00000008

§ EPHY_BMSR_LINKSTAT

#define EPHY_BMSR_LINKSTAT   0x00000004

§ EPHY_BMSR_JABBER

#define EPHY_BMSR_JABBER   0x00000002

§ EPHY_BMSR_EXTEN

#define EPHY_BMSR_EXTEN   0x00000001

§ EPHY_ID1_OUIMSB_M

#define EPHY_ID1_OUIMSB_M   0x0000FFFF

§ EPHY_ID1_OUIMSB_S

#define EPHY_ID1_OUIMSB_S   0

§ EPHY_ID2_OUILSB_M

#define EPHY_ID2_OUILSB_M   0x0000FC00

§ EPHY_ID2_VNDRMDL_M

#define EPHY_ID2_VNDRMDL_M   0x000003F0

§ EPHY_ID2_MDLREV_M

#define EPHY_ID2_MDLREV_M   0x0000000F

§ EPHY_ID2_OUILSB_S

#define EPHY_ID2_OUILSB_S   10

§ EPHY_ID2_VNDRMDL_S

#define EPHY_ID2_VNDRMDL_S   4

§ EPHY_ID2_MDLREV_S

#define EPHY_ID2_MDLREV_S   0

§ EPHY_ANA_NP

#define EPHY_ANA_NP   0x00008000

§ EPHY_ANA_RF

#define EPHY_ANA_RF   0x00002000

§ EPHY_ANA_ASMDUP

#define EPHY_ANA_ASMDUP   0x00000800

§ EPHY_ANA_PAUSE

#define EPHY_ANA_PAUSE   0x00000400

§ EPHY_ANA_100BT4

#define EPHY_ANA_100BT4   0x00000200

§ EPHY_ANA_100BTXFD

#define EPHY_ANA_100BTXFD   0x00000100

§ EPHY_ANA_100BTX

#define EPHY_ANA_100BTX   0x00000080

§ EPHY_ANA_10BTFD

#define EPHY_ANA_10BTFD   0x00000040

§ EPHY_ANA_10BT

#define EPHY_ANA_10BT   0x00000020

§ EPHY_ANA_SELECT_M

#define EPHY_ANA_SELECT_M   0x0000001F

§ EPHY_ANA_SELECT_S

#define EPHY_ANA_SELECT_S   0

§ EPHY_ANLPA_NP

#define EPHY_ANLPA_NP   0x00008000

§ EPHY_ANLPA_ACK

#define EPHY_ANLPA_ACK   0x00004000

§ EPHY_ANLPA_RF

#define EPHY_ANLPA_RF   0x00002000

§ EPHY_ANLPA_ASMDUP

#define EPHY_ANLPA_ASMDUP   0x00000800

§ EPHY_ANLPA_PAUSE

#define EPHY_ANLPA_PAUSE   0x00000400

§ EPHY_ANLPA_100BT4

#define EPHY_ANLPA_100BT4   0x00000200

§ EPHY_ANLPA_100BTXFD

#define EPHY_ANLPA_100BTXFD   0x00000100

§ EPHY_ANLPA_100BTX

#define EPHY_ANLPA_100BTX   0x00000080

§ EPHY_ANLPA_10BTFD

#define EPHY_ANLPA_10BTFD   0x00000040

§ EPHY_ANLPA_10BT

#define EPHY_ANLPA_10BT   0x00000020

§ EPHY_ANLPA_SELECT_M

#define EPHY_ANLPA_SELECT_M   0x0000001F

§ EPHY_ANLPA_SELECT_S

#define EPHY_ANLPA_SELECT_S   0

§ EPHY_ANER_PDF

#define EPHY_ANER_PDF   0x00000010

§ EPHY_ANER_LPNPABLE

#define EPHY_ANER_LPNPABLE   0x00000008

§ EPHY_ANER_NPABLE

#define EPHY_ANER_NPABLE   0x00000004

§ EPHY_ANER_PAGERX

#define EPHY_ANER_PAGERX   0x00000002

§ EPHY_ANER_LPANABLE

#define EPHY_ANER_LPANABLE   0x00000001

§ EPHY_ANNPTR_NP

#define EPHY_ANNPTR_NP   0x00008000

§ EPHY_ANNPTR_MP

#define EPHY_ANNPTR_MP   0x00002000

§ EPHY_ANNPTR_ACK2

#define EPHY_ANNPTR_ACK2   0x00001000

§ EPHY_ANNPTR_TOGTX

#define EPHY_ANNPTR_TOGTX   0x00000800

§ EPHY_ANNPTR_CODE_M

#define EPHY_ANNPTR_CODE_M   0x000007FF

§ EPHY_ANNPTR_CODE_S

#define EPHY_ANNPTR_CODE_S   0

§ EPHY_ANLNPTR_NP

#define EPHY_ANLNPTR_NP   0x00008000

§ EPHY_ANLNPTR_ACK

#define EPHY_ANLNPTR_ACK   0x00004000

§ EPHY_ANLNPTR_MP

#define EPHY_ANLNPTR_MP   0x00002000

§ EPHY_ANLNPTR_ACK2

#define EPHY_ANLNPTR_ACK2   0x00001000

§ EPHY_ANLNPTR_TOG

#define EPHY_ANLNPTR_TOG   0x00000800

§ EPHY_ANLNPTR_CODE_M

#define EPHY_ANLNPTR_CODE_M   0x000007FF

§ EPHY_ANLNPTR_CODE_S

#define EPHY_ANLNPTR_CODE_S   0

§ EPHY_CFG1_DONE

#define EPHY_CFG1_DONE   0x00008000

§ EPHY_CFG1_TDRAR

#define EPHY_CFG1_TDRAR   0x00000100

§ EPHY_CFG1_LLR

#define EPHY_CFG1_LLR   0x00000080

§ EPHY_CFG1_FAMDIX

#define EPHY_CFG1_FAMDIX   0x00000040

§ EPHY_CFG1_RAMDIX

#define EPHY_CFG1_RAMDIX   0x00000020

§ EPHY_CFG1_FASTANEN

#define EPHY_CFG1_FASTANEN   0x00000010

§ EPHY_CFG1_FANSEL_M

#define EPHY_CFG1_FANSEL_M   0x0000000C

§ EPHY_CFG1_FANSEL_BLT80

#define EPHY_CFG1_FANSEL_BLT80   0x00000000

§ EPHY_CFG1_FANSEL_BLT120

#define EPHY_CFG1_FANSEL_BLT120   0x00000004

§ EPHY_CFG1_FANSEL_BLT240

#define EPHY_CFG1_FANSEL_BLT240   0x00000008

§ EPHY_CFG1_FRXDVDET

#define EPHY_CFG1_FRXDVDET   0x00000002

§ EPHY_CFG2_FLUPPD

#define EPHY_CFG2_FLUPPD   0x00000040

§ EPHY_CFG2_EXTFD

#define EPHY_CFG2_EXTFD   0x00000020

§ EPHY_CFG2_ENLEDLINK

#define EPHY_CFG2_ENLEDLINK   0x00000010

§ EPHY_CFG2_ISOMIILL

#define EPHY_CFG2_ISOMIILL   0x00000008

§ EPHY_CFG2_RXERRIDLE

#define EPHY_CFG2_RXERRIDLE   0x00000004

§ EPHY_CFG2_ODDNDETDIS

#define EPHY_CFG2_ODDNDETDIS   0x00000002

§ EPHY_CFG3_POLSWAP

#define EPHY_CFG3_POLSWAP   0x00000080

§ EPHY_CFG3_MDIMDIXS

#define EPHY_CFG3_MDIMDIXS   0x00000040

§ EPHY_CFG3_FLDWNM_M

#define EPHY_CFG3_FLDWNM_M   0x0000001F

§ EPHY_CFG3_FLDWNM_S

#define EPHY_CFG3_FLDWNM_S   0

§ EPHY_REGCTL_FUNC_M

#define EPHY_REGCTL_FUNC_M   0x0000C000

§ EPHY_REGCTL_FUNC_ADDR

#define EPHY_REGCTL_FUNC_ADDR   0x00000000

§ EPHY_REGCTL_FUNC_DATANI

#define EPHY_REGCTL_FUNC_DATANI   0x00004000

§ EPHY_REGCTL_FUNC_DATAPIRW

#define EPHY_REGCTL_FUNC_DATAPIRW   0x00008000

§ EPHY_REGCTL_FUNC_DATAPIWO

#define EPHY_REGCTL_FUNC_DATAPIWO   0x0000C000

§ EPHY_REGCTL_DEVAD_M

#define EPHY_REGCTL_DEVAD_M   0x0000001F

§ EPHY_REGCTL_DEVAD_S

#define EPHY_REGCTL_DEVAD_S   0

§ EPHY_ADDAR_ADDRDATA_M

#define EPHY_ADDAR_ADDRDATA_M   0x0000FFFF

§ EPHY_ADDAR_ADDRDATA_S

#define EPHY_ADDAR_ADDRDATA_S   0

§ EPHY_STS_MDIXM

#define EPHY_STS_MDIXM   0x00004000

§ EPHY_STS_RXLERR

#define EPHY_STS_RXLERR   0x00002000

§ EPHY_STS_POLSTAT

#define EPHY_STS_POLSTAT   0x00001000

§ EPHY_STS_FCSL

#define EPHY_STS_FCSL   0x00000800

§ EPHY_STS_SD

#define EPHY_STS_SD   0x00000400

§ EPHY_STS_DL

#define EPHY_STS_DL   0x00000200

§ EPHY_STS_PAGERX

#define EPHY_STS_PAGERX   0x00000100

§ EPHY_STS_MIIREQ

#define EPHY_STS_MIIREQ   0x00000080

§ EPHY_STS_RF

#define EPHY_STS_RF   0x00000040

§ EPHY_STS_JD

#define EPHY_STS_JD   0x00000020

§ EPHY_STS_ANS

#define EPHY_STS_ANS   0x00000010

§ EPHY_STS_MIILB

#define EPHY_STS_MIILB   0x00000008

§ EPHY_STS_DUPLEX

#define EPHY_STS_DUPLEX   0x00000004

§ EPHY_STS_SPEED

#define EPHY_STS_SPEED   0x00000002

§ EPHY_STS_LINK

#define EPHY_STS_LINK   0x00000001

§ EPHY_SCR_DISCLK

#define EPHY_SCR_DISCLK   0x00008000

§ EPHY_SCR_PSEN

#define EPHY_SCR_PSEN   0x00004000

§ EPHY_SCR_PSMODE_M

#define EPHY_SCR_PSMODE_M   0x00003000

§ EPHY_SCR_PSMODE_NORMAL

#define EPHY_SCR_PSMODE_NORMAL   0x00000000

§ EPHY_SCR_PSMODE_LOWPWR

#define EPHY_SCR_PSMODE_LOWPWR   0x00001000

§ EPHY_SCR_PSMODE_ACTWOL

#define EPHY_SCR_PSMODE_ACTWOL   0x00002000

§ EPHY_SCR_PSMODE_PASWOL

#define EPHY_SCR_PSMODE_PASWOL   0x00003000

§ EPHY_SCR_SBPYASS

#define EPHY_SCR_SBPYASS   0x00000800

§ EPHY_SCR_LBFIFO_M

#define EPHY_SCR_LBFIFO_M   0x00000300

§ EPHY_SCR_LBFIFO_4

#define EPHY_SCR_LBFIFO_4   0x00000000

§ EPHY_SCR_LBFIFO_5

#define EPHY_SCR_LBFIFO_5   0x00000100

§ EPHY_SCR_LBFIFO_6

#define EPHY_SCR_LBFIFO_6   0x00000200

§ EPHY_SCR_LBFIFO_8

#define EPHY_SCR_LBFIFO_8   0x00000300

§ EPHY_SCR_COLFDM

#define EPHY_SCR_COLFDM   0x00000010

§ EPHY_SCR_TINT

#define EPHY_SCR_TINT   0x00000004

§ EPHY_SCR_INTEN

#define EPHY_SCR_INTEN   0x00000002

§ EPHY_MISR1_LINKSTAT

#define EPHY_MISR1_LINKSTAT   0x00002000

§ EPHY_MISR1_SPEED

#define EPHY_MISR1_SPEED   0x00001000

§ EPHY_MISR1_DUPLEXM

#define EPHY_MISR1_DUPLEXM   0x00000800

§ EPHY_MISR1_ANC

#define EPHY_MISR1_ANC   0x00000400

§ EPHY_MISR1_FCHF

#define EPHY_MISR1_FCHF   0x00000200

§ EPHY_MISR1_RXHF

#define EPHY_MISR1_RXHF   0x00000100

§ EPHY_MISR1_LINKSTATEN

#define EPHY_MISR1_LINKSTATEN   0x00000020

§ EPHY_MISR1_SPEEDEN

#define EPHY_MISR1_SPEEDEN   0x00000010

§ EPHY_MISR1_DUPLEXMEN

#define EPHY_MISR1_DUPLEXMEN   0x00000008

§ EPHY_MISR1_ANCEN

#define EPHY_MISR1_ANCEN   0x00000004

§ EPHY_MISR1_FCHFEN

#define EPHY_MISR1_FCHFEN   0x00000002

§ EPHY_MISR1_RXHFEN

#define EPHY_MISR1_RXHFEN   0x00000001

§ EPHY_MISR2_ANERR

#define EPHY_MISR2_ANERR   0x00004000

§ EPHY_MISR2_PAGERX

#define EPHY_MISR2_PAGERX   0x00002000

§ EPHY_MISR2_LBFIFO

#define EPHY_MISR2_LBFIFO   0x00001000

§ EPHY_MISR2_MDICO

#define EPHY_MISR2_MDICO   0x00000800

§ EPHY_MISR2_SLEEP

#define EPHY_MISR2_SLEEP   0x00000400

§ EPHY_MISR2_POLINT

#define EPHY_MISR2_POLINT   0x00000200

§ EPHY_MISR2_JABBER

#define EPHY_MISR2_JABBER   0x00000100

§ EPHY_MISR2_ANERREN

#define EPHY_MISR2_ANERREN   0x00000040

§ EPHY_MISR2_PAGERXEN

#define EPHY_MISR2_PAGERXEN   0x00000020

§ EPHY_MISR2_LBFIFOEN

#define EPHY_MISR2_LBFIFOEN   0x00000010

§ EPHY_MISR2_MDICOEN

#define EPHY_MISR2_MDICOEN   0x00000008

§ EPHY_MISR2_SLEEPEN

#define EPHY_MISR2_SLEEPEN   0x00000004

§ EPHY_MISR2_POLINTEN

#define EPHY_MISR2_POLINTEN   0x00000002

§ EPHY_MISR2_JABBEREN

#define EPHY_MISR2_JABBEREN   0x00000001

§ EPHY_FCSCR_FCSCNT_M

#define EPHY_FCSCR_FCSCNT_M   0x000000FF

§ EPHY_FCSCR_FCSCNT_S

#define EPHY_FCSCR_FCSCNT_S   0

§ EPHY_RXERCNT_RXERRCNT_M

#define EPHY_RXERCNT_RXERRCNT_M   0x0000FFFF

§ EPHY_RXERCNT_RXERRCNT_S

#define EPHY_RXERCNT_RXERRCNT_S   0

§ EPHY_BISTCR_PRBSM

#define EPHY_BISTCR_PRBSM   0x00004000

§ EPHY_BISTCR_PRBSPKT

#define EPHY_BISTCR_PRBSPKT   0x00002000

§ EPHY_BISTCR_PKTEN

#define EPHY_BISTCR_PKTEN   0x00001000

§ EPHY_BISTCR_PRBSCHKLK

#define EPHY_BISTCR_PRBSCHKLK   0x00000800

§ EPHY_BISTCR_PRBSCHKSYNC

#define EPHY_BISTCR_PRBSCHKSYNC   0x00000400

§ EPHY_BISTCR_PKTGENSTAT

#define EPHY_BISTCR_PKTGENSTAT   0x00000200

§ EPHY_BISTCR_PWRMODE

#define EPHY_BISTCR_PWRMODE   0x00000100

§ EPHY_BISTCR_TXMIILB

#define EPHY_BISTCR_TXMIILB   0x00000040

§ EPHY_BISTCR_LBMODE_M

#define EPHY_BISTCR_LBMODE_M   0x0000001F

§ EPHY_BISTCR_LBMODE_NPCSIN

#define EPHY_BISTCR_LBMODE_NPCSIN   0x00000001

§ EPHY_BISTCR_LBMODE_NPCSOUT

#define EPHY_BISTCR_LBMODE_NPCSOUT   0x00000002

§ EPHY_BISTCR_LBMODE_NDIG

#define EPHY_BISTCR_LBMODE_NDIG   0x00000004

§ EPHY_BISTCR_LBMODE_NANA

#define EPHY_BISTCR_LBMODE_NANA   0x00000008

§ EPHY_BISTCR_LBMODE_FREV

#define EPHY_BISTCR_LBMODE_FREV   0x00000010

§ EPHY_LEDCR_BLINKRATE_M

#define EPHY_LEDCR_BLINKRATE_M   0x00000600

§ EPHY_LEDCR_BLINKRATE_20HZ

#define EPHY_LEDCR_BLINKRATE_20HZ   0x00000000

§ EPHY_LEDCR_BLINKRATE_10HZ

#define EPHY_LEDCR_BLINKRATE_10HZ   0x00000200

§ EPHY_LEDCR_BLINKRATE_5HZ

#define EPHY_LEDCR_BLINKRATE_5HZ   0x00000400

§ EPHY_LEDCR_BLINKRATE_2HZ

#define EPHY_LEDCR_BLINKRATE_2HZ   0x00000600

§ EPHY_CTL_AUTOMDI

#define EPHY_CTL_AUTOMDI   0x00008000

§ EPHY_CTL_FORCEMDI

#define EPHY_CTL_FORCEMDI   0x00004000

§ EPHY_CTL_PAUSERX

#define EPHY_CTL_PAUSERX   0x00002000

§ EPHY_CTL_PAUSETX

#define EPHY_CTL_PAUSETX   0x00001000

§ EPHY_CTL_MIILNKSTAT

#define EPHY_CTL_MIILNKSTAT   0x00000800

§ EPHY_CTL_BYPLEDSTRCH

#define EPHY_CTL_BYPLEDSTRCH   0x00000080

§ EPHY_10BTSC_RXTHEN

#define EPHY_10BTSC_RXTHEN   0x00002000

§ EPHY_10BTSC_SQUELCH_M

#define EPHY_10BTSC_SQUELCH_M   0x00001E00

§ EPHY_10BTSC_NLPDIS

#define EPHY_10BTSC_NLPDIS   0x00000080

§ EPHY_10BTSC_POLSTAT

#define EPHY_10BTSC_POLSTAT   0x00000010

§ EPHY_10BTSC_JABBERD

#define EPHY_10BTSC_JABBERD   0x00000001

§ EPHY_10BTSC_SQUELCH_S

#define EPHY_10BTSC_SQUELCH_S   9

§ EPHY_BICSR1_ERRCNT_M

#define EPHY_BICSR1_ERRCNT_M   0x0000FF00

§ EPHY_BICSR1_IPGLENGTH_M

#define EPHY_BICSR1_IPGLENGTH_M   0x000000FF

§ EPHY_BICSR1_ERRCNT_S

#define EPHY_BICSR1_ERRCNT_S   8

§ EPHY_BICSR1_IPGLENGTH_S

#define EPHY_BICSR1_IPGLENGTH_S   0

§ EPHY_BICSR2_PKTLENGTH_M

#define EPHY_BICSR2_PKTLENGTH_M   0x000007FF

§ EPHY_BICSR2_PKTLENGTH_S

#define EPHY_BICSR2_PKTLENGTH_S   0

§ EPHY_CDCR_START

#define EPHY_CDCR_START   0x00008000

§ EPHY_CDCR_LINKQUAL_M

#define EPHY_CDCR_LINKQUAL_M   0x00000300

§ EPHY_CDCR_LINKQUAL_GOOD

#define EPHY_CDCR_LINKQUAL_GOOD   0x00000100

§ EPHY_CDCR_LINKQUAL_MILD

#define EPHY_CDCR_LINKQUAL_MILD   0x00000200

§ EPHY_CDCR_LINKQUAL_POOR

#define EPHY_CDCR_LINKQUAL_POOR   0x00000300

§ EPHY_CDCR_DONE

#define EPHY_CDCR_DONE   0x00000002

§ EPHY_CDCR_FAIL

#define EPHY_CDCR_FAIL   0x00000001

§ EPHY_RCR_SWRST

#define EPHY_RCR_SWRST   0x00008000

§ EPHY_RCR_SWRESTART

#define EPHY_RCR_SWRESTART   0x00004000

§ EPHY_LEDCFG_LED2_M

#define EPHY_LEDCFG_LED2_M   0x00000F00

§ EPHY_LEDCFG_LED2_LINK

#define EPHY_LEDCFG_LED2_LINK   0x00000000

§ EPHY_LEDCFG_LED2_RXTX

#define EPHY_LEDCFG_LED2_RXTX   0x00000100

§ EPHY_LEDCFG_LED2_TX

#define EPHY_LEDCFG_LED2_TX   0x00000200

§ EPHY_LEDCFG_LED2_RX

#define EPHY_LEDCFG_LED2_RX   0x00000300

§ EPHY_LEDCFG_LED2_COL

#define EPHY_LEDCFG_LED2_COL   0x00000400

§ EPHY_LEDCFG_LED2_100BT

#define EPHY_LEDCFG_LED2_100BT   0x00000500

§ EPHY_LEDCFG_LED2_10BT

#define EPHY_LEDCFG_LED2_10BT   0x00000600

§ EPHY_LEDCFG_LED2_FD

#define EPHY_LEDCFG_LED2_FD   0x00000700

§ EPHY_LEDCFG_LED2_LINKTXRX

#define EPHY_LEDCFG_LED2_LINKTXRX   0x00000800

§ EPHY_LEDCFG_LED1_M

#define EPHY_LEDCFG_LED1_M   0x000000F0

§ EPHY_LEDCFG_LED1_LINK

#define EPHY_LEDCFG_LED1_LINK   0x00000000

§ EPHY_LEDCFG_LED1_RXTX

#define EPHY_LEDCFG_LED1_RXTX   0x00000010

§ EPHY_LEDCFG_LED1_TX

#define EPHY_LEDCFG_LED1_TX   0x00000020

§ EPHY_LEDCFG_LED1_RX

#define EPHY_LEDCFG_LED1_RX   0x00000030

§ EPHY_LEDCFG_LED1_COL

#define EPHY_LEDCFG_LED1_COL   0x00000040

§ EPHY_LEDCFG_LED1_100BT

#define EPHY_LEDCFG_LED1_100BT   0x00000050

§ EPHY_LEDCFG_LED1_10BT

#define EPHY_LEDCFG_LED1_10BT   0x00000060

§ EPHY_LEDCFG_LED1_FD

#define EPHY_LEDCFG_LED1_FD   0x00000070

§ EPHY_LEDCFG_LED1_LINKTXRX

#define EPHY_LEDCFG_LED1_LINKTXRX   0x00000080

§ EPHY_LEDCFG_LED0_M

#define EPHY_LEDCFG_LED0_M   0x0000000F

§ EPHY_LEDCFG_LED0_LINK

#define EPHY_LEDCFG_LED0_LINK   0x00000000

§ EPHY_LEDCFG_LED0_RXTX

#define EPHY_LEDCFG_LED0_RXTX   0x00000001

§ EPHY_LEDCFG_LED0_TX

#define EPHY_LEDCFG_LED0_TX   0x00000002

§ EPHY_LEDCFG_LED0_RX

#define EPHY_LEDCFG_LED0_RX   0x00000003

§ EPHY_LEDCFG_LED0_COL

#define EPHY_LEDCFG_LED0_COL   0x00000004

§ EPHY_LEDCFG_LED0_100BT

#define EPHY_LEDCFG_LED0_100BT   0x00000005

§ EPHY_LEDCFG_LED0_10BT

#define EPHY_LEDCFG_LED0_10BT   0x00000006

§ EPHY_LEDCFG_LED0_FD

#define EPHY_LEDCFG_LED0_FD   0x00000007

§ EPHY_LEDCFG_LED0_LINKTXRX

#define EPHY_LEDCFG_LED0_LINKTXRX   0x00000008

§ EMAC_PPSCTRL_PPSCTRL_1HZ

#define EMAC_PPSCTRL_PPSCTRL_1HZ   0x00000000

§ EMAC_PPSCTRL_PPSCTRL_2HZ

#define EMAC_PPSCTRL_PPSCTRL_2HZ   0x00000001

§ EMAC_PPSCTRL_PPSCTRL_4HZ

#define EMAC_PPSCTRL_PPSCTRL_4HZ   0x00000002

§ EMAC_PPSCTRL_PPSCTRL_8HZ

#define EMAC_PPSCTRL_PPSCTRL_8HZ   0x00000003

§ EMAC_PPSCTRL_PPSCTRL_16HZ

#define EMAC_PPSCTRL_PPSCTRL_16HZ   0x00000004

§ EMAC_PPSCTRL_PPSCTRL_32HZ

#define EMAC_PPSCTRL_PPSCTRL_32HZ   0x00000005

§ EMAC_PPSCTRL_PPSCTRL_64HZ

#define EMAC_PPSCTRL_PPSCTRL_64HZ   0x00000006

§ EMAC_PPSCTRL_PPSCTRL_128HZ

#define EMAC_PPSCTRL_PPSCTRL_128HZ   0x00000007

§ EMAC_PPSCTRL_PPSCTRL_256HZ

#define EMAC_PPSCTRL_PPSCTRL_256HZ   0x00000008

§ EMAC_PPSCTRL_PPSCTRL_512HZ

#define EMAC_PPSCTRL_PPSCTRL_512HZ   0x00000009

§ EMAC_PPSCTRL_PPSCTRL_1024HZ

#define EMAC_PPSCTRL_PPSCTRL_1024HZ   0x0000000A

§ EMAC_PPSCTRL_PPSCTRL_2048HZ

#define EMAC_PPSCTRL_PPSCTRL_2048HZ   0x0000000B

§ EMAC_PPSCTRL_PPSCTRL_4096HZ

#define EMAC_PPSCTRL_PPSCTRL_4096HZ   0x0000000C

§ EMAC_PPSCTRL_PPSCTRL_8192HZ

#define EMAC_PPSCTRL_PPSCTRL_8192HZ   0x0000000D

§ EMAC_PPSCTRL_PPSCTRL_16384HZ

#define EMAC_PPSCTRL_PPSCTRL_16384HZ   0x0000000E

§ EMAC_PPSCTRL_PPSCTRL_32768HZ

#define EMAC_PPSCTRL_PPSCTRL_32768HZ   0x0000000F

§ EMAC_CC_CS_PA7

#define EMAC_CC_CS_PA7   0x00000001
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