hw_emac.h
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1 //*****************************************************************************
2 //
3 // hw_emac.h - Macros used when accessing the EMAC hardware.
4 //
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37 
38 #ifndef __HW_EMAC_H__
39 #define __HW_EMAC_H__
40 
41 //*****************************************************************************
42 //
43 // The following are defines for the EMAC register offsets.
44 //
45 //*****************************************************************************
46 #define EMAC_O_CFG 0x00000000 // Ethernet MAC Configuration
47 #define EMAC_O_FRAMEFLTR 0x00000004 // Ethernet MAC Frame Filter
48 #define EMAC_O_HASHTBLH 0x00000008 // Ethernet MAC Hash Table High
49 #define EMAC_O_HASHTBLL 0x0000000C // Ethernet MAC Hash Table Low
50 #define EMAC_O_MIIADDR 0x00000010 // Ethernet MAC MII Address
51 #define EMAC_O_MIIDATA 0x00000014 // Ethernet MAC MII Data Register
52 #define EMAC_O_FLOWCTL 0x00000018 // Ethernet MAC Flow Control
53 #define EMAC_O_VLANTG 0x0000001C // Ethernet MAC VLAN Tag
54 #define EMAC_O_STATUS 0x00000024 // Ethernet MAC Status
55 #define EMAC_O_RWUFF 0x00000028 // Ethernet MAC Remote Wake-Up
56  // Frame Filter
57 #define EMAC_O_PMTCTLSTAT 0x0000002C // Ethernet MAC PMT Control and
58  // Status Register
59 #define EMAC_O_LPICTLSTAT 0x00000030 // Ethernet MAC Low Power Idle
60  // Control and Status Register
61 #define EMAC_O_LPITIMERCTL 0x00000034 // Ethernet MAC Low Power Idle
62  // Timer Control Register
63 #define EMAC_O_RIS 0x00000038 // Ethernet MAC Raw Interrupt
64  // Status
65 #define EMAC_O_IM 0x0000003C // Ethernet MAC Interrupt Mask
66 #define EMAC_O_ADDR0H 0x00000040 // Ethernet MAC Address 0 High
67 #define EMAC_O_ADDR0L 0x00000044 // Ethernet MAC Address 0 Low
68  // Register
69 #define EMAC_O_ADDR1H 0x00000048 // Ethernet MAC Address 1 High
70 #define EMAC_O_ADDR1L 0x0000004C // Ethernet MAC Address 1 Low
71 #define EMAC_O_ADDR2H 0x00000050 // Ethernet MAC Address 2 High
72 #define EMAC_O_ADDR2L 0x00000054 // Ethernet MAC Address 2 Low
73 #define EMAC_O_ADDR3H 0x00000058 // Ethernet MAC Address 3 High
74 #define EMAC_O_ADDR3L 0x0000005C // Ethernet MAC Address 3 Low
75 #define EMAC_O_WDOGTO 0x000000DC // Ethernet MAC Watchdog Timeout
76 #define EMAC_O_MMCCTRL 0x00000100 // Ethernet MAC MMC Control
77 #define EMAC_O_MMCRXRIS 0x00000104 // Ethernet MAC MMC Receive Raw
78  // Interrupt Status
79 #define EMAC_O_MMCTXRIS 0x00000108 // Ethernet MAC MMC Transmit Raw
80  // Interrupt Status
81 #define EMAC_O_MMCRXIM 0x0000010C // Ethernet MAC MMC Receive
82  // Interrupt Mask
83 #define EMAC_O_MMCTXIM 0x00000110 // Ethernet MAC MMC Transmit
84  // Interrupt Mask
85 #define EMAC_O_TXCNTGB 0x00000118 // Ethernet MAC Transmit Frame
86  // Count for Good and Bad Frames
87 #define EMAC_O_TXCNTSCOL 0x0000014C // Ethernet MAC Transmit Frame
88  // Count for Frames Transmitted
89  // after Single Collision
90 #define EMAC_O_TXCNTMCOL 0x00000150 // Ethernet MAC Transmit Frame
91  // Count for Frames Transmitted
92  // after Multiple Collisions
93 #define EMAC_O_TXOCTCNTG 0x00000164 // Ethernet MAC Transmit Octet
94  // Count Good
95 #define EMAC_O_RXCNTGB 0x00000180 // Ethernet MAC Receive Frame Count
96  // for Good and Bad Frames
97 #define EMAC_O_RXCNTCRCERR 0x00000194 // Ethernet MAC Receive Frame Count
98  // for CRC Error Frames
99 #define EMAC_O_RXCNTALGNERR 0x00000198 // Ethernet MAC Receive Frame Count
100  // for Alignment Error Frames
101 #define EMAC_O_RXCNTGUNI 0x000001C4 // Ethernet MAC Receive Frame Count
102  // for Good Unicast Frames
103 #define EMAC_O_VLNINCREP 0x00000584 // Ethernet MAC VLAN Tag Inclusion
104  // or Replacement
105 #define EMAC_O_VLANHASH 0x00000588 // Ethernet MAC VLAN Hash Table
106 #define EMAC_O_TIMSTCTRL 0x00000700 // Ethernet MAC Timestamp Control
107 #define EMAC_O_SUBSECINC 0x00000704 // Ethernet MAC Sub-Second
108  // Increment
109 #define EMAC_O_TIMSEC 0x00000708 // Ethernet MAC System Time -
110  // Seconds
111 #define EMAC_O_TIMNANO 0x0000070C // Ethernet MAC System Time -
112  // Nanoseconds
113 #define EMAC_O_TIMSECU 0x00000710 // Ethernet MAC System Time -
114  // Seconds Update
115 #define EMAC_O_TIMNANOU 0x00000714 // Ethernet MAC System Time -
116  // Nanoseconds Update
117 #define EMAC_O_TIMADD 0x00000718 // Ethernet MAC Timestamp Addend
118 #define EMAC_O_TARGSEC 0x0000071C // Ethernet MAC Target Time Seconds
119 #define EMAC_O_TARGNANO 0x00000720 // Ethernet MAC Target Time
120  // Nanoseconds
121 #define EMAC_O_HWORDSEC 0x00000724 // Ethernet MAC System Time-Higher
122  // Word Seconds
123 #define EMAC_O_TIMSTAT 0x00000728 // Ethernet MAC Timestamp Status
124 #define EMAC_O_PPSCTRL 0x0000072C // Ethernet MAC PPS Control
125 #define EMAC_O_PPS0INTVL 0x00000760 // Ethernet MAC PPS0 Interval
126 #define EMAC_O_PPS0WIDTH 0x00000764 // Ethernet MAC PPS0 Width
127 #define EMAC_O_DMABUSMOD 0x00000C00 // Ethernet MAC DMA Bus Mode
128 #define EMAC_O_TXPOLLD 0x00000C04 // Ethernet MAC Transmit Poll
129  // Demand
130 #define EMAC_O_RXPOLLD 0x00000C08 // Ethernet MAC Receive Poll Demand
131 #define EMAC_O_RXDLADDR 0x00000C0C // Ethernet MAC Receive Descriptor
132  // List Address
133 #define EMAC_O_TXDLADDR 0x00000C10 // Ethernet MAC Transmit Descriptor
134  // List Address
135 #define EMAC_O_DMARIS 0x00000C14 // Ethernet MAC DMA Interrupt
136  // Status
137 #define EMAC_O_DMAOPMODE 0x00000C18 // Ethernet MAC DMA Operation Mode
138 #define EMAC_O_DMAIM 0x00000C1C // Ethernet MAC DMA Interrupt Mask
139  // Register
140 #define EMAC_O_MFBOC 0x00000C20 // Ethernet MAC Missed Frame and
141  // Buffer Overflow Counter
142 #define EMAC_O_RXINTWDT 0x00000C24 // Ethernet MAC Receive Interrupt
143  // Watchdog Timer
144 #define EMAC_O_HOSTXDESC 0x00000C48 // Ethernet MAC Current Host
145  // Transmit Descriptor
146 #define EMAC_O_HOSRXDESC 0x00000C4C // Ethernet MAC Current Host
147  // Receive Descriptor
148 #define EMAC_O_HOSTXBA 0x00000C50 // Ethernet MAC Current Host
149  // Transmit Buffer Address
150 #define EMAC_O_HOSRXBA 0x00000C54 // Ethernet MAC Current Host
151  // Receive Buffer Address
152 #define EMAC_O_PP 0x00000FC0 // Ethernet MAC Peripheral Property
153  // Register
154 #define EMAC_O_PC 0x00000FC4 // Ethernet MAC Peripheral
155  // Configuration Register
156 #define EMAC_O_CC 0x00000FC8 // Ethernet MAC Clock Configuration
157  // Register
158 #define EMAC_O_EPHYRIS 0x00000FD0 // Ethernet PHY Raw Interrupt
159  // Status
160 #define EMAC_O_EPHYIM 0x00000FD4 // Ethernet PHY Interrupt Mask
161 #define EMAC_O_EPHYMISC 0x00000FD8 // Ethernet PHY Masked Interrupt
162  // Status and Clear
163 
164 //*****************************************************************************
165 //
166 // The following are defines for the bit fields in the EMAC_O_CFG register.
167 //
168 //*****************************************************************************
169 #define EMAC_CFG_TWOKPEN 0x08000000 // IEEE 802
170 #define EMAC_CFG_CST 0x02000000 // CRC Stripping for Type Frames
171 #define EMAC_CFG_WDDIS 0x00800000 // Watchdog Disable
172 #define EMAC_CFG_JD 0x00400000 // Jabber Disable
173 #define EMAC_CFG_JFEN 0x00100000 // Jumbo Frame Enable
174 #define EMAC_CFG_IFG_M 0x000E0000 // Inter-Frame Gap (IFG)
175 #define EMAC_CFG_IFG_96 0x00000000 // 96 bit times
176 #define EMAC_CFG_IFG_88 0x00020000 // 88 bit times
177 #define EMAC_CFG_IFG_80 0x00040000 // 80 bit times
178 #define EMAC_CFG_IFG_72 0x00060000 // 72 bit times
179 #define EMAC_CFG_IFG_64 0x00080000 // 64 bit times
180 #define EMAC_CFG_IFG_56 0x000A0000 // 56 bit times
181 #define EMAC_CFG_IFG_48 0x000C0000 // 48 bit times
182 #define EMAC_CFG_IFG_40 0x000E0000 // 40 bit times
183 #define EMAC_CFG_DISCRS 0x00010000 // Disable Carrier Sense During
184  // Transmission
185 #define EMAC_CFG_PS 0x00008000 // Port Select
186 #define EMAC_CFG_FES 0x00004000 // Speed
187 #define EMAC_CFG_DRO 0x00002000 // Disable Receive Own
188 #define EMAC_CFG_LOOPBM 0x00001000 // Loopback Mode
189 #define EMAC_CFG_DUPM 0x00000800 // Duplex Mode
190 #define EMAC_CFG_IPC 0x00000400 // Checksum Offload
191 #define EMAC_CFG_DR 0x00000200 // Disable Retry
192 #define EMAC_CFG_ACS 0x00000080 // Automatic Pad or CRC Stripping
193 #define EMAC_CFG_BL_M 0x00000060 // Back-Off Limit
194 #define EMAC_CFG_BL_1024 0x00000000 // k = min (n,10)
195 #define EMAC_CFG_BL_256 0x00000020 // k = min (n,8)
196 #define EMAC_CFG_BL_8 0x00000040 // k = min (n,4)
197 #define EMAC_CFG_BL_2 0x00000060 // k = min (n,1)
198 #define EMAC_CFG_DC 0x00000010 // Deferral Check
199 #define EMAC_CFG_TE 0x00000008 // Transmitter Enable
200 #define EMAC_CFG_RE 0x00000004 // Receiver Enable
201 #define EMAC_CFG_PRELEN_M 0x00000003 // Preamble Length for Transmit
202  // Frames
203 #define EMAC_CFG_PRELEN_7 0x00000000 // 7 bytes of preamble
204 #define EMAC_CFG_PRELEN_5 0x00000001 // 5 bytes of preamble
205 #define EMAC_CFG_PRELEN_3 0x00000002 // 3 bytes of preamble
206 
207 //*****************************************************************************
208 //
209 // The following are defines for the bit fields in the EMAC_O_FRAMEFLTR
210 // register.
211 //
212 //*****************************************************************************
213 #define EMAC_FRAMEFLTR_RA 0x80000000 // Receive All
214 #define EMAC_FRAMEFLTR_VTFE 0x00010000 // VLAN Tag Filter Enable
215 #define EMAC_FRAMEFLTR_HPF 0x00000400 // Hash or Perfect Filter
216 #define EMAC_FRAMEFLTR_SAF 0x00000200 // Source Address Filter Enable
217 #define EMAC_FRAMEFLTR_SAIF 0x00000100 // Source Address (SA) Inverse
218  // Filtering
219 #define EMAC_FRAMEFLTR_PCF_M 0x000000C0 // Pass Control Frames
220 #define EMAC_FRAMEFLTR_PCF_ALL 0x00000000 // The MAC filters all control
221  // frames from reaching application
222 #define EMAC_FRAMEFLTR_PCF_PAUSE \
223  0x00000040 // MAC forwards all control frames
224  // except PAUSE control frames to
225  // application even if they fail
226  // the address filter
227 #define EMAC_FRAMEFLTR_PCF_NONE 0x00000080 // MAC forwards all control frames
228  // to application even if they fail
229  // the address Filter
230 #define EMAC_FRAMEFLTR_PCF_ADDR 0x000000C0 // MAC forwards control frames that
231  // pass the address Filter
232 #define EMAC_FRAMEFLTR_DBF 0x00000020 // Disable Broadcast Frames
233 #define EMAC_FRAMEFLTR_PM 0x00000010 // Pass All Multicast
234 #define EMAC_FRAMEFLTR_DAIF 0x00000008 // Destination Address (DA) Inverse
235  // Filtering
236 #define EMAC_FRAMEFLTR_HMC 0x00000004 // Hash Multicast
237 #define EMAC_FRAMEFLTR_HUC 0x00000002 // Hash Unicast
238 #define EMAC_FRAMEFLTR_PR 0x00000001 // Promiscuous Mode
239 
240 //*****************************************************************************
241 //
242 // The following are defines for the bit fields in the EMAC_O_HASHTBLH
243 // register.
244 //
245 //*****************************************************************************
246 #define EMAC_HASHTBLH_HTH_M 0xFFFFFFFF // Hash Table High
247 #define EMAC_HASHTBLH_HTH_S 0
248 
249 //*****************************************************************************
250 //
251 // The following are defines for the bit fields in the EMAC_O_HASHTBLL
252 // register.
253 //
254 //*****************************************************************************
255 #define EMAC_HASHTBLL_HTL_M 0xFFFFFFFF // Hash Table Low
256 #define EMAC_HASHTBLL_HTL_S 0
257 
258 //*****************************************************************************
259 //
260 // The following are defines for the bit fields in the EMAC_O_MIIADDR register.
261 //
262 //*****************************************************************************
263 #define EMAC_MIIADDR_PLA_M 0x0000F800 // Physical Layer Address
264 #define EMAC_MIIADDR_MII_M 0x000007C0 // MII Register
265 #define EMAC_MIIADDR_CR_M 0x0000003C // Clock Reference Frequency
266  // Selection
267 #define EMAC_MIIADDR_CR_60_100 0x00000000 // The frequency of the System
268  // Clock is 60 to 100 MHz providing
269  // a MDIO clock of SYSCLK/42
270 #define EMAC_MIIADDR_CR_100_150 0x00000004 // The frequency of the System
271  // Clock is 100 to 150 MHz
272  // providing a MDIO clock of
273  // SYSCLK/62
274 #define EMAC_MIIADDR_CR_20_35 0x00000008 // The frequency of the System
275  // Clock is 20-35 MHz providing a
276  // MDIO clock of System Clock/16
277 #define EMAC_MIIADDR_CR_35_60 0x0000000C // The frequency of the System
278  // Clock is 35 to 60 MHz providing
279  // a MDIO clock of System Clock/26
280 #define EMAC_MIIADDR_MIIW 0x00000002 // MII Write
281 #define EMAC_MIIADDR_MIIB 0x00000001 // MII Busy
282 #define EMAC_MIIADDR_PLA_S 11
283 #define EMAC_MIIADDR_MII_S 6
284 
285 //*****************************************************************************
286 //
287 // The following are defines for the bit fields in the EMAC_O_MIIDATA register.
288 //
289 //*****************************************************************************
290 #define EMAC_MIIDATA_DATA_M 0x0000FFFF // MII Data
291 #define EMAC_MIIDATA_DATA_S 0
292 
293 //*****************************************************************************
294 //
295 // The following are defines for the bit fields in the EMAC_O_FLOWCTL register.
296 //
297 //*****************************************************************************
298 #define EMAC_FLOWCTL_PT_M 0xFFFF0000 // Pause Time
299 #define EMAC_FLOWCTL_DZQP 0x00000080 // Disable Zero-Quanta Pause
300 #define EMAC_FLOWCTL_UP 0x00000008 // Unicast Pause Frame Detect
301 #define EMAC_FLOWCTL_RFE 0x00000004 // Receive Flow Control Enable
302 #define EMAC_FLOWCTL_TFE 0x00000002 // Transmit Flow Control Enable
303 #define EMAC_FLOWCTL_FCBBPA 0x00000001 // Flow Control Busy or
304  // Back-pressure Activate
305 #define EMAC_FLOWCTL_PT_S 16
306 
307 //*****************************************************************************
308 //
309 // The following are defines for the bit fields in the EMAC_O_VLANTG register.
310 //
311 //*****************************************************************************
312 #define EMAC_VLANTG_VTHM 0x00080000 // VLAN Tag Hash Table Match Enable
313 #define EMAC_VLANTG_ESVL 0x00040000 // Enable S-VLAN
314 #define EMAC_VLANTG_VTIM 0x00020000 // VLAN Tag Inverse Match Enable
315 #define EMAC_VLANTG_ETV 0x00010000 // Enable 12-Bit VLAN Tag
316  // Comparison
317 #define EMAC_VLANTG_VL_M 0x0000FFFF // VLAN Tag Identifier for Receive
318  // Frames
319 #define EMAC_VLANTG_VL_S 0
320 
321 //*****************************************************************************
322 //
323 // The following are defines for the bit fields in the EMAC_O_STATUS register.
324 //
325 //*****************************************************************************
326 #define EMAC_STATUS_TXFF 0x02000000 // TX/RX Controller TX FIFO Full
327  // Status
328 #define EMAC_STATUS_TXFE 0x01000000 // TX/RX Controller TX FIFO Not
329  // Empty Status
330 #define EMAC_STATUS_TWC 0x00400000 // TX/RX Controller TX FIFO Write
331  // Controller Active Status
332 #define EMAC_STATUS_TRC_M 0x00300000 // TX/RX Controller's TX FIFO Read
333  // Controller Status
334 #define EMAC_STATUS_TRC_IDLE 0x00000000 // IDLE state
335 #define EMAC_STATUS_TRC_READ 0x00100000 // READ state (transferring data to
336  // MAC transmitter)
337 #define EMAC_STATUS_TRC_WAIT 0x00200000 // Waiting for TX Status from MAC
338  // transmitter
339 #define EMAC_STATUS_TRC_WRFLUSH 0x00300000 // Writing the received TX Status
340  // or flushing the TX FIFO
341 #define EMAC_STATUS_TXPAUSED 0x00080000 // MAC Transmitter PAUSE
342 #define EMAC_STATUS_TFC_M 0x00060000 // MAC Transmit Frame Controller
343  // Status
344 #define EMAC_STATUS_TFC_IDLE 0x00000000 // IDLE state
345 #define EMAC_STATUS_TFC_STATUS 0x00020000 // Waiting for status of previous
346  // frame or IFG or backoff period
347  // to be over
348 #define EMAC_STATUS_TFC_PAUSE 0x00040000 // Generating and transmitting a
349  // PAUSE control frame (in the
350  // full-duplex mode)
351 #define EMAC_STATUS_TFC_INPUT 0x00060000 // Transferring input frame for
352  // transmission
353 #define EMAC_STATUS_TPE 0x00010000 // MAC MII Transmit Protocol Engine
354  // Status
355 #define EMAC_STATUS_RXF_M 0x00000300 // TX/RX Controller RX FIFO
356  // Fill-level Status
357 #define EMAC_STATUS_RXF_EMPTY 0x00000000 // RX FIFO Empty
358 #define EMAC_STATUS_RXF_BELOW 0x00000100 // RX FIFO fill level is below the
359  // flow-control deactivate
360  // threshold
361 #define EMAC_STATUS_RXF_ABOVE 0x00000200 // RX FIFO fill level is above the
362  // flow-control activate threshold
363 #define EMAC_STATUS_RXF_FULL 0x00000300 // RX FIFO Full
364 #define EMAC_STATUS_RRC_M 0x00000060 // TX/RX Controller Read Controller
365  // State
366 #define EMAC_STATUS_RRC_IDLE 0x00000000 // IDLE state
367 #define EMAC_STATUS_RRC_STATUS 0x00000020 // Reading frame data
368 #define EMAC_STATUS_RRC_DATA 0x00000040 // Reading frame status (or
369  // timestamp)
370 #define EMAC_STATUS_RRC_FLUSH 0x00000060 // Flushing the frame data and
371  // status
372 #define EMAC_STATUS_RWC 0x00000010 // TX/RX Controller RX FIFO Write
373  // Controller Active Status
374 #define EMAC_STATUS_RFCFC_M 0x00000006 // MAC Receive Frame Controller
375  // FIFO Status
376 #define EMAC_STATUS_RPE 0x00000001 // MAC MII Receive Protocol Engine
377  // Status
378 #define EMAC_STATUS_RFCFC_S 1
379 
380 //*****************************************************************************
381 //
382 // The following are defines for the bit fields in the EMAC_O_RWUFF register.
383 //
384 //*****************************************************************************
385 #define EMAC_RWUFF_WAKEUPFIL_M 0xFFFFFFFF // Remote Wake-Up Frame Filter
386 #define EMAC_RWUFF_WAKEUPFIL_S 0
387 
388 //*****************************************************************************
389 //
390 // The following are defines for the bit fields in the EMAC_O_PMTCTLSTAT
391 // register.
392 //
393 //*****************************************************************************
394 #define EMAC_PMTCTLSTAT_WUPFRRST \
395  0x80000000 // Wake-Up Frame Filter Register
396  // Pointer Reset
397 #define EMAC_PMTCTLSTAT_RWKPTR_M \
398  0x07000000 // Remote Wake-Up FIFO Pointer
399 #define EMAC_PMTCTLSTAT_GLBLUCAST \
400  0x00000200 // Global Unicast
401 #define EMAC_PMTCTLSTAT_WUPRX 0x00000040 // Wake-Up Frame Received
402 #define EMAC_PMTCTLSTAT_MGKPRX 0x00000020 // Magic Packet Received
403 #define EMAC_PMTCTLSTAT_WUPFREN 0x00000004 // Wake-Up Frame Enable
404 #define EMAC_PMTCTLSTAT_MGKPKTEN \
405  0x00000002 // Magic Packet Enable
406 #define EMAC_PMTCTLSTAT_PWRDWN 0x00000001 // Power Down
407 #define EMAC_PMTCTLSTAT_RWKPTR_S \
408  24
409 
410 //*****************************************************************************
411 //
412 // The following are defines for the bit fields in the EMAC_O_LPICTLSTAT
413 // register.
414 //
415 //*****************************************************************************
416 #define EMAC_LPICTLSTAT_LPITXA 0x00080000 // LPI TX Automate
417 #define EMAC_LPICTLSTAT_PLSEN 0x00040000 // PHY Link Status Enable
418 #define EMAC_LPICTLSTAT_PLS 0x00020000 // PHY Link Status
419 #define EMAC_LPICTLSTAT_LPIEN 0x00010000 // LPI Enable
420 #define EMAC_LPICTLSTAT_RLPIST 0x00000200 // Receive LPI State
421 #define EMAC_LPICTLSTAT_TLPIST 0x00000100 // Transmit LPI State
422 #define EMAC_LPICTLSTAT_RLPIEX 0x00000008 // Receive LPI Exit
423 #define EMAC_LPICTLSTAT_RLPIEN 0x00000004 // Receive LPI Entry
424 #define EMAC_LPICTLSTAT_TLPIEX 0x00000002 // Transmit LPI Exit
425 #define EMAC_LPICTLSTAT_TLPIEN 0x00000001 // Transmit LPI Entry
426 
427 //*****************************************************************************
428 //
429 // The following are defines for the bit fields in the EMAC_O_LPITIMERCTL
430 // register.
431 //
432 //*****************************************************************************
433 #define EMAC_LPITIMERCTL_LST_M 0x03FF0000 // Low Power Idle LS Timer
434 #define EMAC_LPITIMERCTL_LST_S 16
435 #define EMAC_LPITIMERCTL_TWT_M 0x0000FFFF // Low Power Idle TW Timer
436 #define EMAC_LPITIMERCTL_TWT_S 0
437 
438 //*****************************************************************************
439 //
440 // The following are defines for the bit fields in the EMAC_O_RIS register.
441 //
442 //*****************************************************************************
443 #define EMAC_RIS_LPI 0x00000400 // LPI Interrupt Status
444 #define EMAC_RIS_TS 0x00000200 // Timestamp Interrupt Status
445 #define EMAC_RIS_MMCTX 0x00000040 // MMC Transmit Interrupt Status
446 #define EMAC_RIS_MMCRX 0x00000020 // MMC Receive Interrupt Status
447 #define EMAC_RIS_MMC 0x00000010 // MMC Interrupt Status
448 #define EMAC_RIS_PMT 0x00000008 // PMT Interrupt Status
449 
450 //*****************************************************************************
451 //
452 // The following are defines for the bit fields in the EMAC_O_IM register.
453 //
454 //*****************************************************************************
455 #define EMAC_IM_LPI 0x00000400 // LPI Interrupt Mask
456 #define EMAC_IM_TSI 0x00000200 // Timestamp Interrupt Mask
457 #define EMAC_IM_PMT 0x00000008 // PMT Interrupt Mask
458 
459 //*****************************************************************************
460 //
461 // The following are defines for the bit fields in the EMAC_O_ADDR0H register.
462 //
463 //*****************************************************************************
464 #define EMAC_ADDR0H_AE 0x80000000 // Address Enable
465 #define EMAC_ADDR0H_ADDRHI_M 0x0000FFFF // MAC Address0 [47:32]
466 #define EMAC_ADDR0H_ADDRHI_S 0
467 
468 //*****************************************************************************
469 //
470 // The following are defines for the bit fields in the EMAC_O_ADDR0L register.
471 //
472 //*****************************************************************************
473 #define EMAC_ADDR0L_ADDRLO_M 0xFFFFFFFF // MAC Address0 [31:0]
474 #define EMAC_ADDR0L_ADDRLO_S 0
475 
476 //*****************************************************************************
477 //
478 // The following are defines for the bit fields in the EMAC_O_ADDR1H register.
479 //
480 //*****************************************************************************
481 #define EMAC_ADDR1H_AE 0x80000000 // Address Enable
482 #define EMAC_ADDR1H_SA 0x40000000 // Source Address
483 #define EMAC_ADDR1H_MBC_M 0x3F000000 // Mask Byte Control
484 #define EMAC_ADDR1H_ADDRHI_M 0x0000FFFF // MAC Address1 [47:32]
485 #define EMAC_ADDR1H_MBC_S 24
486 #define EMAC_ADDR1H_ADDRHI_S 0
487 
488 //*****************************************************************************
489 //
490 // The following are defines for the bit fields in the EMAC_O_ADDR1L register.
491 //
492 //*****************************************************************************
493 #define EMAC_ADDR1L_ADDRLO_M 0xFFFFFFFF // MAC Address1 [31:0]
494 #define EMAC_ADDR1L_ADDRLO_S 0
495 
496 //*****************************************************************************
497 //
498 // The following are defines for the bit fields in the EMAC_O_ADDR2H register.
499 //
500 //*****************************************************************************
501 #define EMAC_ADDR2H_AE 0x80000000 // Address Enable
502 #define EMAC_ADDR2H_SA 0x40000000 // Source Address
503 #define EMAC_ADDR2H_MBC_M 0x3F000000 // Mask Byte Control
504 #define EMAC_ADDR2H_ADDRHI_M 0x0000FFFF // MAC Address2 [47:32]
505 #define EMAC_ADDR2H_MBC_S 24
506 #define EMAC_ADDR2H_ADDRHI_S 0
507 
508 //*****************************************************************************
509 //
510 // The following are defines for the bit fields in the EMAC_O_ADDR2L register.
511 //
512 //*****************************************************************************
513 #define EMAC_ADDR2L_ADDRLO_M 0xFFFFFFFF // MAC Address2 [31:0]
514 #define EMAC_ADDR2L_ADDRLO_S 0
515 
516 //*****************************************************************************
517 //
518 // The following are defines for the bit fields in the EMAC_O_ADDR3H register.
519 //
520 //*****************************************************************************
521 #define EMAC_ADDR3H_AE 0x80000000 // Address Enable
522 #define EMAC_ADDR3H_SA 0x40000000 // Source Address
523 #define EMAC_ADDR3H_MBC_M 0x3F000000 // Mask Byte Control
524 #define EMAC_ADDR3H_ADDRHI_M 0x0000FFFF // MAC Address3 [47:32]
525 #define EMAC_ADDR3H_MBC_S 24
526 #define EMAC_ADDR3H_ADDRHI_S 0
527 
528 //*****************************************************************************
529 //
530 // The following are defines for the bit fields in the EMAC_O_ADDR3L register.
531 //
532 //*****************************************************************************
533 #define EMAC_ADDR3L_ADDRLO_M 0xFFFFFFFF // MAC Address3 [31:0]
534 #define EMAC_ADDR3L_ADDRLO_S 0
535 
536 //*****************************************************************************
537 //
538 // The following are defines for the bit fields in the EMAC_O_WDOGTO register.
539 //
540 //*****************************************************************************
541 #define EMAC_WDOGTO_PWE 0x00010000 // Programmable Watchdog Enable
542 #define EMAC_WDOGTO_WTO_M 0x00003FFF // Watchdog Timeout
543 #define EMAC_WDOGTO_WTO_S 0
544 
545 //*****************************************************************************
546 //
547 // The following are defines for the bit fields in the EMAC_O_MMCCTRL register.
548 //
549 //*****************************************************************************
550 #define EMAC_MMCCTRL_UCDBC 0x00000100 // Update MMC Counters for Dropped
551  // Broadcast Frames
552 #define EMAC_MMCCTRL_CNTPRSTLVL 0x00000020 // Full/Half Preset Level Value
553 #define EMAC_MMCCTRL_CNTPRST 0x00000010 // Counters Preset
554 #define EMAC_MMCCTRL_CNTFREEZ 0x00000008 // MMC Counter Freeze
555 #define EMAC_MMCCTRL_RSTONRD 0x00000004 // Reset on Read
556 #define EMAC_MMCCTRL_CNTSTPRO 0x00000002 // Counters Stop Rollover
557 #define EMAC_MMCCTRL_CNTRST 0x00000001 // Counters Reset
558 
559 //*****************************************************************************
560 //
561 // The following are defines for the bit fields in the EMAC_O_MMCRXRIS
562 // register.
563 //
564 //*****************************************************************************
565 #define EMAC_MMCRXRIS_UCGF 0x00020000 // MMC Receive Unicast Good Frame
566  // Counter Interrupt Status
567 #define EMAC_MMCRXRIS_ALGNERR 0x00000040 // MMC Receive Alignment Error
568  // Frame Counter Interrupt Status
569 #define EMAC_MMCRXRIS_CRCERR 0x00000020 // MMC Receive CRC Error Frame
570  // Counter Interrupt Status
571 #define EMAC_MMCRXRIS_GBF 0x00000001 // MMC Receive Good Bad Frame
572  // Counter Interrupt Status
573 
574 //*****************************************************************************
575 //
576 // The following are defines for the bit fields in the EMAC_O_MMCTXRIS
577 // register.
578 //
579 //*****************************************************************************
580 #define EMAC_MMCTXRIS_OCTCNT 0x00100000 // Octet Counter Interrupt Status
581 #define EMAC_MMCTXRIS_MCOLLGF 0x00008000 // MMC Transmit Multiple Collision
582  // Good Frame Counter Interrupt
583  // Status
584 #define EMAC_MMCTXRIS_SCOLLGF 0x00004000 // MMC Transmit Single Collision
585  // Good Frame Counter Interrupt
586  // Status
587 #define EMAC_MMCTXRIS_GBF 0x00000002 // MMC Transmit Good Bad Frame
588  // Counter Interrupt Status
589 
590 //*****************************************************************************
591 //
592 // The following are defines for the bit fields in the EMAC_O_MMCRXIM register.
593 //
594 //*****************************************************************************
595 #define EMAC_MMCRXIM_UCGF 0x00020000 // MMC Receive Unicast Good Frame
596  // Counter Interrupt Mask
597 #define EMAC_MMCRXIM_ALGNERR 0x00000040 // MMC Receive Alignment Error
598  // Frame Counter Interrupt Mask
599 #define EMAC_MMCRXIM_CRCERR 0x00000020 // MMC Receive CRC Error Frame
600  // Counter Interrupt Mask
601 #define EMAC_MMCRXIM_GBF 0x00000001 // MMC Receive Good Bad Frame
602  // Counter Interrupt Mask
603 
604 //*****************************************************************************
605 //
606 // The following are defines for the bit fields in the EMAC_O_MMCTXIM register.
607 //
608 //*****************************************************************************
609 #define EMAC_MMCTXIM_OCTCNT 0x00100000 // MMC Transmit Good Octet Counter
610  // Interrupt Mask
611 #define EMAC_MMCTXIM_MCOLLGF 0x00008000 // MMC Transmit Multiple Collision
612  // Good Frame Counter Interrupt
613  // Mask
614 #define EMAC_MMCTXIM_SCOLLGF 0x00004000 // MMC Transmit Single Collision
615  // Good Frame Counter Interrupt
616  // Mask
617 #define EMAC_MMCTXIM_GBF 0x00000002 // MMC Transmit Good Bad Frame
618  // Counter Interrupt Mask
619 
620 //*****************************************************************************
621 //
622 // The following are defines for the bit fields in the EMAC_O_TXCNTGB register.
623 //
624 //*****************************************************************************
625 #define EMAC_TXCNTGB_TXFRMGB_M 0xFFFFFFFF // This field indicates the number
626  // of good and bad frames
627  // transmitted, exclusive of
628  // retried frames
629 #define EMAC_TXCNTGB_TXFRMGB_S 0
630 
631 //*****************************************************************************
632 //
633 // The following are defines for the bit fields in the EMAC_O_TXCNTSCOL
634 // register.
635 //
636 //*****************************************************************************
637 #define EMAC_TXCNTSCOL_TXSNGLCOLG_M \
638  0xFFFFFFFF // This field indicates the number
639  // of successfully transmitted
640  // frames after a single collision
641  // in the half-duplex mode
642 #define EMAC_TXCNTSCOL_TXSNGLCOLG_S \
643  0
644 
645 //*****************************************************************************
646 //
647 // The following are defines for the bit fields in the EMAC_O_TXCNTMCOL
648 // register.
649 //
650 //*****************************************************************************
651 #define EMAC_TXCNTMCOL_TXMULTCOLG_M \
652  0xFFFFFFFF // This field indicates the number
653  // of successfully transmitted
654  // frames after multiple collisions
655  // in the half-duplex mode
656 #define EMAC_TXCNTMCOL_TXMULTCOLG_S \
657  0
658 
659 //*****************************************************************************
660 //
661 // The following are defines for the bit fields in the EMAC_O_TXOCTCNTG
662 // register.
663 //
664 //*****************************************************************************
665 #define EMAC_TXOCTCNTG_TXOCTG_M 0xFFFFFFFF // This field indicates the number
666  // of bytes transmitted, exclusive
667  // of preamble, in good frames
668 #define EMAC_TXOCTCNTG_TXOCTG_S 0
669 
670 //*****************************************************************************
671 //
672 // The following are defines for the bit fields in the EMAC_O_RXCNTGB register.
673 //
674 //*****************************************************************************
675 #define EMAC_RXCNTGB_RXFRMGB_M 0xFFFFFFFF // This field indicates the number
676  // of received good and bad frames
677 #define EMAC_RXCNTGB_RXFRMGB_S 0
678 
679 //*****************************************************************************
680 //
681 // The following are defines for the bit fields in the EMAC_O_RXCNTCRCERR
682 // register.
683 //
684 //*****************************************************************************
685 #define EMAC_RXCNTCRCERR_RXCRCERR_M \
686  0xFFFFFFFF // This field indicates the number
687  // of frames received with CRC
688  // error
689 #define EMAC_RXCNTCRCERR_RXCRCERR_S \
690  0
691 
692 //*****************************************************************************
693 //
694 // The following are defines for the bit fields in the EMAC_O_RXCNTALGNERR
695 // register.
696 //
697 //*****************************************************************************
698 #define EMAC_RXCNTALGNERR_RXALGNERR_M \
699  0xFFFFFFFF // This field indicates the number
700  // of frames received with
701  // alignment (dribble) error
702 #define EMAC_RXCNTALGNERR_RXALGNERR_S \
703  0
704 
705 //*****************************************************************************
706 //
707 // The following are defines for the bit fields in the EMAC_O_RXCNTGUNI
708 // register.
709 //
710 //*****************************************************************************
711 #define EMAC_RXCNTGUNI_RXUCASTG_M \
712  0xFFFFFFFF // This field indicates the number
713  // of received good unicast frames
714 #define EMAC_RXCNTGUNI_RXUCASTG_S \
715  0
716 
717 //*****************************************************************************
718 //
719 // The following are defines for the bit fields in the EMAC_O_VLNINCREP
720 // register.
721 //
722 //*****************************************************************************
723 #define EMAC_VLNINCREP_CSVL 0x00080000 // C-VLAN or S-VLAN
724 #define EMAC_VLNINCREP_VLP 0x00040000 // VLAN Priority Control
725 #define EMAC_VLNINCREP_VLC_M 0x00030000 // VLAN Tag Control in Transmit
726  // Frames
727 #define EMAC_VLNINCREP_VLC_NONE 0x00000000 // No VLAN tag deletion, insertion,
728  // or replacement
729 #define EMAC_VLNINCREP_VLC_TAGDEL \
730  0x00010000 // VLAN tag deletion
731 #define EMAC_VLNINCREP_VLC_TAGINS \
732  0x00020000 // VLAN tag insertion
733 #define EMAC_VLNINCREP_VLC_TAGREP \
734  0x00030000 // VLAN tag replacement
735 #define EMAC_VLNINCREP_VLT_M 0x0000FFFF // VLAN Tag for Transmit Frames
736 #define EMAC_VLNINCREP_VLT_S 0
737 
738 //*****************************************************************************
739 //
740 // The following are defines for the bit fields in the EMAC_O_VLANHASH
741 // register.
742 //
743 //*****************************************************************************
744 #define EMAC_VLANHASH_VLHT_M 0x0000FFFF // VLAN Hash Table
745 #define EMAC_VLANHASH_VLHT_S 0
746 
747 //*****************************************************************************
748 //
749 // The following are defines for the bit fields in the EMAC_O_TIMSTCTRL
750 // register.
751 //
752 //*****************************************************************************
753 #define EMAC_TIMSTCTRL_PTPFLTR 0x00040000 // Enable MAC address for PTP Frame
754  // Filtering
755 #define EMAC_TIMSTCTRL_SELPTP_M 0x00030000 // Select PTP packets for Taking
756  // Snapshots
757 #define EMAC_TIMSTCTRL_TSMAST 0x00008000 // Enable Snapshot for Messages
758  // Relevant to Master
759 #define EMAC_TIMSTCTRL_TSEVNT 0x00004000 // Enable Timestamp Snapshot for
760  // Event Messages
761 #define EMAC_TIMSTCTRL_PTPIPV4 0x00002000 // Enable Processing of PTP Frames
762  // Sent over IPv4-UDP
763 #define EMAC_TIMSTCTRL_PTPIPV6 0x00001000 // Enable Processing of PTP Frames
764  // Sent Over IPv6-UDP
765 #define EMAC_TIMSTCTRL_PTPETH 0x00000800 // Enable Processing of PTP Over
766  // Ethernet Frames
767 #define EMAC_TIMSTCTRL_PTPVER2 0x00000400 // Enable PTP Packet Processing For
768  // Version 2 Format
769 #define EMAC_TIMSTCTRL_DGTLBIN 0x00000200 // Timestamp Digital or Binary
770  // Rollover Control
771 #define EMAC_TIMSTCTRL_ALLF 0x00000100 // Enable Timestamp For All Frames
772 #define EMAC_TIMSTCTRL_ADDREGUP 0x00000020 // Addend Register Update
773 #define EMAC_TIMSTCTRL_INTTRIG 0x00000010 // Timestamp Interrupt Trigger
774  // Enable
775 #define EMAC_TIMSTCTRL_TSUPDT 0x00000008 // Timestamp Update
776 #define EMAC_TIMSTCTRL_TSINIT 0x00000004 // Timestamp Initialize
777 #define EMAC_TIMSTCTRL_TSFCUPDT 0x00000002 // Timestamp Fine or Coarse Update
778 #define EMAC_TIMSTCTRL_TSEN 0x00000001 // Timestamp Enable
779 #define EMAC_TIMSTCTRL_SELPTP_S 16
780 
781 //*****************************************************************************
782 //
783 // The following are defines for the bit fields in the EMAC_O_SUBSECINC
784 // register.
785 //
786 //*****************************************************************************
787 #define EMAC_SUBSECINC_SSINC_M 0x000000FF // Sub-second Increment Value
788 #define EMAC_SUBSECINC_SSINC_S 0
789 
790 //*****************************************************************************
791 //
792 // The following are defines for the bit fields in the EMAC_O_TIMSEC register.
793 //
794 //*****************************************************************************
795 #define EMAC_TIMSEC_TSS_M 0xFFFFFFFF // Timestamp Second
796 #define EMAC_TIMSEC_TSS_S 0
797 
798 //*****************************************************************************
799 //
800 // The following are defines for the bit fields in the EMAC_O_TIMNANO register.
801 //
802 //*****************************************************************************
803 #define EMAC_TIMNANO_TSSS_M 0x7FFFFFFF // Timestamp Sub-Seconds
804 #define EMAC_TIMNANO_TSSS_S 0
805 
806 //*****************************************************************************
807 //
808 // The following are defines for the bit fields in the EMAC_O_TIMSECU register.
809 //
810 //*****************************************************************************
811 #define EMAC_TIMSECU_TSS_M 0xFFFFFFFF // Timestamp Second
812 #define EMAC_TIMSECU_TSS_S 0
813 
814 //*****************************************************************************
815 //
816 // The following are defines for the bit fields in the EMAC_O_TIMNANOU
817 // register.
818 //
819 //*****************************************************************************
820 #define EMAC_TIMNANOU_ADDSUB 0x80000000 // Add or subtract time
821 #define EMAC_TIMNANOU_TSSS_M 0x7FFFFFFF // Timestamp Sub-Second
822 #define EMAC_TIMNANOU_TSSS_S 0
823 
824 //*****************************************************************************
825 //
826 // The following are defines for the bit fields in the EMAC_O_TIMADD register.
827 //
828 //*****************************************************************************
829 #define EMAC_TIMADD_TSAR_M 0xFFFFFFFF // Timestamp Addend Register
830 #define EMAC_TIMADD_TSAR_S 0
831 
832 //*****************************************************************************
833 //
834 // The following are defines for the bit fields in the EMAC_O_TARGSEC register.
835 //
836 //*****************************************************************************
837 #define EMAC_TARGSEC_TSTR_M 0xFFFFFFFF // Target Time Seconds Register
838 #define EMAC_TARGSEC_TSTR_S 0
839 
840 //*****************************************************************************
841 //
842 // The following are defines for the bit fields in the EMAC_O_TARGNANO
843 // register.
844 //
845 //*****************************************************************************
846 #define EMAC_TARGNANO_TRGTBUSY 0x80000000 // Target Time Register Busy
847 #define EMAC_TARGNANO_TTSLO_M 0x7FFFFFFF // Target Timestamp Low Register
848 #define EMAC_TARGNANO_TTSLO_S 0
849 
850 //*****************************************************************************
851 //
852 // The following are defines for the bit fields in the EMAC_O_HWORDSEC
853 // register.
854 //
855 //*****************************************************************************
856 #define EMAC_HWORDSEC_TSHWR_M 0x0000FFFF // Target Timestamp Higher Word
857  // Register
858 #define EMAC_HWORDSEC_TSHWR_S 0
859 
860 //*****************************************************************************
861 //
862 // The following are defines for the bit fields in the EMAC_O_TIMSTAT register.
863 //
864 //*****************************************************************************
865 #define EMAC_TIMSTAT_TSTARGT 0x00000002 // Timestamp Target Time Reached
866 #define EMAC_TIMSTAT_TSSOVF 0x00000001 // Timestamp Seconds Overflow
867 
868 //*****************************************************************************
869 //
870 // The following are defines for the bit fields in the EMAC_O_PPSCTRL register.
871 //
872 //*****************************************************************************
873 #define EMAC_PPSCTRL_TRGMODS0_M 0x00000060 // Target Time Register Mode for
874  // PPS0 Output
875 #define EMAC_PPSCTRL_TRGMODS0_INTONLY \
876  0x00000000 // Indicates that the Target Time
877  // registers are programmed only
878  // for generating the interrupt
879  // event
880 #define EMAC_PPSCTRL_TRGMODS0_INTPPS0 \
881  0x00000040 // Indicates that the Target Time
882  // registers are programmed for
883  // generating the interrupt event
884  // and starting or stopping the
885  // generation of the EN0PPS output
886  // signal
887 #define EMAC_PPSCTRL_TRGMODS0_PPS0ONLY \
888  0x00000060 // Indicates that the Target Time
889  // registers are programmed only
890  // for starting or stopping the
891  // generation of the EN0PPS output
892  // signal. No interrupt is asserted
893 #define EMAC_PPSCTRL_PPSEN0 0x00000010 // Flexible PPS Output Mode Enable
894 #define EMAC_PPSCTRL_PPSCTRL_M 0x0000000F // EN0PPS Output Frequency Control
895  // (PPSCTRL) or Command Control
896  // (PPSCMD)
897 
898 //*****************************************************************************
899 //
900 // The following are defines for the bit fields in the EMAC_O_PPS0INTVL
901 // register.
902 //
903 //*****************************************************************************
904 #define EMAC_PPS0INTVL_PPS0INT_M \
905  0xFFFFFFFF // PPS0 Output Signal Interval
906 #define EMAC_PPS0INTVL_PPS0INT_S \
907  0
908 
909 //*****************************************************************************
910 //
911 // The following are defines for the bit fields in the EMAC_O_PPS0WIDTH
912 // register.
913 //
914 //*****************************************************************************
915 #define EMAC_PPS0WIDTH_M 0xFFFFFFFF // EN0PPS Output Signal Width
916 #define EMAC_PPS0WIDTH_S 0
917 
918 //*****************************************************************************
919 //
920 // The following are defines for the bit fields in the EMAC_O_DMABUSMOD
921 // register.
922 //
923 //*****************************************************************************
924 #define EMAC_DMABUSMOD_RIB 0x80000000 // Rebuild Burst
925 #define EMAC_DMABUSMOD_TXPR 0x08000000 // Transmit Priority
926 #define EMAC_DMABUSMOD_MB 0x04000000 // Mixed Burst
927 #define EMAC_DMABUSMOD_AAL 0x02000000 // Address Aligned Beats
928 #define EMAC_DMABUSMOD_8XPBL 0x01000000 // 8 x Programmable Burst Length
929  // (PBL) Mode
930 #define EMAC_DMABUSMOD_USP 0x00800000 // Use Separate Programmable Burst
931  // Length (PBL)
932 #define EMAC_DMABUSMOD_RPBL_M 0x007E0000 // RX DMA Programmable Burst Length
933  // (PBL)
934 #define EMAC_DMABUSMOD_FB 0x00010000 // Fixed Burst
935 #define EMAC_DMABUSMOD_PR_M 0x0000C000 // Priority Ratio
936 #define EMAC_DMABUSMOD_PBL_M 0x00003F00 // Programmable Burst Length
937 #define EMAC_DMABUSMOD_ATDS 0x00000080 // Alternate Descriptor Size
938 #define EMAC_DMABUSMOD_DSL_M 0x0000007C // Descriptor Skip Length
939 #define EMAC_DMABUSMOD_DA 0x00000002 // DMA Arbitration Scheme
940 #define EMAC_DMABUSMOD_SWR 0x00000001 // DMA Software Reset
941 #define EMAC_DMABUSMOD_RPBL_S 17
942 #define EMAC_DMABUSMOD_PR_S 14
943 #define EMAC_DMABUSMOD_PBL_S 8
944 #define EMAC_DMABUSMOD_DSL_S 2
945 
946 //*****************************************************************************
947 //
948 // The following are defines for the bit fields in the EMAC_O_TXPOLLD register.
949 //
950 //*****************************************************************************
951 #define EMAC_TXPOLLD_TPD_M 0xFFFFFFFF // Transmit Poll Demand
952 #define EMAC_TXPOLLD_TPD_S 0
953 
954 //*****************************************************************************
955 //
956 // The following are defines for the bit fields in the EMAC_O_RXPOLLD register.
957 //
958 //*****************************************************************************
959 #define EMAC_RXPOLLD_RPD_M 0xFFFFFFFF // Receive Poll Demand
960 #define EMAC_RXPOLLD_RPD_S 0
961 
962 //*****************************************************************************
963 //
964 // The following are defines for the bit fields in the EMAC_O_RXDLADDR
965 // register.
966 //
967 //*****************************************************************************
968 #define EMAC_RXDLADDR_STRXLIST_M \
969  0xFFFFFFFC // Start of Receive List
970 #define EMAC_RXDLADDR_STRXLIST_S \
971  2
972 
973 //*****************************************************************************
974 //
975 // The following are defines for the bit fields in the EMAC_O_TXDLADDR
976 // register.
977 //
978 //*****************************************************************************
979 #define EMAC_TXDLADDR_TXDLADDR_M \
980  0xFFFFFFFC // Start of Transmit List Base
981  // Address
982 #define EMAC_TXDLADDR_TXDLADDR_S \
983  2
984 
985 //*****************************************************************************
986 //
987 // The following are defines for the bit fields in the EMAC_O_DMARIS register.
988 //
989 //*****************************************************************************
990 #define EMAC_DMARIS_LPI 0x40000000 // LPI Trigger Interrupt Status
991 #define EMAC_DMARIS_TT 0x20000000 // Timestamp Trigger Interrupt
992  // Status
993 #define EMAC_DMARIS_PMT 0x10000000 // MAC PMT Interrupt Status
994 #define EMAC_DMARIS_MMC 0x08000000 // MAC MMC Interrupt
995 #define EMAC_DMARIS_AE_M 0x03800000 // Access Error
996 #define EMAC_DMARIS_AE_RXDMAWD 0x00000000 // Error during RX DMA Write Data
997  // Transfer
998 #define EMAC_DMARIS_AE_TXDMARD 0x01800000 // Error during TX DMA Read Data
999  // Transfer
1000 #define EMAC_DMARIS_AE_RXDMADW 0x02000000 // Error during RX DMA Descriptor
1001  // Write Access
1002 #define EMAC_DMARIS_AE_TXDMADW 0x02800000 // Error during TX DMA Descriptor
1003  // Write Access
1004 #define EMAC_DMARIS_AE_RXDMADR 0x03000000 // Error during RX DMA Descriptor
1005  // Read Access
1006 #define EMAC_DMARIS_AE_TXDMADR 0x03800000 // Error during TX DMA Descriptor
1007  // Read Access
1008 #define EMAC_DMARIS_TS_M 0x00700000 // Transmit Process State
1009 #define EMAC_DMARIS_TS_STOP 0x00000000 // Stopped; Reset or Stop transmit
1010  // command processed
1011 #define EMAC_DMARIS_TS_RUNTXTD 0x00100000 // Running; Fetching transmit
1012  // transfer descriptor
1013 #define EMAC_DMARIS_TS_STATUS 0x00200000 // Running; Waiting for status
1014 #define EMAC_DMARIS_TS_RUNTX 0x00300000 // Running; Reading data from host
1015  // memory buffer and queuing it to
1016  // transmit buffer (TX FIFO)
1017 #define EMAC_DMARIS_TS_TSTAMP 0x00400000 // Writing Timestamp
1018 #define EMAC_DMARIS_TS_SUSPEND 0x00600000 // Suspended; Transmit descriptor
1019  // unavailable or transmit buffer
1020  // underflow
1021 #define EMAC_DMARIS_TS_RUNCTD 0x00700000 // Running; Closing transmit
1022  // descriptor
1023 #define EMAC_DMARIS_RS_M 0x000E0000 // Received Process State
1024 #define EMAC_DMARIS_RS_STOP 0x00000000 // Stopped: Reset or stop receive
1025  // command issued
1026 #define EMAC_DMARIS_RS_RUNRXTD 0x00020000 // Running: Fetching receive
1027  // transfer descriptor
1028 #define EMAC_DMARIS_RS_RUNRXD 0x00060000 // Running: Waiting for receive
1029  // packet
1030 #define EMAC_DMARIS_RS_SUSPEND 0x00080000 // Suspended: Receive descriptor
1031  // unavailable
1032 #define EMAC_DMARIS_RS_RUNCRD 0x000A0000 // Running: Closing receive
1033  // descriptor
1034 #define EMAC_DMARIS_RS_TSWS 0x000C0000 // Writing Timestamp
1035 #define EMAC_DMARIS_RS_RUNTXD 0x000E0000 // Running: Transferring the
1036  // receive packet data from receive
1037  // buffer to host memory
1038 #define EMAC_DMARIS_NIS 0x00010000 // Normal Interrupt Summary
1039 #define EMAC_DMARIS_AIS 0x00008000 // Abnormal Interrupt Summary
1040 #define EMAC_DMARIS_ERI 0x00004000 // Early Receive Interrupt
1041 #define EMAC_DMARIS_FBI 0x00002000 // Fatal Bus Error Interrupt
1042 #define EMAC_DMARIS_ETI 0x00000400 // Early Transmit Interrupt
1043 #define EMAC_DMARIS_RWT 0x00000200 // Receive Watchdog Timeout
1044 #define EMAC_DMARIS_RPS 0x00000100 // Receive Process Stopped
1045 #define EMAC_DMARIS_RU 0x00000080 // Receive Buffer Unavailable
1046 #define EMAC_DMARIS_RI 0x00000040 // Receive Interrupt
1047 #define EMAC_DMARIS_UNF 0x00000020 // Transmit Underflow
1048 #define EMAC_DMARIS_OVF 0x00000010 // Receive Overflow
1049 #define EMAC_DMARIS_TJT 0x00000008 // Transmit Jabber Timeout
1050 #define EMAC_DMARIS_TU 0x00000004 // Transmit Buffer Unavailable
1051 #define EMAC_DMARIS_TPS 0x00000002 // Transmit Process Stopped
1052 #define EMAC_DMARIS_TI 0x00000001 // Transmit Interrupt
1053 
1054 //*****************************************************************************
1055 //
1056 // The following are defines for the bit fields in the EMAC_O_DMAOPMODE
1057 // register.
1058 //
1059 //*****************************************************************************
1060 #define EMAC_DMAOPMODE_DT 0x04000000 // Disable Dropping of TCP/IP
1061  // Checksum Error Frames
1062 #define EMAC_DMAOPMODE_RSF 0x02000000 // Receive Store and Forward
1063 #define EMAC_DMAOPMODE_DFF 0x01000000 // Disable Flushing of Received
1064  // Frames
1065 #define EMAC_DMAOPMODE_TSF 0x00200000 // Transmit Store and Forward
1066 #define EMAC_DMAOPMODE_FTF 0x00100000 // Flush Transmit FIFO
1067 #define EMAC_DMAOPMODE_TTC_M 0x0001C000 // Transmit Threshold Control
1068 #define EMAC_DMAOPMODE_TTC_64 0x00000000 // 64 bytes
1069 #define EMAC_DMAOPMODE_TTC_128 0x00004000 // 128 bytes
1070 #define EMAC_DMAOPMODE_TTC_192 0x00008000 // 192 bytes
1071 #define EMAC_DMAOPMODE_TTC_256 0x0000C000 // 256 bytes
1072 #define EMAC_DMAOPMODE_TTC_40 0x00010000 // 40 bytes
1073 #define EMAC_DMAOPMODE_TTC_32 0x00014000 // 32 bytes
1074 #define EMAC_DMAOPMODE_TTC_24 0x00018000 // 24 bytes
1075 #define EMAC_DMAOPMODE_TTC_16 0x0001C000 // 16 bytes
1076 #define EMAC_DMAOPMODE_ST 0x00002000 // Start or Stop Transmission
1077  // Command
1078 #define EMAC_DMAOPMODE_FEF 0x00000080 // Forward Error Frames
1079 #define EMAC_DMAOPMODE_FUF 0x00000040 // Forward Undersized Good Frames
1080 #define EMAC_DMAOPMODE_DGF 0x00000020 // Drop Giant Frame Enable
1081 #define EMAC_DMAOPMODE_RTC_M 0x00000018 // Receive Threshold Control
1082 #define EMAC_DMAOPMODE_RTC_64 0x00000000 // 64 bytes
1083 #define EMAC_DMAOPMODE_RTC_32 0x00000008 // 32 bytes
1084 #define EMAC_DMAOPMODE_RTC_96 0x00000010 // 96 bytes
1085 #define EMAC_DMAOPMODE_RTC_128 0x00000018 // 128 bytes
1086 #define EMAC_DMAOPMODE_OSF 0x00000004 // Operate on Second Frame
1087 #define EMAC_DMAOPMODE_SR 0x00000002 // Start or Stop Receive
1088 
1089 //*****************************************************************************
1090 //
1091 // The following are defines for the bit fields in the EMAC_O_DMAIM register.
1092 //
1093 //*****************************************************************************
1094 #define EMAC_DMAIM_NIE 0x00010000 // Normal Interrupt Summary Enable
1095 #define EMAC_DMAIM_AIE 0x00008000 // Abnormal Interrupt Summary
1096  // Enable
1097 #define EMAC_DMAIM_ERE 0x00004000 // Early Receive Interrupt Enable
1098 #define EMAC_DMAIM_FBE 0x00002000 // Fatal Bus Error Enable
1099 #define EMAC_DMAIM_ETE 0x00000400 // Early Transmit Interrupt Enable
1100 #define EMAC_DMAIM_RWE 0x00000200 // Receive Watchdog Timeout Enable
1101 #define EMAC_DMAIM_RSE 0x00000100 // Receive Stopped Enable
1102 #define EMAC_DMAIM_RUE 0x00000080 // Receive Buffer Unavailable
1103  // Enable
1104 #define EMAC_DMAIM_RIE 0x00000040 // Receive Interrupt Enable
1105 #define EMAC_DMAIM_UNE 0x00000020 // Underflow Interrupt Enable
1106 #define EMAC_DMAIM_OVE 0x00000010 // Overflow Interrupt Enable
1107 #define EMAC_DMAIM_TJE 0x00000008 // Transmit Jabber Timeout Enable
1108 #define EMAC_DMAIM_TUE 0x00000004 // Transmit Buffer Unvailable
1109  // Enable
1110 #define EMAC_DMAIM_TSE 0x00000002 // Transmit Stopped Enable
1111 #define EMAC_DMAIM_TIE 0x00000001 // Transmit Interrupt Enable
1112 
1113 //*****************************************************************************
1114 //
1115 // The following are defines for the bit fields in the EMAC_O_MFBOC register.
1116 //
1117 //*****************************************************************************
1118 #define EMAC_MFBOC_OVFCNTOVF 0x10000000 // Overflow Bit for FIFO Overflow
1119  // Counter
1120 #define EMAC_MFBOC_OVFFRMCNT_M 0x0FFE0000 // Overflow Frame Counter
1121 #define EMAC_MFBOC_MISCNTOVF 0x00010000 // Overflow bit for Missed Frame
1122  // Counter
1123 #define EMAC_MFBOC_MISFRMCNT_M 0x0000FFFF // Missed Frame Counter
1124 #define EMAC_MFBOC_OVFFRMCNT_S 17
1125 #define EMAC_MFBOC_MISFRMCNT_S 0
1126 
1127 //*****************************************************************************
1128 //
1129 // The following are defines for the bit fields in the EMAC_O_RXINTWDT
1130 // register.
1131 //
1132 //*****************************************************************************
1133 #define EMAC_RXINTWDT_RIWT_M 0x000000FF // Receive Interrupt Watchdog Timer
1134  // Count
1135 #define EMAC_RXINTWDT_RIWT_S 0
1136 
1137 //*****************************************************************************
1138 //
1139 // The following are defines for the bit fields in the EMAC_O_HOSTXDESC
1140 // register.
1141 //
1142 //*****************************************************************************
1143 #define EMAC_HOSTXDESC_CURTXDESC_M \
1144  0xFFFFFFFF // Host Transmit Descriptor Address
1145  // Pointer
1146 #define EMAC_HOSTXDESC_CURTXDESC_S \
1147  0
1148 
1149 //*****************************************************************************
1150 //
1151 // The following are defines for the bit fields in the EMAC_O_HOSRXDESC
1152 // register.
1153 //
1154 //*****************************************************************************
1155 #define EMAC_HOSRXDESC_CURRXDESC_M \
1156  0xFFFFFFFF // Host Receive Descriptor Address
1157  // Pointer
1158 #define EMAC_HOSRXDESC_CURRXDESC_S \
1159  0
1160 
1161 //*****************************************************************************
1162 //
1163 // The following are defines for the bit fields in the EMAC_O_HOSTXBA register.
1164 //
1165 //*****************************************************************************
1166 #define EMAC_HOSTXBA_CURTXBUFA_M \
1167  0xFFFFFFFF // Host Transmit Buffer Address
1168  // Pointer
1169 #define EMAC_HOSTXBA_CURTXBUFA_S \
1170  0
1171 
1172 //*****************************************************************************
1173 //
1174 // The following are defines for the bit fields in the EMAC_O_HOSRXBA register.
1175 //
1176 //*****************************************************************************
1177 #define EMAC_HOSRXBA_CURRXBUFA_M \
1178  0xFFFFFFFF // Host Receive Buffer Address
1179  // Pointer
1180 #define EMAC_HOSRXBA_CURRXBUFA_S \
1181  0
1182 
1183 //*****************************************************************************
1184 //
1185 // The following are defines for the bit fields in the EMAC_O_PP register.
1186 //
1187 //*****************************************************************************
1188 #define EMAC_PP_MACTYPE_M 0x00000700 // Ethernet MAC Type
1189 #define EMAC_PP_MACTYPE_1 0x00000100 // MSP432E4x class MAC
1190 #define EMAC_PP_PHYTYPE_M 0x00000007 // Ethernet PHY Type
1191 #define EMAC_PP_PHYTYPE_NONE 0x00000000 // No PHY
1192 #define EMAC_PP_PHYTYPE_1 0x00000003 // MSP432E4x class PHY
1193 
1194 //*****************************************************************************
1195 //
1196 // The following are defines for the bit fields in the EMAC_O_PC register.
1197 //
1198 //*****************************************************************************
1199 #define EMAC_PC_PHYEXT 0x80000000 // PHY Select
1200 #define EMAC_PC_PINTFS_M 0x70000000 // Ethernet Interface Select
1201 #define EMAC_PC_PINTFS_IMII 0x00000000 // MII (default) Used for internal
1202  // PHY or external PHY connected
1203  // via MII
1204 #define EMAC_PC_PINTFS_RMII 0x40000000 // RMII: Used for external PHY
1205  // connected via RMII
1206 #define EMAC_PC_DIGRESTART 0x02000000 // PHY Soft Restart
1207 #define EMAC_PC_NIBDETDIS 0x01000000 // Odd Nibble TXER Detection
1208  // Disable
1209 #define EMAC_PC_RXERIDLE 0x00800000 // RXER Detection During Idle
1210 #define EMAC_PC_ISOMIILL 0x00400000 // Isolate MII in Link Loss
1211 #define EMAC_PC_LRR 0x00200000 // Link Loss Recovery
1212 #define EMAC_PC_TDRRUN 0x00100000 // TDR Auto Run
1213 #define EMAC_PC_FASTLDMODE_M 0x000F8000 // Fast Link Down Mode
1214 #define EMAC_PC_POLSWAP 0x00004000 // Polarity Swap
1215 #define EMAC_PC_MDISWAP 0x00002000 // MDI Swap
1216 #define EMAC_PC_RBSTMDIX 0x00001000 // Robust Auto MDI-X
1217 #define EMAC_PC_FASTMDIX 0x00000800 // Fast Auto MDI-X
1218 #define EMAC_PC_MDIXEN 0x00000400 // MDIX Enable
1219 #define EMAC_PC_FASTRXDV 0x00000200 // Fast RXDV Detection
1220 #define EMAC_PC_FASTLUPD 0x00000100 // FAST Link-Up in Parallel Detect
1221 #define EMAC_PC_EXTFD 0x00000080 // Extended Full Duplex Ability
1222 #define EMAC_PC_FASTANEN 0x00000040 // Fast Auto Negotiation Enable
1223 #define EMAC_PC_FASTANSEL_M 0x00000030 // Fast Auto Negotiation Select
1224 #define EMAC_PC_ANEN 0x00000008 // Auto Negotiation Enable
1225 #define EMAC_PC_ANMODE_M 0x00000006 // Auto Negotiation Mode
1226 #define EMAC_PC_ANMODE_10HD 0x00000000 // When ANEN = 0x0, the mode is
1227  // 10Base-T, Half-Duplex
1228 #define EMAC_PC_ANMODE_10FD 0x00000002 // When ANEN = 0x0, the mode is
1229  // 10Base-T, Full-Duplex
1230 #define EMAC_PC_ANMODE_100HD 0x00000004 // When ANEN = 0x0, the mode is
1231  // 100Base-TX, Half-Duplex
1232 #define EMAC_PC_ANMODE_100FD 0x00000006 // When ANEN = 0x0, the mode is
1233  // 100Base-TX, Full-Duplex
1234 #define EMAC_PC_PHYHOLD 0x00000001 // Ethernet PHY Hold
1235 #define EMAC_PC_FASTLDMODE_S 15
1236 #define EMAC_PC_FASTANSEL_S 4
1237 
1238 //*****************************************************************************
1239 //
1240 // The following are defines for the bit fields in the EMAC_O_CC register.
1241 //
1242 //*****************************************************************************
1243 #define EMAC_CC_PTPCEN 0x00040000 // PTP Clock Reference Enable
1244 #define EMAC_CC_POL 0x00020000 // LED Polarity Control
1245 #define EMAC_CC_CLKEN 0x00010000 // EN0RREF_CLK Signal Enable
1246 
1247 //*****************************************************************************
1248 //
1249 // The following are defines for the bit fields in the EMAC_O_EPHYRIS register.
1250 //
1251 //*****************************************************************************
1252 #define EMAC_EPHYRIS_INT 0x00000001 // Ethernet PHY Raw Interrupt
1253  // Status
1254 
1255 //*****************************************************************************
1256 //
1257 // The following are defines for the bit fields in the EMAC_O_EPHYIM register.
1258 //
1259 //*****************************************************************************
1260 #define EMAC_EPHYIM_INT 0x00000001 // Ethernet PHY Interrupt Mask
1261 
1262 //*****************************************************************************
1263 //
1264 // The following are defines for the bit fields in the EMAC_O_EPHYMISC
1265 // register.
1266 //
1267 //*****************************************************************************
1268 #define EMAC_EPHYMISC_INT 0x00000001 // Ethernet PHY Status and Clear
1269  // register
1270 
1271 //*****************************************************************************
1272 //
1273 // The following are defines for the EPHY register offsets.
1274 //
1275 //*****************************************************************************
1276 #define EPHY_BMCR 0x00000000 // Ethernet PHY Basic Mode Control
1277 #define EPHY_BMSR 0x00000001 // Ethernet PHY Basic Mode Status
1278 #define EPHY_ID1 0x00000002 // Ethernet PHY Identifier Register
1279  // 1
1280 #define EPHY_ID2 0x00000003 // Ethernet PHY Identifier Register
1281  // 2
1282 #define EPHY_ANA 0x00000004 // Ethernet PHY Auto-Negotiation
1283  // Advertisement
1284 #define EPHY_ANLPA 0x00000005 // Ethernet PHY Auto-Negotiation
1285  // Link Partner Ability
1286 #define EPHY_ANER 0x00000006 // Ethernet PHY Auto-Negotiation
1287  // Expansion
1288 #define EPHY_ANNPTR 0x00000007 // Ethernet PHY Auto-Negotiation
1289  // Next Page TX
1290 #define EPHY_ANLNPTR 0x00000008 // Ethernet PHY Auto-Negotiation
1291  // Link Partner Ability Next Page
1292 #define EPHY_CFG1 0x00000009 // Ethernet PHY Configuration 1
1293 #define EPHY_CFG2 0x0000000A // Ethernet PHY Configuration 2
1294 #define EPHY_CFG3 0x0000000B // Ethernet PHY Configuration 3
1295 #define EPHY_REGCTL 0x0000000D // Ethernet PHY Register Control
1296 #define EPHY_ADDAR 0x0000000E // Ethernet PHY Address or Data
1297 #define EPHY_STS 0x00000010 // Ethernet PHY Status
1298 #define EPHY_SCR 0x00000011 // Ethernet PHY Specific Control
1299 #define EPHY_MISR1 0x00000012 // Ethernet PHY MII Interrupt
1300  // Status 1
1301 #define EPHY_MISR2 0x00000013 // Ethernet PHY MII Interrupt
1302  // Status 2
1303 #define EPHY_FCSCR 0x00000014 // Ethernet PHY False Carrier Sense
1304  // Counter
1305 #define EPHY_RXERCNT 0x00000015 // Ethernet PHY Receive Error Count
1306 #define EPHY_BISTCR 0x00000016 // Ethernet PHY BIST Control
1307 #define EPHY_LEDCR 0x00000018 // Ethernet PHY LED Control
1308 #define EPHY_CTL 0x00000019 // Ethernet PHY Control
1309 #define EPHY_10BTSC 0x0000001A // Ethernet PHY 10Base-T
1310  // Status/Control - MR26
1311 #define EPHY_BICSR1 0x0000001B // Ethernet PHY BIST Control and
1312  // Status 1
1313 #define EPHY_BICSR2 0x0000001C // Ethernet PHY BIST Control and
1314  // Status 2
1315 #define EPHY_CDCR 0x0000001E // Ethernet PHY Cable Diagnostic
1316  // Control
1317 #define EPHY_RCR 0x0000001F // Ethernet PHY Reset Control
1318 #define EPHY_LEDCFG 0x00000025 // Ethernet PHY LED Configuration
1319 
1320 //*****************************************************************************
1321 //
1322 // The following are defines for the bit fields in the EPHY_BMCR register.
1323 //
1324 //*****************************************************************************
1325 #define EPHY_BMCR_MIIRESET 0x00008000 // MII Register reset
1326 #define EPHY_BMCR_MIILOOPBK 0x00004000 // MII Loopback
1327 #define EPHY_BMCR_SPEED 0x00002000 // Speed Select
1328 #define EPHY_BMCR_ANEN 0x00001000 // Auto-Negotiate Enable
1329 #define EPHY_BMCR_PWRDWN 0x00000800 // Power Down
1330 #define EPHY_BMCR_ISOLATE 0x00000400 // Port Isolate
1331 #define EPHY_BMCR_RESTARTAN 0x00000200 // Restart Auto-Negotiation
1332 #define EPHY_BMCR_DUPLEXM 0x00000100 // Duplex Mode
1333 #define EPHY_BMCR_COLLTST 0x00000080 // Collision Test
1334 
1335 //*****************************************************************************
1336 //
1337 // The following are defines for the bit fields in the EPHY_BMSR register.
1338 //
1339 //*****************************************************************************
1340 #define EPHY_BMSR_100BTXFD 0x00004000 // 100Base-TX Full Duplex Capable
1341 #define EPHY_BMSR_100BTXHD 0x00002000 // 100Base-TX Half Duplex Capable
1342 #define EPHY_BMSR_10BTFD 0x00001000 // 10 Base-T Full Duplex Capable
1343 #define EPHY_BMSR_10BTHD 0x00000800 // 10 Base-T Half Duplex Capable
1344 #define EPHY_BMSR_MFPRESUP 0x00000040 // Preamble Suppression Capable
1345 #define EPHY_BMSR_ANC 0x00000020 // Auto-Negotiation Complete
1346 #define EPHY_BMSR_RFAULT 0x00000010 // Remote Fault
1347 #define EPHY_BMSR_ANEN 0x00000008 // Auto Negotiation Enabled
1348 #define EPHY_BMSR_LINKSTAT 0x00000004 // Link Status
1349 #define EPHY_BMSR_JABBER 0x00000002 // Jabber Detect
1350 #define EPHY_BMSR_EXTEN 0x00000001 // Extended Capability Enable
1351 
1352 //*****************************************************************************
1353 //
1354 // The following are defines for the bit fields in the EPHY_ID1 register.
1355 //
1356 //*****************************************************************************
1357 #define EPHY_ID1_OUIMSB_M 0x0000FFFF // OUI Most Significant Bits
1358 #define EPHY_ID1_OUIMSB_S 0
1359 
1360 //*****************************************************************************
1361 //
1362 // The following are defines for the bit fields in the EPHY_ID2 register.
1363 //
1364 //*****************************************************************************
1365 #define EPHY_ID2_OUILSB_M 0x0000FC00 // OUI Least Significant Bits
1366 #define EPHY_ID2_VNDRMDL_M 0x000003F0 // Vendor Model Number
1367 #define EPHY_ID2_MDLREV_M 0x0000000F // Model Revision Number
1368 #define EPHY_ID2_OUILSB_S 10
1369 #define EPHY_ID2_VNDRMDL_S 4
1370 #define EPHY_ID2_MDLREV_S 0
1371 
1372 //*****************************************************************************
1373 //
1374 // The following are defines for the bit fields in the EPHY_ANA register.
1375 //
1376 //*****************************************************************************
1377 #define EPHY_ANA_NP 0x00008000 // Next Page Indication
1378 #define EPHY_ANA_RF 0x00002000 // Remote Fault
1379 #define EPHY_ANA_ASMDUP 0x00000800 // Asymmetric PAUSE support for
1380  // Full Duplex Links
1381 #define EPHY_ANA_PAUSE 0x00000400 // PAUSE Support for Full Duplex
1382  // Links
1383 #define EPHY_ANA_100BT4 0x00000200 // 100Base-T4 Support
1384 #define EPHY_ANA_100BTXFD 0x00000100 // 100Base-TX Full Duplex Support
1385 #define EPHY_ANA_100BTX 0x00000080 // 100Base-TX Support
1386 #define EPHY_ANA_10BTFD 0x00000040 // 10Base-T Full Duplex Support
1387 #define EPHY_ANA_10BT 0x00000020 // 10Base-T Support
1388 #define EPHY_ANA_SELECT_M 0x0000001F // Protocol Selection
1389 #define EPHY_ANA_SELECT_S 0
1390 
1391 //*****************************************************************************
1392 //
1393 // The following are defines for the bit fields in the EPHY_ANLPA register.
1394 //
1395 //*****************************************************************************
1396 #define EPHY_ANLPA_NP 0x00008000 // Next Page Indication
1397 #define EPHY_ANLPA_ACK 0x00004000 // Acknowledge
1398 #define EPHY_ANLPA_RF 0x00002000 // Remote Fault
1399 #define EPHY_ANLPA_ASMDUP 0x00000800 // Asymmetric PAUSE
1400 #define EPHY_ANLPA_PAUSE 0x00000400 // PAUSE
1401 #define EPHY_ANLPA_100BT4 0x00000200 // 100Base-T4 Support
1402 #define EPHY_ANLPA_100BTXFD 0x00000100 // 100Base-TX Full Duplex Support
1403 #define EPHY_ANLPA_100BTX 0x00000080 // 100Base-TX Support
1404 #define EPHY_ANLPA_10BTFD 0x00000040 // 10Base-T Full Duplex Support
1405 #define EPHY_ANLPA_10BT 0x00000020 // 10Base-T Support
1406 #define EPHY_ANLPA_SELECT_M 0x0000001F // Protocol Selection
1407 #define EPHY_ANLPA_SELECT_S 0
1408 
1409 //*****************************************************************************
1410 //
1411 // The following are defines for the bit fields in the EPHY_ANER register.
1412 //
1413 //*****************************************************************************
1414 #define EPHY_ANER_PDF 0x00000010 // Parallel Detection Fault
1415 #define EPHY_ANER_LPNPABLE 0x00000008 // Link Partner Next Page Able
1416 #define EPHY_ANER_NPABLE 0x00000004 // Next Page Able
1417 #define EPHY_ANER_PAGERX 0x00000002 // Link Code Word Page Received
1418 #define EPHY_ANER_LPANABLE 0x00000001 // Link Partner Auto-Negotiation
1419  // Able
1420 
1421 //*****************************************************************************
1422 //
1423 // The following are defines for the bit fields in the EPHY_ANNPTR register.
1424 //
1425 //*****************************************************************************
1426 #define EPHY_ANNPTR_NP 0x00008000 // Next Page Indication
1427 #define EPHY_ANNPTR_MP 0x00002000 // Message Page
1428 #define EPHY_ANNPTR_ACK2 0x00001000 // Acknowledge 2
1429 #define EPHY_ANNPTR_TOGTX 0x00000800 // Toggle
1430 #define EPHY_ANNPTR_CODE_M 0x000007FF // Code
1431 #define EPHY_ANNPTR_CODE_S 0
1432 
1433 //*****************************************************************************
1434 //
1435 // The following are defines for the bit fields in the EPHY_ANLNPTR register.
1436 //
1437 //*****************************************************************************
1438 #define EPHY_ANLNPTR_NP 0x00008000 // Next Page Indication
1439 #define EPHY_ANLNPTR_ACK 0x00004000 // Acknowledge
1440 #define EPHY_ANLNPTR_MP 0x00002000 // Message Page
1441 #define EPHY_ANLNPTR_ACK2 0x00001000 // Acknowledge 2
1442 #define EPHY_ANLNPTR_TOG 0x00000800 // Toggle
1443 #define EPHY_ANLNPTR_CODE_M 0x000007FF // Code
1444 #define EPHY_ANLNPTR_CODE_S 0
1445 
1446 //*****************************************************************************
1447 //
1448 // The following are defines for the bit fields in the EPHY_CFG1 register.
1449 //
1450 //*****************************************************************************
1451 #define EPHY_CFG1_DONE 0x00008000 // Configuration Done
1452 #define EPHY_CFG1_TDRAR 0x00000100 // TDR Auto-Run at Link Down
1453 #define EPHY_CFG1_LLR 0x00000080 // Link Loss Recovery
1454 #define EPHY_CFG1_FAMDIX 0x00000040 // Fast Auto MDI/MDIX
1455 #define EPHY_CFG1_RAMDIX 0x00000020 // Robust Auto MDI/MDIX
1456 #define EPHY_CFG1_FASTANEN 0x00000010 // Fast Auto Negotiation Enable
1457 #define EPHY_CFG1_FANSEL_M 0x0000000C // Fast Auto-Negotiation Select
1458  // Configuration
1459 #define EPHY_CFG1_FANSEL_BLT80 0x00000000 // Break Link Timer: 80 ms
1460 #define EPHY_CFG1_FANSEL_BLT120 0x00000004 // Break Link Timer: 120 ms
1461 #define EPHY_CFG1_FANSEL_BLT240 0x00000008 // Break Link Timer: 240 ms
1462 #define EPHY_CFG1_FRXDVDET 0x00000002 // FAST RXDV Detection
1463 
1464 //*****************************************************************************
1465 //
1466 // The following are defines for the bit fields in the EPHY_CFG2 register.
1467 //
1468 //*****************************************************************************
1469 #define EPHY_CFG2_FLUPPD 0x00000040 // Fast Link-Up in Parallel Detect
1470  // Mode
1471 #define EPHY_CFG2_EXTFD 0x00000020 // Extended Full-Duplex Ability
1472 #define EPHY_CFG2_ENLEDLINK 0x00000010 // Enhanced LED Functionality
1473 #define EPHY_CFG2_ISOMIILL 0x00000008 // Isolate MII outputs when
1474  // Enhanced Link is not Achievable
1475 #define EPHY_CFG2_RXERRIDLE 0x00000004 // Detection of Receive Symbol
1476  // Error During IDLE State
1477 #define EPHY_CFG2_ODDNDETDIS 0x00000002 // Detection of Transmit Error
1478 
1479 //*****************************************************************************
1480 //
1481 // The following are defines for the bit fields in the EPHY_CFG3 register.
1482 //
1483 //*****************************************************************************
1484 #define EPHY_CFG3_POLSWAP 0x00000080 // Polarity Swap
1485 #define EPHY_CFG3_MDIMDIXS 0x00000040 // MDI/MDIX Swap
1486 #define EPHY_CFG3_FLDWNM_M 0x0000001F // Fast Link Down Modes
1487 #define EPHY_CFG3_FLDWNM_S 0
1488 
1489 //*****************************************************************************
1490 //
1491 // The following are defines for the bit fields in the EPHY_REGCTL register.
1492 //
1493 //*****************************************************************************
1494 #define EPHY_REGCTL_FUNC_M 0x0000C000 // Function
1495 #define EPHY_REGCTL_FUNC_ADDR 0x00000000 // Address
1496 #define EPHY_REGCTL_FUNC_DATANI 0x00004000 // Data, no post increment
1497 #define EPHY_REGCTL_FUNC_DATAPIRW \
1498  0x00008000 // Data, post increment on read and
1499  // write
1500 #define EPHY_REGCTL_FUNC_DATAPIWO \
1501  0x0000C000 // Data, post increment on write
1502  // only
1503 #define EPHY_REGCTL_DEVAD_M 0x0000001F // Device Address
1504 #define EPHY_REGCTL_DEVAD_S 0
1505 
1506 //*****************************************************************************
1507 //
1508 // The following are defines for the bit fields in the EPHY_ADDAR register.
1509 //
1510 //*****************************************************************************
1511 #define EPHY_ADDAR_ADDRDATA_M 0x0000FFFF // Address or Data
1512 #define EPHY_ADDAR_ADDRDATA_S 0
1513 
1514 //*****************************************************************************
1515 //
1516 // The following are defines for the bit fields in the EPHY_STS register.
1517 //
1518 //*****************************************************************************
1519 #define EPHY_STS_MDIXM 0x00004000 // MDI-X Mode
1520 #define EPHY_STS_RXLERR 0x00002000 // Receive Error Latch
1521 #define EPHY_STS_POLSTAT 0x00001000 // Polarity Status
1522 #define EPHY_STS_FCSL 0x00000800 // False Carrier Sense Latch
1523 #define EPHY_STS_SD 0x00000400 // Signal Detect
1524 #define EPHY_STS_DL 0x00000200 // Descrambler Lock
1525 #define EPHY_STS_PAGERX 0x00000100 // Link Code Page Received
1526 #define EPHY_STS_MIIREQ 0x00000080 // MII Interrupt Pending
1527 #define EPHY_STS_RF 0x00000040 // Remote Fault
1528 #define EPHY_STS_JD 0x00000020 // Jabber Detect
1529 #define EPHY_STS_ANS 0x00000010 // Auto-Negotiation Status
1530 #define EPHY_STS_MIILB 0x00000008 // MII Loopback Status
1531 #define EPHY_STS_DUPLEX 0x00000004 // Duplex Status
1532 #define EPHY_STS_SPEED 0x00000002 // Speed Status
1533 #define EPHY_STS_LINK 0x00000001 // Link Status
1534 
1535 //*****************************************************************************
1536 //
1537 // The following are defines for the bit fields in the EPHY_SCR register.
1538 //
1539 //*****************************************************************************
1540 #define EPHY_SCR_DISCLK 0x00008000 // Disable CLK
1541 #define EPHY_SCR_PSEN 0x00004000 // Power Saving Modes Enable
1542 #define EPHY_SCR_PSMODE_M 0x00003000 // Power Saving Modes
1543 #define EPHY_SCR_PSMODE_NORMAL 0x00000000 // Normal: Normal operation mode.
1544  // PHY is fully functional
1545 #define EPHY_SCR_PSMODE_LOWPWR 0x00001000 // IEEE Power Down
1546 #define EPHY_SCR_PSMODE_ACTWOL 0x00002000 // Active Sleep
1547 #define EPHY_SCR_PSMODE_PASWOL 0x00003000 // Passive Sleep
1548 #define EPHY_SCR_SBPYASS 0x00000800 // Scrambler Bypass
1549 #define EPHY_SCR_LBFIFO_M 0x00000300 // Loopback FIFO Depth
1550 #define EPHY_SCR_LBFIFO_4 0x00000000 // Four nibble FIFO
1551 #define EPHY_SCR_LBFIFO_5 0x00000100 // Five nibble FIFO
1552 #define EPHY_SCR_LBFIFO_6 0x00000200 // Six nibble FIFO
1553 #define EPHY_SCR_LBFIFO_8 0x00000300 // Eight nibble FIFO
1554 #define EPHY_SCR_COLFDM 0x00000010 // Collision in Full-Duplex Mode
1555 #define EPHY_SCR_TINT 0x00000004 // Test Interrupt
1556 #define EPHY_SCR_INTEN 0x00000002 // Interrupt Enable
1557 
1558 //*****************************************************************************
1559 //
1560 // The following are defines for the bit fields in the EPHY_MISR1 register.
1561 //
1562 //*****************************************************************************
1563 #define EPHY_MISR1_LINKSTAT 0x00002000 // Change of Link Status Interrupt
1564 #define EPHY_MISR1_SPEED 0x00001000 // Change of Speed Status Interrupt
1565 #define EPHY_MISR1_DUPLEXM 0x00000800 // Change of Duplex Status
1566  // Interrupt
1567 #define EPHY_MISR1_ANC 0x00000400 // Auto-Negotiation Complete
1568  // Interrupt
1569 #define EPHY_MISR1_FCHF 0x00000200 // False Carrier Counter Half-Full
1570  // Interrupt
1571 #define EPHY_MISR1_RXHF 0x00000100 // Receive Error Counter Half-Full
1572  // Interrupt
1573 #define EPHY_MISR1_LINKSTATEN 0x00000020 // Link Status Interrupt Enable
1574 #define EPHY_MISR1_SPEEDEN 0x00000010 // Speed Change Interrupt Enable
1575 #define EPHY_MISR1_DUPLEXMEN 0x00000008 // Duplex Status Interrupt Enable
1576 #define EPHY_MISR1_ANCEN 0x00000004 // Auto-Negotiation Complete
1577  // Interrupt Enable
1578 #define EPHY_MISR1_FCHFEN 0x00000002 // False Carrier Counter Register
1579  // half-full Interrupt Enable
1580 #define EPHY_MISR1_RXHFEN 0x00000001 // Receive Error Counter Register
1581  // Half-Full Event Interrupt
1582 
1583 //*****************************************************************************
1584 //
1585 // The following are defines for the bit fields in the EPHY_MISR2 register.
1586 //
1587 //*****************************************************************************
1588 #define EPHY_MISR2_ANERR 0x00004000 // Auto-Negotiation Error Interrupt
1589 #define EPHY_MISR2_PAGERX 0x00002000 // Page Receive Interrupt
1590 #define EPHY_MISR2_LBFIFO 0x00001000 // Loopback FIFO Overflow/Underflow
1591  // Event Interrupt
1592 #define EPHY_MISR2_MDICO 0x00000800 // MDI/MDIX Crossover Status
1593  // Changed Interrupt
1594 #define EPHY_MISR2_SLEEP 0x00000400 // Sleep Mode Event Interrupt
1595 #define EPHY_MISR2_POLINT 0x00000200 // Polarity Changed Interrupt
1596 #define EPHY_MISR2_JABBER 0x00000100 // Jabber Detect Event Interrupt
1597 #define EPHY_MISR2_ANERREN 0x00000040 // Auto-Negotiation Error Interrupt
1598  // Enable
1599 #define EPHY_MISR2_PAGERXEN 0x00000020 // Page Receive Interrupt Enable
1600 #define EPHY_MISR2_LBFIFOEN 0x00000010 // Loopback FIFO Overflow/Underflow
1601  // Interrupt Enable
1602 #define EPHY_MISR2_MDICOEN 0x00000008 // MDI/MDIX Crossover Status
1603  // Changed Interrupt Enable
1604 #define EPHY_MISR2_SLEEPEN 0x00000004 // Sleep Mode Event Interrupt
1605  // Enable
1606 #define EPHY_MISR2_POLINTEN 0x00000002 // Polarity Changed Interrupt
1607  // Enable
1608 #define EPHY_MISR2_JABBEREN 0x00000001 // Jabber Detect Event Interrupt
1609  // Enable
1610 
1611 //*****************************************************************************
1612 //
1613 // The following are defines for the bit fields in the EPHY_FCSCR register.
1614 //
1615 //*****************************************************************************
1616 #define EPHY_FCSCR_FCSCNT_M 0x000000FF // False Carrier Event Counter
1617 #define EPHY_FCSCR_FCSCNT_S 0
1618 
1619 //*****************************************************************************
1620 //
1621 // The following are defines for the bit fields in the EPHY_RXERCNT register.
1622 //
1623 //*****************************************************************************
1624 #define EPHY_RXERCNT_RXERRCNT_M 0x0000FFFF // Receive Error Count
1625 #define EPHY_RXERCNT_RXERRCNT_S 0
1626 
1627 //*****************************************************************************
1628 //
1629 // The following are defines for the bit fields in the EPHY_BISTCR register.
1630 //
1631 //*****************************************************************************
1632 #define EPHY_BISTCR_PRBSM 0x00004000 // PRBS Single/Continuous Mode
1633 #define EPHY_BISTCR_PRBSPKT 0x00002000 // Generated PRBS Packets
1634 #define EPHY_BISTCR_PKTEN 0x00001000 // Packet Generation Enable
1635 #define EPHY_BISTCR_PRBSCHKLK 0x00000800 // PRBS Checker Lock Indication
1636 #define EPHY_BISTCR_PRBSCHKSYNC 0x00000400 // PRBS Checker Lock Sync Loss
1637  // Indication
1638 #define EPHY_BISTCR_PKTGENSTAT 0x00000200 // Packet Generator Status
1639  // Indication
1640 #define EPHY_BISTCR_PWRMODE 0x00000100 // Power Mode Indication
1641 #define EPHY_BISTCR_TXMIILB 0x00000040 // Transmit Data in MII Loopback
1642  // Mode
1643 #define EPHY_BISTCR_LBMODE_M 0x0000001F // Loopback Mode Select
1644 #define EPHY_BISTCR_LBMODE_NPCSIN \
1645  0x00000001 // Near-end loopback: PCS Input
1646  // Loopback
1647 #define EPHY_BISTCR_LBMODE_NPCSOUT \
1648  0x00000002 // Near-end loopback: PCS Output
1649  // Loopback (In 100Base-TX only)
1650 #define EPHY_BISTCR_LBMODE_NDIG 0x00000004 // Near-end loopback: Digital
1651  // Loopback
1652 #define EPHY_BISTCR_LBMODE_NANA 0x00000008 // Near-end loopback: Analog
1653  // Loopback (requires 100 Ohm
1654  // termination)
1655 #define EPHY_BISTCR_LBMODE_FREV 0x00000010 // Far-end Loopback: Reverse
1656  // Loopback
1657 
1658 //*****************************************************************************
1659 //
1660 // The following are defines for the bit fields in the EPHY_LEDCR register.
1661 //
1662 //*****************************************************************************
1663 #define EPHY_LEDCR_BLINKRATE_M 0x00000600 // LED Blinking Rate (ON/OFF
1664  // duration):
1665 #define EPHY_LEDCR_BLINKRATE_20HZ \
1666  0x00000000 // 20 Hz (50 ms)
1667 #define EPHY_LEDCR_BLINKRATE_10HZ \
1668  0x00000200 // 10 Hz (100 ms)
1669 #define EPHY_LEDCR_BLINKRATE_5HZ \
1670  0x00000400 // 5 Hz (200 ms)
1671 #define EPHY_LEDCR_BLINKRATE_2HZ \
1672  0x00000600 // 2 Hz (500 ms)
1673 
1674 //*****************************************************************************
1675 //
1676 // The following are defines for the bit fields in the EPHY_CTL register.
1677 //
1678 //*****************************************************************************
1679 #define EPHY_CTL_AUTOMDI 0x00008000 // Auto-MDIX Enable
1680 #define EPHY_CTL_FORCEMDI 0x00004000 // Force MDIX
1681 #define EPHY_CTL_PAUSERX 0x00002000 // Pause Receive Negotiated Status
1682 #define EPHY_CTL_PAUSETX 0x00001000 // Pause Transmit Negotiated Status
1683 #define EPHY_CTL_MIILNKSTAT 0x00000800 // MII Link Status
1684 #define EPHY_CTL_BYPLEDSTRCH 0x00000080 // Bypass LED Stretching
1685 
1686 //*****************************************************************************
1687 //
1688 // The following are defines for the bit fields in the EPHY_10BTSC register.
1689 //
1690 //*****************************************************************************
1691 #define EPHY_10BTSC_RXTHEN 0x00002000 // Lower Receiver Threshold Enable
1692 #define EPHY_10BTSC_SQUELCH_M 0x00001E00 // Squelch Configuration
1693 #define EPHY_10BTSC_NLPDIS 0x00000080 // Normal Link Pulse (NLP)
1694  // Transmission Control
1695 #define EPHY_10BTSC_POLSTAT 0x00000010 // 10 Mb Polarity Status
1696 #define EPHY_10BTSC_JABBERD 0x00000001 // Jabber Disable
1697 #define EPHY_10BTSC_SQUELCH_S 9
1698 
1699 //*****************************************************************************
1700 //
1701 // The following are defines for the bit fields in the EPHY_BICSR1 register.
1702 //
1703 //*****************************************************************************
1704 #define EPHY_BICSR1_ERRCNT_M 0x0000FF00 // BIST Error Count
1705 #define EPHY_BICSR1_IPGLENGTH_M 0x000000FF // BIST IPG Length
1706 #define EPHY_BICSR1_ERRCNT_S 8
1707 #define EPHY_BICSR1_IPGLENGTH_S 0
1708 
1709 //*****************************************************************************
1710 //
1711 // The following are defines for the bit fields in the EPHY_BICSR2 register.
1712 //
1713 //*****************************************************************************
1714 #define EPHY_BICSR2_PKTLENGTH_M 0x000007FF // BIST Packet Length
1715 #define EPHY_BICSR2_PKTLENGTH_S 0
1716 
1717 //*****************************************************************************
1718 //
1719 // The following are defines for the bit fields in the EPHY_CDCR register.
1720 //
1721 //*****************************************************************************
1722 #define EPHY_CDCR_START 0x00008000 // Cable Diagnostic Process Start
1723 #define EPHY_CDCR_LINKQUAL_M 0x00000300 // Link Quality Indication
1724 #define EPHY_CDCR_LINKQUAL_GOOD 0x00000100 // Good Quality Link Indication
1725 #define EPHY_CDCR_LINKQUAL_MILD 0x00000200 // Mid- Quality Link Indication
1726 #define EPHY_CDCR_LINKQUAL_POOR 0x00000300 // Poor Quality Link Indication
1727 #define EPHY_CDCR_DONE 0x00000002 // Cable Diagnostic Process Done
1728 #define EPHY_CDCR_FAIL 0x00000001 // Cable Diagnostic Process Fail
1729 
1730 //*****************************************************************************
1731 //
1732 // The following are defines for the bit fields in the EPHY_RCR register.
1733 //
1734 //*****************************************************************************
1735 #define EPHY_RCR_SWRST 0x00008000 // Software Reset
1736 #define EPHY_RCR_SWRESTART 0x00004000 // Software Restart
1737 
1738 //*****************************************************************************
1739 //
1740 // The following are defines for the bit fields in the EPHY_LEDCFG register.
1741 //
1742 //*****************************************************************************
1743 #define EPHY_LEDCFG_LED2_M 0x00000F00 // LED2 Configuration
1744 #define EPHY_LEDCFG_LED2_LINK 0x00000000 // Link OK
1745 #define EPHY_LEDCFG_LED2_RXTX 0x00000100 // RX/TX Activity
1746 #define EPHY_LEDCFG_LED2_TX 0x00000200 // TX Activity
1747 #define EPHY_LEDCFG_LED2_RX 0x00000300 // RX Activity
1748 #define EPHY_LEDCFG_LED2_COL 0x00000400 // Collision
1749 #define EPHY_LEDCFG_LED2_100BT 0x00000500 // 100-Base TX
1750 #define EPHY_LEDCFG_LED2_10BT 0x00000600 // 10-Base TX
1751 #define EPHY_LEDCFG_LED2_FD 0x00000700 // Full Duplex
1752 #define EPHY_LEDCFG_LED2_LINKTXRX \
1753  0x00000800 // Link OK/Blink on TX/RX Activity
1754 #define EPHY_LEDCFG_LED1_M 0x000000F0 // LED1 Configuration
1755 #define EPHY_LEDCFG_LED1_LINK 0x00000000 // Link OK
1756 #define EPHY_LEDCFG_LED1_RXTX 0x00000010 // RX/TX Activity
1757 #define EPHY_LEDCFG_LED1_TX 0x00000020 // TX Activity
1758 #define EPHY_LEDCFG_LED1_RX 0x00000030 // RX Activity
1759 #define EPHY_LEDCFG_LED1_COL 0x00000040 // Collision
1760 #define EPHY_LEDCFG_LED1_100BT 0x00000050 // 100-Base TX
1761 #define EPHY_LEDCFG_LED1_10BT 0x00000060 // 10-Base TX
1762 #define EPHY_LEDCFG_LED1_FD 0x00000070 // Full Duplex
1763 #define EPHY_LEDCFG_LED1_LINKTXRX \
1764  0x00000080 // Link OK/Blink on TX/RX Activity
1765 #define EPHY_LEDCFG_LED0_M 0x0000000F // LED0 Configuration
1766 #define EPHY_LEDCFG_LED0_LINK 0x00000000 // Link OK
1767 #define EPHY_LEDCFG_LED0_RXTX 0x00000001 // RX/TX Activity
1768 #define EPHY_LEDCFG_LED0_TX 0x00000002 // TX Activity
1769 #define EPHY_LEDCFG_LED0_RX 0x00000003 // RX Activity
1770 #define EPHY_LEDCFG_LED0_COL 0x00000004 // Collision
1771 #define EPHY_LEDCFG_LED0_100BT 0x00000005 // 100-Base TX
1772 #define EPHY_LEDCFG_LED0_10BT 0x00000006 // 10-Base TX
1773 #define EPHY_LEDCFG_LED0_FD 0x00000007 // Full Duplex
1774 #define EPHY_LEDCFG_LED0_LINKTXRX \
1775  0x00000008 // Link OK/Blink on TX/RX Activity
1776 
1777 //*****************************************************************************
1778 //
1779 // The following definitions are deprecated.
1780 //
1781 //*****************************************************************************
1782 #ifndef DEPRECATED
1783 
1784 //*****************************************************************************
1785 //
1786 // The following are deprecated defines for the bit fields in the
1787 // EMAC_O_PPSCTRL register.
1788 //
1789 //*****************************************************************************
1790 #define EMAC_PPSCTRL_PPSCTRL_1HZ \
1791  0x00000000 // When the PPSEN0 bit = 0x0, the
1792  // EN0PPS signal is 1 pulse of the
1793  // PTP reference clock.(of width
1794  // clk_ptp_i) every second
1795 #define EMAC_PPSCTRL_PPSCTRL_2HZ \
1796  0x00000001 // When the PPSEN0 bit = 0x0, the
1797  // binary rollover is 2 Hz, and the
1798  // digital rollover is 1 Hz
1799 #define EMAC_PPSCTRL_PPSCTRL_4HZ \
1800  0x00000002 // When the PPSEN0 bit = 0x0, the
1801  // binary rollover is 4 Hz, and the
1802  // digital rollover is 2 Hz
1803 #define EMAC_PPSCTRL_PPSCTRL_8HZ \
1804  0x00000003 // When thePPSEN0 bit = 0x0, the
1805  // binary rollover is 8 Hz, and the
1806  // digital rollover is 4 Hz,
1807 #define EMAC_PPSCTRL_PPSCTRL_16HZ \
1808  0x00000004 // When thePPSEN0 bit = 0x0, the
1809  // binary rollover is 16 Hz, and
1810  // the digital rollover is 8 Hz
1811 #define EMAC_PPSCTRL_PPSCTRL_32HZ \
1812  0x00000005 // When thePPSEN0 bit = 0x0, the
1813  // binary rollover is 32 Hz, and
1814  // the digital rollover is 16 Hz
1815 #define EMAC_PPSCTRL_PPSCTRL_64HZ \
1816  0x00000006 // When thePPSEN0 bit = 0x0, the
1817  // binary rollover is 64 Hz, and
1818  // the digital rollover is 32 Hz
1819 #define EMAC_PPSCTRL_PPSCTRL_128HZ \
1820  0x00000007 // When thePPSEN0 bit = 0x0, the
1821  // binary rollover is 128 Hz, and
1822  // the digital rollover is 64 Hz
1823 #define EMAC_PPSCTRL_PPSCTRL_256HZ \
1824  0x00000008 // When thePPSEN0 bit = 0x0, the
1825  // binary rollover is 256 Hz, and
1826  // the digital rollover is 128 Hz
1827 #define EMAC_PPSCTRL_PPSCTRL_512HZ \
1828  0x00000009 // When thePPSEN0 bit = 0x0, the
1829  // binary rollover is 512 Hz, and
1830  // the digital rollover is 256 Hz
1831 #define EMAC_PPSCTRL_PPSCTRL_1024HZ \
1832  0x0000000A // When the PPSEN0 bit = 0x0, the
1833  // binary rollover is 1.024 kHz,
1834  // and the digital rollover is 512
1835  // Hz
1836 #define EMAC_PPSCTRL_PPSCTRL_2048HZ \
1837  0x0000000B // When thePPSEN0 bit = 0x0, the
1838  // binary rollover is 2.048 kHz,
1839  // and the digital rollover is
1840  // 1.024 kHz
1841 #define EMAC_PPSCTRL_PPSCTRL_4096HZ \
1842  0x0000000C // When thePPSEN0 bit = 0x0, the
1843  // binary rollover is 4.096 kHz,
1844  // and the digital rollover is
1845  // 2.048 kHz
1846 #define EMAC_PPSCTRL_PPSCTRL_8192HZ \
1847  0x0000000D // When thePPSEN0 bit = 0x0, the
1848  // binary rollover is 8.192 kHz,
1849  // and the digital rollover is
1850  // 4.096 kHz
1851 #define EMAC_PPSCTRL_PPSCTRL_16384HZ \
1852  0x0000000E // When thePPSEN0 bit = 0x0, the
1853  // binary rollover is 16.384 kHz,
1854  // and the digital rollover is
1855  // 8.092 kHz
1856 #define EMAC_PPSCTRL_PPSCTRL_32768HZ \
1857  0x0000000F // When thePPSEN0 bit = 0x0, the
1858  // binary rollover is 32.768 KHz,
1859  // and the digital rollover is
1860  // 16.384 KHz
1861 
1862 //*****************************************************************************
1863 //
1864 // The following are deprecated defines for the bit fields in the EMAC_O_CC
1865 // register.
1866 //
1867 //*****************************************************************************
1868 #define EMAC_CC_CS_PA7 0x00000001 // GPIO
1869 
1870 #endif
1871 
1872 #endif // __HW_EMAC_H__
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