Functions
void	I2CMasterInitExpClk (uint32_t ui32Base, uint32_t ui32I2CClk, bool bFast)

void	I2CSlaveInit (uint32_t ui32Base, uint8_t ui8SlaveAddr)

void	I2CSlaveAddressSet (uint32_t ui32Base, uint8_t ui8AddrNum, uint8_t ui8SlaveAddr)

void	I2CMasterEnable (uint32_t ui32Base)

void	I2CSlaveEnable (uint32_t ui32Base)

void	I2CMasterDisable (uint32_t ui32Base)

void	I2CSlaveDisable (uint32_t ui32Base)

void	I2CIntRegister (uint32_t ui32Base, void(*pfnHandler)(void))

void	I2CIntUnregister (uint32_t ui32Base)

void	I2CMasterIntEnable (uint32_t ui32Base)

void	I2CMasterIntEnableEx (uint32_t ui32Base, uint32_t ui32IntFlags)

void	I2CSlaveIntEnable (uint32_t ui32Base)

void	I2CSlaveIntEnableEx (uint32_t ui32Base, uint32_t ui32IntFlags)

void	I2CMasterIntDisable (uint32_t ui32Base)

void	I2CMasterIntDisableEx (uint32_t ui32Base, uint32_t ui32IntFlags)

void	I2CSlaveIntDisable (uint32_t ui32Base)

void	I2CSlaveIntDisableEx (uint32_t ui32Base, uint32_t ui32IntFlags)

bool	I2CMasterIntStatus (uint32_t ui32Base, bool bMasked)

uint32_t	I2CMasterIntStatusEx (uint32_t ui32Base, bool bMasked)

bool	I2CSlaveIntStatus (uint32_t ui32Base, bool bMasked)

uint32_t	I2CSlaveIntStatusEx (uint32_t ui32Base, bool bMasked)

void	I2CMasterIntClear (uint32_t ui32Base)

void	I2CMasterIntClearEx (uint32_t ui32Base, uint32_t ui32IntFlags)

void	I2CSlaveIntClear (uint32_t ui32Base)

void	I2CSlaveIntClearEx (uint32_t ui32Base, uint32_t ui32IntFlags)

void	I2CMasterSlaveAddrSet (uint32_t ui32Base, uint8_t ui8SlaveAddr, bool bReceive)

uint32_t	I2CMasterLineStateGet (uint32_t ui32Base)

bool	I2CMasterBusy (uint32_t ui32Base)

bool	I2CMasterBusBusy (uint32_t ui32Base)

void	I2CMasterControl (uint32_t ui32Base, uint32_t ui32Cmd)

uint32_t	I2CMasterErr (uint32_t ui32Base)

void	I2CMasterDataPut (uint32_t ui32Base, uint8_t ui8Data)

uint32_t	I2CMasterDataGet (uint32_t ui32Base)

void	I2CMasterTimeoutSet (uint32_t ui32Base, uint32_t ui32Value)

void	I2CSlaveACKOverride (uint32_t ui32Base, bool bEnable)

void	I2CSlaveACKValueSet (uint32_t ui32Base, bool bACK)

uint32_t	I2CSlaveStatus (uint32_t ui32Base)

void	I2CSlaveDataPut (uint32_t ui32Base, uint8_t ui8Data)

uint32_t	I2CSlaveDataGet (uint32_t ui32Base)

void	I2CTxFIFOConfigSet (uint32_t ui32Base, uint32_t ui32Config)

void	I2CTxFIFOFlush (uint32_t ui32Base)

void	I2CRxFIFOConfigSet (uint32_t ui32Base, uint32_t ui32Config)

void	I2CRxFIFOFlush (uint32_t ui32Base)

uint32_t	I2CFIFOStatus (uint32_t ui32Base)

void	I2CFIFODataPut (uint32_t ui32Base, uint8_t ui8Data)

uint32_t	I2CFIFODataPutNonBlocking (uint32_t ui32Base, uint8_t ui8Data)

uint32_t	I2CFIFODataGet (uint32_t ui32Base)

uint32_t	I2CFIFODataGetNonBlocking (uint32_t ui32Base, uint8_t *pui8Data)

void	I2CMasterBurstLengthSet (uint32_t ui32Base, uint8_t ui8Length)

uint32_t	I2CMasterBurstCountGet (uint32_t ui32Base)

void	I2CMasterGlitchFilterConfigSet (uint32_t ui32Base, uint32_t ui32Config)

void	I2CSlaveFIFOEnable (uint32_t ui32Base, uint32_t ui32Config)

void	I2CSlaveFIFODisable (uint32_t ui32Base)

void	I2CLoopbackEnable (uint32_t ui32Base)

Detailed Description

Function Documentation

§ I2CMasterInitExpClk()

void I2CMasterInitExpClk	(	uint32_t	ui32Base,
		uint32_t	ui32I2CClk,
		bool	bFast
	)

Initializes the I2C Master block.

Parameters

ui32Base	is the base address of the I2C module.
ui32I2CClk	is the rate of the clock supplied to the I2C module.
bFast	set up for fast data transfers.

This function initializes operation of the I2C Master block by configuring the bus speed for the master and enabling the I2C Master block.

If the parameter bFast is true, then the master block is set up to transfer data at 400 Kbps; otherwise, it is set up to transfer data at 100 Kbps. If Fast Mode Plus (1 Mbps) is desired, software should manually write the I2CMTPR after calling this function. For High Speed (3.4 Mbps) mode, a specific command is used to switch to the faster clocks after the initial communication with the slave is done at either 100 Kbps or 400 Kbps.

The peripheral clock is the same as the processor clock. The frequency of the system clock is the value returned by SysCtlClockFreqSet(), or it can be explicitly hard coded if it is constant and known (to save the code/execution overhead of fetch of the variable call holding the return value of SysCtlClockFreqSet()).

Returns: None.

References ASSERT, HWREG, I2C_MTPR_HS, I2C_O_MTPR, I2C_O_PP, I2C_PP_HS, and I2CMasterEnable().

§ I2CSlaveInit()

void I2CSlaveInit	(	uint32_t	ui32Base,
		uint8_t	ui8SlaveAddr
	)

Initializes the I2C Slave block.

Parameters

ui32Base	is the base address of the I2C module.
ui8SlaveAddr	7-bit slave address

This function initializes operation of the I2C Slave block by configuring the slave address and enabling the I2C Slave block.

The parameter ui8SlaveAddr is the value that is compared against the slave address sent by an I2C master.

Returns: None.

References ASSERT, HWREG, I2C_O_SOAR, and I2CSlaveEnable().

§ I2CSlaveAddressSet()

void I2CSlaveAddressSet	(	uint32_t	ui32Base,
		uint8_t	ui8AddrNum,
		uint8_t	ui8SlaveAddr
	)

Sets the I2C slave address.

Parameters

ui32Base	is the base address of the I2C module.
ui8AddrNum	determines which slave address is set.
ui8SlaveAddr	is the 7-bit slave address

This function writes the specified slave address. The ui32AddrNum field dictates which slave address is configured. For example, a value of 0 configures the primary address and a value of 1 configures the secondary.

Returns: None.

References ASSERT, HWREG, I2C_O_SOAR, I2C_O_SOAR2, and I2C_SOAR2_OAR2EN.

§ I2CMasterEnable()

void I2CMasterEnable ( uint32_t ui32Base )

Enables the I2C Master block.

Parameters

ui32Base is the base address of the I2C module.

This function enables operation of the I2C Master block.

Returns: None.

References ASSERT, HWREG, I2C_MCR_MFE, and I2C_O_MCR.

Referenced by I2CMasterInitExpClk().

§ I2CSlaveEnable()

void I2CSlaveEnable ( uint32_t ui32Base )

Enables the I2C Slave block.

Parameters

ui32Base is the base address of the I2C module.

This fucntion enables operation of the I2C Slave block.

Returns: None.

References ASSERT, HWREG, I2C_MCR_SFE, I2C_O_MCR, I2C_O_SCSR, and I2C_SCSR_DA.

Referenced by I2CSlaveInit().

§ I2CMasterDisable()

void I2CMasterDisable ( uint32_t ui32Base )

Disables the I2C master block.

Parameters

ui32Base is the base address of the I2C module.

This function disables operation of the I2C master block.

Returns: None.

References ASSERT, HWREG, I2C_MCR_MFE, and I2C_O_MCR.

§ I2CSlaveDisable()

void I2CSlaveDisable ( uint32_t ui32Base )

Disables the I2C slave block.

Parameters

ui32Base is the base address of the I2C module.

This function disables operation of the I2C slave block.

Returns: None.

References ASSERT, HWREG, I2C_MCR_SFE, I2C_O_MCR, and I2C_O_SCSR.

§ I2CIntRegister()

void I2CIntRegister	(	uint32_t	ui32Base,
		void(*)(void)	pfnHandler
	)

Registers an interrupt handler for the I2C module.

Parameters

ui32Base	is the base address of the I2C module.
pfnHandler	is a pointer to the function to be called when the I2C interrupt occurs.

This function sets the handler to be called when an I2C interrupt occurs. This function enables the global interrupt in the interrupt controller; specific I2C interrupts must be enabled via I2CMasterIntEnable() and I2CSlaveIntEnable(). If necessary, it is the interrupt handler's responsibility to clear the interrupt source via I2CMasterIntClear() and I2CSlaveIntClear().

See also: IntRegister() for important information about registering interrupt handlers.

Returns: None.

References ASSERT.

§ I2CIntUnregister()

void I2CIntUnregister ( uint32_t ui32Base )

Unregisters an interrupt handler for the I2C module.

Parameters

ui32Base is the base address of the I2C module.

This function clears the handler to be called when an I2C interrupt occurs. This function also masks off the interrupt in the interrupt r controller so that the interrupt handler no longer is called.

See also: IntRegister() for important information about registering interrupt handlers.

Returns: None.

References ASSERT.

§ I2CMasterIntEnable()

void I2CMasterIntEnable ( uint32_t ui32Base )

Enables the I2C Master interrupt.

Parameters

ui32Base is the base address of the I2C module.

This function enables the I2C Master interrupt source.

Returns: None.

References ASSERT, HWREG, and I2C_O_MIMR.

§ I2CMasterIntEnableEx()

void I2CMasterIntEnableEx	(	uint32_t	ui32Base,
		uint32_t	ui32IntFlags
	)

Enables individual I2C Master interrupt sources.

Parameters

ui32Base	is the base address of the I2C module.
ui32IntFlags	is the bit mask of the interrupt sources to be enabled.

This function enables the indicated I2C Master interrupt sources. Only the sources that are enabled can be reflected to the processor interrupt; disabled sources have no effect on the processor.

The ui32IntFlags parameter is the logical OR of any of the following:

I2C_MASTER_INT_RX_FIFO_FULL - RX FIFO Full interrupt
I2C_MASTER_INT_TX_FIFO_EMPTY - TX FIFO Empty interrupt
I2C_MASTER_INT_RX_FIFO_REQ - RX FIFO Request interrupt
I2C_MASTER_INT_TX_FIFO_REQ - TX FIFO Request interrupt
I2C_MASTER_INT_ARB_LOST - Arbitration Lost interrupt
I2C_MASTER_INT_STOP - Stop Condition interrupt
I2C_MASTER_INT_START - Start Condition interrupt
I2C_MASTER_INT_NACK - Address/Data NACK interrupt
I2C_MASTER_INT_TX_DMA_DONE - TX DMA Complete interrupt
I2C_MASTER_INT_RX_DMA_DONE - RX DMA Complete interrupt
I2C_MASTER_INT_TIMEOUT - Clock Timeout interrupt
I2C_MASTER_INT_DATA - Data interrupt

Returns: None.

References ASSERT, HWREG, and I2C_O_MIMR.

§ I2CSlaveIntEnable()

void I2CSlaveIntEnable ( uint32_t ui32Base )

Enables the I2C Slave interrupt.

Parameters

ui32Base is the base address of the I2C module.

This function enables the I2C Slave interrupt source.

Returns: None.

References ASSERT, HWREG, I2C_O_SIMR, and I2C_SLAVE_INT_DATA.

§ I2CSlaveIntEnableEx()

void I2CSlaveIntEnableEx	(	uint32_t	ui32Base,
		uint32_t	ui32IntFlags
	)

Enables individual I2C Slave interrupt sources.

Parameters

ui32Base	is the base address of the I2C module.
ui32IntFlags	is the bit mask of the interrupt sources to be enabled.

This function enables the indicated I2C Slave interrupt sources. Only the sources that are enabled can be reflected to the processor interrupt; disabled sources have no effect on the processor.

The ui32IntFlags parameter is the logical OR of any of the following:

I2C_SLAVE_INT_RX_FIFO_FULL - RX FIFO Full interrupt
I2C_SLAVE_INT_TX_FIFO_EMPTY - TX FIFO Empty interrupt
I2C_SLAVE_INT_RX_FIFO_REQ - RX FIFO Request interrupt
I2C_SLAVE_INT_TX_FIFO_REQ - TX FIFO Request interrupt
I2C_SLAVE_INT_TX_DMA_DONE - TX DMA Complete interrupt
I2C_SLAVE_INT_RX_DMA_DONE - RX DMA Complete interrupt
I2C_SLAVE_INT_STOP - Stop condition detected interrupt
I2C_SLAVE_INT_START - Start condition detected interrupt
I2C_SLAVE_INT_DATA - Data interrupt

Returns: None.

References ASSERT, HWREG, and I2C_O_SIMR.

§ I2CMasterIntDisable()

void I2CMasterIntDisable ( uint32_t ui32Base )

Disables the I2C Master interrupt.

Parameters

ui32Base is the base address of the I2C module.

This function disables the I2C Master interrupt source.

Returns: None.

References ASSERT, HWREG, and I2C_O_MIMR.

§ I2CMasterIntDisableEx()

void I2CMasterIntDisableEx	(	uint32_t	ui32Base,
		uint32_t	ui32IntFlags
	)

Disables individual I2C Master interrupt sources.

Parameters

ui32Base	is the base address of the I2C module.
ui32IntFlags	is the bit mask of the interrupt sources to be disabled.

This function disables the indicated I2C Master interrupt sources. Only the sources that are enabled can be reflected to the processor interrupt; disabled sources have no effect on the processor.

The ui32IntFlags parameter has the same definition as the ui32IntFlags parameter to I2CMasterIntEnableEx().

Returns: None.

References ASSERT, HWREG, and I2C_O_MIMR.

§ I2CSlaveIntDisable()

void I2CSlaveIntDisable ( uint32_t ui32Base )

Disables the I2C Slave interrupt.

Parameters

ui32Base is the base address of the I2C module.

This function disables the I2C Slave interrupt source.

Returns: None.

References ASSERT, HWREG, I2C_O_SIMR, and I2C_SLAVE_INT_DATA.

§ I2CSlaveIntDisableEx()

void I2CSlaveIntDisableEx	(	uint32_t	ui32Base,
		uint32_t	ui32IntFlags
	)

Disables individual I2C Slave interrupt sources.

Parameters

ui32Base	is the base address of the I2C module.
ui32IntFlags	is the bit mask of the interrupt sources to be disabled.

This function disables the indicated I2C Slave interrupt sources. Only the sources that are enabled can be reflected to the processor interrupt; disabled sources have no effect on the processor.

The ui32IntFlags parameter has the same definition as the ui32IntFlags parameter to I2CSlaveIntEnableEx().

Returns: None.

References ASSERT, HWREG, and I2C_O_SIMR.

§ I2CMasterIntStatus()

bool I2CMasterIntStatus	(	uint32_t	ui32Base,
		bool	bMasked
	)

Gets the current I2C Master interrupt status.

Parameters

ui32Base	is the base address of the I2C module.
bMasked	is false if the raw interrupt status is requested and true if the masked interrupt status is requested.

This function returns the interrupt status for the I2C module. Either the raw interrupt status or the status of interrupts that are allowed to reflect to the processor can be returned.

Returns: The current interrupt status, returned as true if active or false if not active.

References ASSERT, HWREG, I2C_O_MMIS, and I2C_O_MRIS.

§ I2CMasterIntStatusEx()

uint32_t I2CMasterIntStatusEx	(	uint32_t	ui32Base,
		bool	bMasked
	)

Gets the current I2C Master interrupt status.

Parameters

ui32Base	is the base address of the I2C module.
bMasked	is false if the raw interrupt status is requested and true if the masked interrupt status is requested.

This function returns the interrupt status for the I2C module. Either the raw interrupt status or the status of interrupts that are allowed to reflect to the processor can be returned.

Returns: Returns the current interrupt status, enumerated as a bit field of values described in I2CMasterIntEnableEx().

References ASSERT, HWREG, I2C_O_MMIS, and I2C_O_MRIS.

§ I2CSlaveIntStatus()

bool I2CSlaveIntStatus	(	uint32_t	ui32Base,
		bool	bMasked
	)

Gets the current I2C Slave interrupt status.

Parameters

ui32Base	is the base address of the I2C module.
bMasked	is false if the raw interrupt status is requested and true if the masked interrupt status is requested.

This function returns the interrupt status for the I2C Slave. Either the raw interrupt status or the status of interrupts that are allowed to reflect to the processor can be returned.

Returns: The current interrupt status, returned as true if active or false if not active.

References ASSERT, HWREG, I2C_O_SMIS, and I2C_O_SRIS.

§ I2CSlaveIntStatusEx()

uint32_t I2CSlaveIntStatusEx	(	uint32_t	ui32Base,
		bool	bMasked
	)

Gets the current I2C Slave interrupt status.

Parameters

ui32Base	is the base address of the I2C module.
bMasked	is false if the raw interrupt status is requested and true if the masked interrupt status is requested.

This function returns the interrupt status for the I2C Slave. Either the raw interrupt status or the status of interrupts that are allowed to reflect to the processor can be returned.

Returns: Returns the current interrupt status, enumerated as a bit field of values described in I2CSlaveIntEnableEx().

References ASSERT, HWREG, I2C_O_SMIS, and I2C_O_SRIS.

§ I2CMasterIntClear()

void I2CMasterIntClear ( uint32_t ui32Base )

Clears I2C Master interrupt sources.

Parameters

ui32Base is the base address of the I2C module.

The I2C Master interrupt source is cleared, so that it no longer asserts. This function must be called in the interrupt handler to keep the interrupt from being triggered again immediately upon exit.

Note: Because there is a write buffer in the Cortex-M processor, it may take several clock cycles before the interrupt source is actually cleared. Therefore, it is recommended that the interrupt source be cleared early in the interrupt handler (as opposed to the very last action) to avoid returning from the interrupt handler before the interrupt source is actually cleared. Failure to do so may result in the interrupt handler being immediately reentered (because the interrupt controller still sees the interrupt source asserted).

Returns: None.

References ASSERT, HWREG, I2C_MICR_IC, I2C_O_MICR, and I2C_O_MMIS.

§ I2CMasterIntClearEx()

void I2CMasterIntClearEx	(	uint32_t	ui32Base,
		uint32_t	ui32IntFlags
	)

Clears I2C Master interrupt sources.

Parameters

ui32Base	is the base address of the I2C module.
ui32IntFlags	is a bit mask of the interrupt sources to be cleared.

The specified I2C Master interrupt sources are cleared, so that they no longer assert. This function must be called in the interrupt handler to keep the interrupt from being triggered again immediately upon exit.

The ui32IntFlags parameter has the same definition as the ui32IntFlags parameter to I2CMasterIntEnableEx().

Note: Because there is a write buffer in the Cortex-M processor, it may take several clock cycles before the interrupt source is actually cleared. Therefore, it is recommended that the interrupt source be cleared early in the interrupt handler (as opposed to the very last action) to avoid returning from the interrupt handler before the interrupt source is actually cleared. Failure to do so may result in the interrupt handler being immediately reentered (because the interrupt controller still sees the interrupt source asserted).

Returns: None.

References ASSERT, HWREG, and I2C_O_MICR.

§ I2CSlaveIntClear()

void I2CSlaveIntClear ( uint32_t ui32Base )

Clears I2C Slave interrupt sources.

Parameters

ui32Base is the base address of the I2C module.

The I2C Slave interrupt source is cleared, so that it no longer asserts. This function must be called in the interrupt handler to keep the interrupt from being triggered again immediately upon exit.

Note: Because there is a write buffer in the Cortex-M processor, it may take several clock cycles before the interrupt source is actually cleared. Therefore, it is recommended that the interrupt source be cleared early in the interrupt handler (as opposed to the very last action) to avoid returning from the interrupt handler before the interrupt source is actually cleared. Failure to do so may result in the interrupt handler being immediately reentered (because the interrupt controller still sees the interrupt source asserted).

Returns: None.

References ASSERT, HWREG, I2C_O_SICR, and I2C_SICR_DATAIC.

§ I2CSlaveIntClearEx()

void I2CSlaveIntClearEx	(	uint32_t	ui32Base,
		uint32_t	ui32IntFlags
	)

Clears I2C Slave interrupt sources.

Parameters

ui32Base	is the base address of the I2C module.
ui32IntFlags	is a bit mask of the interrupt sources to be cleared.

The specified I2C Slave interrupt sources are cleared, so that they no longer assert. This function must be called in the interrupt handler to keep the interrupt from being triggered again immediately upon exit.

The ui32IntFlags parameter has the same definition as the ui32IntFlags parameter to I2CSlaveIntEnableEx().

Note: Because there is a write buffer in the Cortex-M processor, it may take several clock cycles before the interrupt source is actually cleared. Therefore, it is recommended that the interrupt source be cleared early in the interrupt handler (as opposed to the very last action) to avoid returning from the interrupt handler before the interrupt source is actually cleared. Failure to do so may result in the interrupt handler being immediately reentered (because the interrupt controller still sees the interrupt source asserted).

Returns: None.

References ASSERT, HWREG, and I2C_O_SICR.

§ I2CMasterSlaveAddrSet()

void I2CMasterSlaveAddrSet	(	uint32_t	ui32Base,
		uint8_t	ui8SlaveAddr,
		bool	bReceive
	)

Sets the address that the I2C Master places on the bus.

Parameters

ui32Base	is the base address of the I2C module.
ui8SlaveAddr	7-bit slave address
bReceive	flag indicating the type of communication with the slave

This function configures the address that the I2C Master places on the bus when initiating a transaction. When the bReceive parameter is set to true, the address indicates that the I2C Master is initiating a read from the slave; otherwise the address indicates that the I2C Master is initiating a write to the slave.

Returns: None.

References ASSERT, HWREG, and I2C_O_MSA.

§ I2CMasterLineStateGet()

uint32_t I2CMasterLineStateGet ( uint32_t ui32Base )

Reads the state of the SDA and SCL pins.

Parameters

ui32Base is the base address of the I2C module.

This function returns the state of the I2C bus by providing the real time values of the SDA and SCL pins.

Returns: Returns the state of the bus with SDA in bit position 1 and SCL in bit position 0.

References ASSERT, HWREG, and I2C_O_MBMON.

§ I2CMasterBusy()

bool I2CMasterBusy ( uint32_t ui32Base )

Indicates whether or not the I2C Master is busy.

Parameters

ui32Base is the base address of the I2C module.

This function returns an indication of whether or not the I2C Master is busy transmitting or receiving data.

Returns: Returns true if the I2C Master is busy; otherwise, returns false.

References ASSERT, HWREG, I2C_MCS_BUSY, and I2C_O_MCS.

§ I2CMasterBusBusy()

bool I2CMasterBusBusy ( uint32_t ui32Base )

Indicates whether or not the I2C bus is busy.

Parameters

ui32Base is the base address of the I2C module.

This function returns an indication of whether or not the I2C bus is busy. This function can be used in a multi-master environment to determine if another master is currently using the bus.

Returns: Returns true if the I2C bus is busy; otherwise, returns false.

References ASSERT, HWREG, I2C_MCS_BUSBSY, and I2C_O_MCS.

§ I2CMasterControl()

void I2CMasterControl	(	uint32_t	ui32Base,
		uint32_t	ui32Cmd
	)

Controls the state of the I2C Master.

Parameters

ui32Base	is the base address of the I2C module.
ui32Cmd	command to be issued to the I2C Master.

This function is used to control the state of the Master send and receive operations. The ui8Cmd parameter can be one of the following values:

I2C_MASTER_CMD_SINGLE_SEND
I2C_MASTER_CMD_SINGLE_RECEIVE
I2C_MASTER_CMD_BURST_SEND_START
I2C_MASTER_CMD_BURST_SEND_CONT
I2C_MASTER_CMD_BURST_SEND_FINISH
I2C_MASTER_CMD_BURST_SEND_ERROR_STOP
I2C_MASTER_CMD_BURST_RECEIVE_START
I2C_MASTER_CMD_BURST_RECEIVE_CONT
I2C_MASTER_CMD_BURST_RECEIVE_FINISH
I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP
I2C_MASTER_CMD_QUICK_COMMAND
I2C_MASTER_CMD_HS_MASTER_CODE_SEND
I2C_MASTER_CMD_FIFO_SINGLE_SEND
I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE
I2C_MASTER_CMD_FIFO_BURST_SEND_START
I2C_MASTER_CMD_FIFO_BURST_SEND_CONT
I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH
I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP
I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START
I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT
I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH
I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP

Returns: None.

§ I2CMasterErr()

uint32_t I2CMasterErr ( uint32_t ui32Base )

Gets the error status of the I2C Master.

Parameters

ui32Base is the base address of the I2C module.

This function is used to obtain the error status of the Master send and receive operations.

Returns: Returns the error status, as one of I2C_MASTER_ERR_NONE, I2C_MASTER_ERR_ADDR_ACK, I2C_MASTER_ERR_DATA_ACK, or I2C_MASTER_ERR_ARB_LOST.

References ASSERT, HWREG, I2C_MASTER_ERR_NONE, I2C_MCS_ADRACK, I2C_MCS_ARBLST, I2C_MCS_BUSY, I2C_MCS_DATACK, I2C_MCS_ERROR, and I2C_O_MCS.

§ I2CMasterDataPut()

void I2CMasterDataPut	(	uint32_t	ui32Base,
		uint8_t	ui8Data
	)

Transmits a byte from the I2C Master.

Parameters

ui32Base	is the base address of the I2C module.
ui8Data	data to be transmitted from the I2C Master.

This function places the supplied data into I2C Master Data Register.

Returns: None.

References ASSERT, HWREG, and I2C_O_MDR.

§ I2CMasterDataGet()

uint32_t I2CMasterDataGet ( uint32_t ui32Base )

Receives a byte that has been sent to the I2C Master.

Parameters

ui32Base is the base address of the I2C module.

This function reads a byte of data from the I2C Master Data Register.

Returns: Returns the byte received from by the I2C Master, cast as an uint32_t.

References ASSERT, HWREG, and I2C_O_MDR.

§ I2CMasterTimeoutSet()

void I2CMasterTimeoutSet	(	uint32_t	ui32Base,
		uint32_t	ui32Value
	)

Sets the Master clock timeout value.

Parameters

ui32Base	is the base address of the I2C module.
ui32Value	is the number of I2C clocks before the timeout is asserted.

This function enables and configures the clock low timeout feature in the I2C peripheral. This feature is implemented as a 12-bit counter, with the upper 8-bits being programmable. For example, to program a timeout of 20ms with a 100-kHz SCL frequency, ui32Value is 0x7d.

Returns: None.

References ASSERT, HWREG, and I2C_O_MCLKOCNT.

§ I2CSlaveACKOverride()

void I2CSlaveACKOverride	(	uint32_t	ui32Base,
		bool	bEnable
	)

Configures ACK override behavior of the I2C Slave.

Parameters

ui32Base	is the base address of the I2C module.
bEnable	enables or disables ACK override.

This function enables or disables ACK override, allowing the user application to drive the value on SDA during the ACK cycle.

Returns: None.

References ASSERT, HWREG, I2C_O_SACKCTL, and I2C_SACKCTL_ACKOEN.

§ I2CSlaveACKValueSet()

void I2CSlaveACKValueSet	(	uint32_t	ui32Base,
		bool	bACK
	)

Writes the ACK value.

Parameters

ui32Base	is the base address of the I2C module.
bACK	chooses whether to ACK (true) or NACK (false) the transfer.

This function puts the desired ACK value on SDA during the ACK cycle. The value written is only valid when ACK override is enabled using I2CSlaveACKOverride().

Returns: None.

References ASSERT, HWREG, I2C_O_SACKCTL, and I2C_SACKCTL_ACKOVAL.

§ I2CSlaveStatus()

uint32_t I2CSlaveStatus ( uint32_t ui32Base )

Gets the I2C Slave status

Parameters

ui32Base is the base address of the I2C module.

This function returns the action requested from a master, if any. Possible values are:

I2C_SLAVE_ACT_NONE
I2C_SLAVE_ACT_RREQ
I2C_SLAVE_ACT_TREQ
I2C_SLAVE_ACT_RREQ_FBR
I2C_SLAVE_ACT_OWN2SEL
I2C_SLAVE_ACT_QCMD
I2C_SLAVE_ACT_QCMD_DATA

Returns: Returns I2C_SLAVE_ACT_NONE to indicate that no action has been requested of the I2C Slave, I2C_SLAVE_ACT_RREQ to indicate that an I2C master has sent data to the I2C Slave, I2C_SLAVE_ACT_TREQ to indicate that an I2C master has requested that the I2C Slave send data, I2C_SLAVE_ACT_RREQ_FBR to indicate that an I2C master has sent data to the I2C slave and the first byte following the slave's own address has been received, I2C_SLAVE_ACT_OWN2SEL to indicate that the second I2C slave address was matched, I2C_SLAVE_ACT_QCMD to indicate that a quick command was received, and I2C_SLAVE_ACT_QCMD_DATA to indicate that the data bit was set when the quick command was received.

References ASSERT, HWREG, and I2C_O_SCSR.

§ I2CSlaveDataPut()

void I2CSlaveDataPut	(	uint32_t	ui32Base,
		uint8_t	ui8Data
	)

Transmits a byte from the I2C Slave.

Parameters

ui32Base	is the base address of the I2C module.
ui8Data	is the data to be transmitted from the I2C Slave

This function places the supplied data into I2C Slave Data Register.

Returns: None.

References ASSERT, HWREG, and I2C_O_SDR.

§ I2CSlaveDataGet()

uint32_t I2CSlaveDataGet ( uint32_t ui32Base )

Receives a byte that has been sent to the I2C Slave.

Parameters

ui32Base is the base address of the I2C module.

This function reads a byte of data from the I2C Slave Data Register.

Returns: Returns the byte received from by the I2C Slave, cast as an uint32_t.

References ASSERT, HWREG, and I2C_O_SDR.

§ I2CTxFIFOConfigSet()

void I2CTxFIFOConfigSet	(	uint32_t	ui32Base,
		uint32_t	ui32Config
	)

Configures the I2C transmit (TX) FIFO.

Parameters

ui32Base	is the base address of the I2C module.
ui32Config	is the configuration of the FIFO using specified macros.

This configures the I2C peripheral's transmit FIFO. The transmit FIFO can be used by the master or slave, but not both. The following macros are used to configure the TX FIFO behavior for master or slave, with or without DMA:

I2C_FIFO_CFG_TX_MASTER, I2C_FIFO_CFG_TX_SLAVE, I2C_FIFO_CFG_TX_MASTER_DMA, I2C_FIFO_CFG_TX_SLAVE_DMA

To select the trigger level, one of the following macros should be used:

I2C_FIFO_CFG_TX_TRIG_1, I2C_FIFO_CFG_TX_TRIG_2, I2C_FIFO_CFG_TX_TRIG_3, I2C_FIFO_CFG_TX_TRIG_4, I2C_FIFO_CFG_TX_TRIG_5, I2C_FIFO_CFG_TX_TRIG_6, I2C_FIFO_CFG_TX_TRIG_7, I2C_FIFO_CFG_TX_TRIG_8

Returns: None.

References ASSERT, HWREG, and I2C_O_FIFOCTL.

§ I2CTxFIFOFlush()

void I2CTxFIFOFlush ( uint32_t ui32Base )

Flushes the transmit (TX) FIFO.

Parameters

ui32Base is the base address of the I2C module.

This function flushes the I2C transmit FIFO.

Returns: None.

References ASSERT, HWREG, I2C_FIFOCTL_TXFLUSH, and I2C_O_FIFOCTL.

§ I2CRxFIFOConfigSet()

void I2CRxFIFOConfigSet	(	uint32_t	ui32Base,
		uint32_t	ui32Config
	)

Configures the I2C receive (RX) FIFO.

Parameters

ui32Base	is the base address of the I2C module.
ui32Config	is the configuration of the FIFO using specified macros.

This configures the I2C peripheral's receive FIFO. The receive FIFO can be used by the master or slave, but not both. The following macros are used to configure the RX FIFO behavior for master or slave, with or without DMA:

I2C_FIFO_CFG_RX_MASTER, I2C_FIFO_CFG_RX_SLAVE, I2C_FIFO_CFG_RX_MASTER_DMA, I2C_FIFO_CFG_RX_SLAVE_DMA

To select the trigger level, one of the following macros should be used:

I2C_FIFO_CFG_RX_TRIG_1, I2C_FIFO_CFG_RX_TRIG_2, I2C_FIFO_CFG_RX_TRIG_3, I2C_FIFO_CFG_RX_TRIG_4, I2C_FIFO_CFG_RX_TRIG_5, I2C_FIFO_CFG_RX_TRIG_6, I2C_FIFO_CFG_RX_TRIG_7, I2C_FIFO_CFG_RX_TRIG_8

Returns: None.

References ASSERT, HWREG, and I2C_O_FIFOCTL.

§ I2CRxFIFOFlush()

void I2CRxFIFOFlush ( uint32_t ui32Base )

Flushes the receive (RX) FIFO.

Parameters

ui32Base is the base address of the I2C module.

This function flushes the I2C receive FIFO.

Returns: None.

References ASSERT, HWREG, I2C_FIFOCTL_RXFLUSH, and I2C_O_FIFOCTL.

§ I2CFIFOStatus()

uint32_t I2CFIFOStatus ( uint32_t ui32Base )

Gets the current FIFO status.

Parameters

ui32Base is the base address of the I2C module.

This function retrieves the status for both the transmit (TX) and receive (RX) FIFOs. The trigger level for the transmit FIFO is set using I2CTxFIFOConfigSet() and for the receive FIFO using I2CTxFIFOConfigSet().

Returns: Returns the FIFO status, enumerated as a bit field containing I2C_FIFO_RX_BELOW_TRIG_LEVEL, I2C_FIFO_RX_FULL, I2C_FIFO_RX_EMPTY, I2C_FIFO_TX_BELOW_TRIG_LEVEL, I2C_FIFO_TX_FULL, and I2C_FIFO_TX_EMPTY.

References ASSERT, HWREG, and I2C_O_FIFOSTATUS.

§ I2CFIFODataPut()

void I2CFIFODataPut	(	uint32_t	ui32Base,
		uint8_t	ui8Data
	)

Writes a data byte to the I2C transmit FIFO.

Parameters

ui32Base	is the base address of the I2C module.
ui8Data	is the data to be placed into the transmit FIFO.

This function adds a byte of data to the I2C transmit FIFO. If there is no space available in the FIFO, this function waits for space to become available before returning.

Returns: None.

References ASSERT, HWREG, I2C_FIFOSTATUS_TXFF, I2C_O_FIFODATA, and I2C_O_FIFOSTATUS.

§ I2CFIFODataPutNonBlocking()

uint32_t I2CFIFODataPutNonBlocking	(	uint32_t	ui32Base,
		uint8_t	ui8Data
	)

Writes a data byte to the I2C transmit FIFO.

Parameters

ui32Base	is the base address of the I2C module.
ui8Data	is the data to be placed into the transmit FIFO.

This function adds a byte of data to the I2C transmit FIFO. If there is no space available in the FIFO, this function returns a zero.

Returns: The number of elements added to the I2C transmit FIFO.

References ASSERT, HWREG, I2C_FIFOSTATUS_TXFF, I2C_O_FIFODATA, and I2C_O_FIFOSTATUS.

§ I2CFIFODataGet()

uint32_t I2CFIFODataGet ( uint32_t ui32Base )

Reads a byte from the I2C receive FIFO.

Parameters

ui32Base is the base address of the I2C module.

This function reads a byte of data from I2C receive FIFO and places it in the location specified by the pui8Data parameter. If there is no data available, this function waits until data is received before returning.

Returns: The data byte.

References ASSERT, HWREG, I2C_FIFOSTATUS_RXFE, I2C_O_FIFODATA, and I2C_O_FIFOSTATUS.

§ I2CFIFODataGetNonBlocking()

uint32_t I2CFIFODataGetNonBlocking	(	uint32_t	ui32Base,
		uint8_t *	pui8Data
	)

Reads a byte from the I2C receive FIFO.

Parameters

ui32Base	is the base address of the I2C module.
pui8Data	is a pointer where the read data is stored.

This function reads a byte of data from I2C receive FIFO and places it in the location specified by the pui8Data parameter. If there is no data available, this functions returns 0.

Returns: The number of elements read from the I2C receive FIFO.

References ASSERT, HWREG, I2C_FIFOSTATUS_RXFE, I2C_O_FIFODATA, and I2C_O_FIFOSTATUS.

§ I2CMasterBurstLengthSet()

void I2CMasterBurstLengthSet	(	uint32_t	ui32Base,
		uint8_t	ui8Length
	)

Set the burst length for a I2C master FIFO operation.

Parameters

ui32Base	is the base address of the I2C module.
ui8Length	is the length of the burst transfer.

This function configures the burst length for a I2C Master FIFO operation. The burst field is limited to 8 bits or 256 bytes. The burst length applies to a single I2CMCS BURST operation meaning that it specifies the burst length for only the current operation (can be TX or RX). Each burst operation must configure the burst length prior to writing the BURST bit in the I2CMCS using I2CMasterControl().

Returns: None.

References ASSERT, HWREG, and I2C_O_MBLEN.

§ I2CMasterBurstCountGet()

uint32_t I2CMasterBurstCountGet ( uint32_t ui32Base )

Returns the current value of the burst transfer counter.

Parameters

ui32Base is the base address of the I2C module.

This function returns the current value of the burst transfer counter that is used by the FIFO mechanism. Software can use this value to determine how many bytes remain in a transfer, or where in the transfer the burst operation was if an error has occurred.

Returns: None.

References ASSERT, HWREG, and I2C_O_MBCNT.

§ I2CMasterGlitchFilterConfigSet()

void I2CMasterGlitchFilterConfigSet	(	uint32_t	ui32Base,
		uint32_t	ui32Config
	)

Configures the I2C Master glitch filter.

Parameters

ui32Base	is the base address of the I2C module.
ui32Config	is the glitch filter configuration.

This function configures the I2C Master glitch filter. The value passed in to ui32Config determines the sampling range of the glitch filter, which is configurable between 1 and 32 system clock cycles. The default configuration of the glitch filter is 0 system clock cycles, which means that it's disabled.

The ui32Config field should be any of the following values:

I2C_MASTER_GLITCH_FILTER_DISABLED
I2C_MASTER_GLITCH_FILTER_1
I2C_MASTER_GLITCH_FILTER_2
I2C_MASTER_GLITCH_FILTER_3
I2C_MASTER_GLITCH_FILTER_4
I2C_MASTER_GLITCH_FILTER_8
I2C_MASTER_GLITCH_FILTER_16
I2C_MASTER_GLITCH_FILTER_32

Returns: None.

References ASSERT, HWREG, and I2C_O_MTPR.

§ I2CSlaveFIFOEnable()

void I2CSlaveFIFOEnable	(	uint32_t	ui32Base,
		uint32_t	ui32Config
	)

Enables FIFO usage for the I2C Slave.

Parameters

ui32Base	is the base address of the I2C module.
ui32Config	is the desired FIFO configuration of the I2C Slave.

This function configures the I2C Slave to use the FIFO(s). This function should be used in combination with I2CTxFIFOConfigSet() and/or I2CRxFIFOConfigSet(), which configure the FIFO trigger level and tell the FIFO hardware whether to interact with the I2C Master or Slave. The application appropriate combination of I2C_SLAVE_TX_FIFO_ENABLE and I2C_SLAVE_RX_FIFO_ENABLE should be passed in to the ui32Config field.

The Slave I2CSCSR register is write-only, so any call to I2CSlaveEnable(), I2CSlaveDisable or I2CSlaveFIFOEnable() overwrites the slave configuration. Therefore, application software should call I2CSlaveEnable() followed by I2CSlaveFIFOEnable() with the desired FIFO configuration.

Returns: None.

References ASSERT, HWREG, I2C_O_SCSR, and I2C_SCSR_DA.

§ I2CSlaveFIFODisable()

void I2CSlaveFIFODisable ( uint32_t ui32Base )

Disable FIFO usage for the I2C Slave.

Parameters

ui32Base is the base address of the I2C module.

This function disables the FIFOs for the I2C Slave. After calling this this function, the FIFOs are disabled, but the Slave remains active.

Returns: None.

References ASSERT, HWREG, I2C_O_SCSR, and I2C_SCSR_DA.

§ I2CLoopbackEnable()

void I2CLoopbackEnable ( uint32_t ui32Base )

Enables internal loopback mode for an I2C port.

Parameters

ui32Base is the base address of the I2C module.

This function configures an I2C port in internal loopback mode to help with diagnostics and debug. In this mode, the SDA and SCL signals from master and slave modules are internally connected. This allows data to be transferred between the master and slave modules of the same I2C port, without having to go through I/O's. I2CMasterDataPut(), I2CSlaveDataPut(), I2CMasterDataGet(),I2CSlaveDataGet() can be used along with this function.

Returns: None.

References ASSERT, HWREG, I2C_MCR_LPBK, and I2C_O_MCR.

Functions

Detailed Description

Function Documentation

§ I2CMasterInitExpClk()

§ I2CSlaveInit()

§ I2CSlaveAddressSet()

§ I2CMasterEnable()

§ I2CSlaveEnable()

§ I2CMasterDisable()

§ I2CSlaveDisable()

§ I2CIntRegister()

§ I2CIntUnregister()

§ I2CMasterIntEnable()

§ I2CMasterIntEnableEx()

§ I2CSlaveIntEnable()

§ I2CSlaveIntEnableEx()

§ I2CMasterIntDisable()

§ I2CMasterIntDisableEx()

§ I2CSlaveIntDisable()

§ I2CSlaveIntDisableEx()

§ I2CMasterIntStatus()

§ I2CMasterIntStatusEx()

§ I2CSlaveIntStatus()

§ I2CSlaveIntStatusEx()

§ I2CMasterIntClear()

§ I2CMasterIntClearEx()

§ I2CSlaveIntClear()

§ I2CSlaveIntClearEx()

§ I2CMasterSlaveAddrSet()

§ I2CMasterLineStateGet()

§ I2CMasterBusy()

§ I2CMasterBusBusy()

§ I2CMasterControl()

§ I2CMasterErr()

§ I2CMasterDataPut()

§ I2CMasterDataGet()

§ I2CMasterTimeoutSet()

§ I2CSlaveACKOverride()

§ I2CSlaveACKValueSet()

§ I2CSlaveStatus()

§ I2CSlaveDataPut()

§ I2CSlaveDataGet()

§ I2CTxFIFOConfigSet()

§ I2CTxFIFOFlush()

§ I2CRxFIFOConfigSet()

§ I2CRxFIFOFlush()

§ I2CFIFOStatus()

§ I2CFIFODataPut()

§ I2CFIFODataPutNonBlocking()

§ I2CFIFODataGet()

§ I2CFIFODataGetNonBlocking()

§ I2CMasterBurstLengthSet()

§ I2CMasterBurstCountGet()

§ I2CMasterGlitchFilterConfigSet()

§ I2CSlaveFIFOEnable()

§ I2CSlaveFIFODisable()

§ I2CLoopbackEnable()