Structure defining a performance level. More...
#include <PowerMSP432.h>
Data Fields | |
unsigned int | activeState |
The active state for the device. More... | |
unsigned int | VCORE |
The core voltage level. More... | |
unsigned int | clockSource |
The clock source for this performance level. More... | |
unsigned int | DCORESEL |
The DCO frequency range selection. More... | |
unsigned int | SELM |
The MCLK source. More... | |
unsigned int | DIVM |
The MCLK source divider. More... | |
unsigned int | SELS |
The HSMCLK and SMCLK source. More... | |
unsigned int | DIVHS |
The HSMCLK source divider. More... | |
unsigned int | DIVS |
The SMCLK source divider. More... | |
unsigned int | SELB |
The BCLK source. More... | |
unsigned int | SELA |
The ACLK source. More... | |
unsigned int | DIVA |
The ACLK source divider. More... | |
unsigned int | flashWaitStates |
The number of Flash wait-states to be used for this performance level. More... | |
bool | enableFlashBuffer |
Boolean specifying if Flash read buffering should be enabled for this performance level. More... | |
unsigned int | MCLK |
The expected MCLK frequency for this performance level, in Hz. More... | |
unsigned int | HSMCLK |
The expected HSMCLK frequency for this performance level, in Hz. More... | |
unsigned int | SMCLK |
The expected SMCLK frequency for this performance level, in Hz. More... | |
unsigned int | BCLK |
The BCLK frequency for this performance level. Currently only 32768 Hz is supported. More... | |
unsigned int | ACLK |
The ACLK frequency for this performance level. Currently only 32768 Hz is supported. More... | |
Structure defining a performance level.
The MCU performance level can be set with Power_setPerformanceLevel(). A performance level is defined by this PowerMSP432_PerfLevel structure.
The Power driver currently supports four pre-defined performance levels:
Up to four optional 'custom' performance levels can be defined by the user. Performance levels are designated by an index, starting with zero. Any custom performance levels will be indexed following the last pre-defined level. For example, if there are 4 pre-defined levels, they will have indices from '0' to '3'. If there are custom levels defined, they will be indexed starting with '4'.
Eight performance level constraints are supported, one for each of the four pre-defined levels:
plus four for the optional custom performance levels:
The parameters that are used to define a performance level are shown below.
To define custom performance levels the user must add an array of PowerMSP432_PerfLevel structures to their board file, and then reference this array in the PowerMSP432_config structure. An example is shown below.
First, if not already included in the board file, add the includes of cs.h and pcm.h
Next, add an array with two new performance levels:
Then, update the PowerMSP432_config structure to 1) reference the new custom levels, and 2) as appropriate, enable extended performance scaling support, and define the relevant extended configuration parameters. In the first custom perf level shown above the HFXT and LFXT crystals are used as clock sources, so for this example the extended support parameters need to be specfied.
The code below shows additions to the PowerMSP432_config structure for this example. The first two additions to PowerMSP432_config reference the array of custom perf levels, and indicate the number of custom levels. The third addition enables extended support for crystals. The remaining parameters define crystal settings, plus an application-provided ISR function for handling any Clock System fault interrupts.
unsigned int PowerMSP432_PerfLevel::activeState |
The active state for the device.
The states are identified by the enumerations in pcm.h. The supported active states are: PCM_AM_LDO_VCORE0, PM_AM_LDO_VCORE1, PCM_AM_DCDC_VCORE0, PCM_AM_DCDC_VCORE1. Usage of DCDC states requires that the DCDC is available for the device and board configuration.
unsigned int PowerMSP432_PerfLevel::VCORE |
The core voltage level.
The supported levels are '0' indicating VCORE0, and '1' indicating VCORE1.
unsigned int PowerMSP432_PerfLevel::clockSource |
The clock source for this performance level.
This configuration parameter is not currently used.
unsigned int PowerMSP432_PerfLevel::DCORESEL |
The DCO frequency range selection.
The nominal DCO frequency is specified via an enumerated value defined in cs.h, for example: CS_DCO_FREQUENCY_12, CS_DCO_FREQUENCY_24, etc.
unsigned int PowerMSP432_PerfLevel::SELM |
The MCLK source.
The source is specified via an enumerated value from cs.h, for example: CS_DCOCLK_SELECT, CS_HFXTCLK_SELECT, etc.
unsigned int PowerMSP432_PerfLevel::DIVM |
The MCLK source divider.
The divide value is specified via an enumerated value from cs.h, for example: CS_CLOCKDIVIDER_1, CS_CLOCKDIVIDER_2, etc.
unsigned int PowerMSP432_PerfLevel::SELS |
The HSMCLK and SMCLK source.
The source is specified via an enumerated value from cs.h, for example: CS_DCOCLK_SELECT, CS_HFXTCLK_SELECT, etc.
unsigned int PowerMSP432_PerfLevel::DIVHS |
The HSMCLK source divider.
The divide value is specified via an enumerated value from cs.h, for example: CS_CLOCKDIVIDER_1, CS_CLOCKDIVIDER_2, etc.
unsigned int PowerMSP432_PerfLevel::DIVS |
The SMCLK source divider.
The divide value is specified via an enumerated value from cs.h, for example: CS_CLOCKDIVIDER_1, CS_CLOCKDIVIDER_2, etc.
unsigned int PowerMSP432_PerfLevel::SELB |
The BCLK source.
The source is specified via an enumerated value from cs.h, for example: CS_REFOCLK_SELECT, CS_DCOCLK_SELECT, etc.
unsigned int PowerMSP432_PerfLevel::SELA |
The ACLK source.
The source is specified via an enumerated value from cs.h, for example: CS_REFOCLK_SELECT, CS_DCOCLK_SELECT, etc.
unsigned int PowerMSP432_PerfLevel::DIVA |
The ACLK source divider.
The divide value is specified via an enumerated value from cs.h, for example: CS_CLOCKDIVIDER_1, CS_CLOCKDIVIDER_2, etc.
unsigned int PowerMSP432_PerfLevel::flashWaitStates |
The number of Flash wait-states to be used for this performance level.
The number of wait-states is specified as a positive integer value.
bool PowerMSP432_PerfLevel::enableFlashBuffer |
Boolean specifying if Flash read buffering should be enabled for this performance level.
If 'true', buffering will be enabled; if 'false', buffering will be disabled.
unsigned int PowerMSP432_PerfLevel::MCLK |
The expected MCLK frequency for this performance level, in Hz.
Note that this is an informational value; it is the expected MCLK frequency given the DCO frequency and source dividers specified above.
unsigned int PowerMSP432_PerfLevel::HSMCLK |
The expected HSMCLK frequency for this performance level, in Hz.
Note that this is an informational value; it is the expected HSMCLK frequency given the DCO frequency and source dividers specified above.
unsigned int PowerMSP432_PerfLevel::SMCLK |
The expected SMCLK frequency for this performance level, in Hz.
Note that this is an informational value; it is the expected SMCLK frequency given the DCO frequency and source dividers specified above.
unsigned int PowerMSP432_PerfLevel::BCLK |
The BCLK frequency for this performance level. Currently only 32768 Hz is supported.
unsigned int PowerMSP432_PerfLevel::ACLK |
The ACLK frequency for this performance level. Currently only 32768 Hz is supported.