48 #ifndef ti_drivers_power_PowerMSP432__include 49 #define ti_drivers_power_PowerMSP432__include 53 #include <ti/devices/DeviceFamily.h> 59 #include <ti/devices/msp432p4xx/driverlib/pcm.h> 60 #include <ti/devices/msp432p4xx/driverlib/cs.h> 69 #define PowerMSP432_RESUMETIMESLEEP 32 72 #define PowerMSP432_TOTALTIMESLEEP 40 75 #define PowerMSP432_RESUMETIMEDEEPSLEEP_0 16 78 #define PowerMSP432_TOTALTIMEDEEPSLEEP_0 40 81 #define PowerMSP432_RESUMETIMEDEEPSLEEP_1 16 84 #define PowerMSP432_TOTALTIMEDEEPSLEEP_1 40 87 #define PowerMSP432_PERIPH_ADC14 0 90 #define PowerMSP432_PERIPH_DMA 1 93 #define PowerMSP432_PERIPH_EUSCI_A0 2 96 #define PowerMSP432_PERIPH_EUSCI_A1 3 99 #define PowerMSP432_PERIPH_EUSCI_A2 4 102 #define PowerMSP432_PERIPH_EUSCI_A3 5 105 #define PowerMSP432_PERIPH_EUSCI_B0 6 108 #define PowerMSP432_PERIPH_EUSCI_B1 7 111 #define PowerMSP432_PERIPH_EUSCI_B2 8 114 #define PowerMSP432_PERIPH_EUSCI_B3 9 117 #define PowerMSP432_PERIPH_TIMER_A0 10 120 #define PowerMSP432_PERIPH_TIMER_A1 11 123 #define PowerMSP432_PERIPH_TIMER_A2 12 126 #define PowerMSP432_PERIPH_TIMER_A3 13 129 #define PowerMSP432_PERIPH_TIMER_T32 14 134 #define PowerMSP432_DISALLOW_SLEEP 0 137 #define PowerMSP432_DISALLOW_DEEPSLEEP_0 1 140 #define PowerMSP432_DISALLOW_DEEPSLEEP_1 2 143 #define PowerMSP432_DISALLOW_SHUTDOWN_0 3 146 #define PowerMSP432_DISALLOW_SHUTDOWN_1 4 149 #define PowerMSP432_DISALLOW_PERFLEVEL_0 5 152 #define PowerMSP432_DISALLOW_PERFLEVEL_1 6 155 #define PowerMSP432_DISALLOW_PERFLEVEL_2 7 158 #define PowerMSP432_DISALLOW_PERFLEVEL_3 8 161 #define PowerMSP432_DISALLOW_PERFLEVEL_4 9 164 #define PowerMSP432_DISALLOW_PERFLEVEL_5 10 167 #define PowerMSP432_DISALLOW_PERFLEVEL_6 11 170 #define PowerMSP432_DISALLOW_PERFLEVEL_7 12 173 #define PowerMSP432_DISALLOW_PERF_CHANGES 13 177 #define PowerMSP432_NUMCONSTRAINTS 14 185 #define PowerMSP432_ENTERING_SLEEP 0x1 188 #define PowerMSP432_ENTERING_DEEPSLEEP 0x2 191 #define PowerMSP432_ENTERING_SHUTDOWN 0x4 194 #define PowerMSP432_AWAKE_SLEEP 0x8 197 #define PowerMSP432_AWAKE_DEEPSLEEP 0x10 200 #define PowerMSP432_START_CHANGE_PERF_LEVEL 0x20 203 #define PowerMSP432_DONE_CHANGE_PERF_LEVEL 0x40 207 #define PowerMSP432_NUMEVENTS 7 211 #define PowerMSP432_SLEEP 0x1 212 #define PowerMSP432_DEEPSLEEP_0 0x2 213 #define PowerMSP432_DEEPSLEEP_1 0x4 216 #define PowerMSP432_SHUTDOWN_0 0x0 217 #define PowerMSP432_SHUTDOWN_1 0x1 356 typedef struct PowerMSP432_PerfLevel { 648 void (*resumeShutdownHookFxn)(void);
757 typedef struct PowerMSP432_ModuleState {
759 uint32_t constraintMask;
761 unsigned int currentPerfLevel;
763 bool perfInitialized;
765 uint8_t constraintCounts[PowerMSP432_NUMCONSTRAINTS];
767 } PowerMSP432_ModuleState;
829 void PowerMSP432_schedulerDisable(
void);
836 void PowerMSP432_schedulerRestore(
void);
839 uint_fast16_t PowerMSP432_getNumPerfLevels(
void);
842 int_fast16_t PowerMSP432_getFreqs(uint_fast16_t level,
851 #define Power_getDependencyCount(resourceId) Power_EINVALIDINPUT 852 #define Power_releaseDependency(resourceId) Power_EINVALIDINPUT 853 #define Power_setDependency(resourceId) Power_EINVALIDINPUT unsigned int SMCLK
The expected SMCLK frequency for this performance level, in Hz.
Definition: PowerMSP432.h:477
bool enablePerf
Boolean specifying if performance scaling is enabled.
Definition: PowerMSP432.h:566
uint32_t numCustom
Number of custom performance levels.
Definition: PowerMSP432.h:658
unsigned int clockSource
The clock source for this performance level.
Definition: PowerMSP432.h:378
Structure holding device frequencies (in Hz)
Definition: PowerMSP432.h:491
void PowerMSP432_sleepPolicy(void)
The SLEEP Power Policy.
unsigned int SELB
The BCLK source.
Definition: PowerMSP432.h:427
unsigned int LFXTDRIVE
The low frequency crystal (LFXT) drive level.
Definition: PowerMSP432.h:689
unsigned int MCLK
Definition: PowerMSP432.h:492
struct PowerMSP432_ConfigV1 PowerMSP432_ConfigV1
Power global configuration (MSP432-specific)
unsigned int DIVA
The ACLK source divider.
Definition: PowerMSP432.h:441
unsigned int HSMCLK
Definition: PowerMSP432.h:493
bool bypassLFXT
Boolean specifying if the LFXT pin should be configured for LFXT bypass.
Definition: PowerMSP432.h:725
void(* Power_PolicyInitFxn)(void)
Power policy initialization function pointer.
Definition: Power.h:100
unsigned int flashWaitStates
The number of Flash wait-states to be used for this performance level.
Definition: PowerMSP432.h:448
bool configurePinHFXT
Boolean specifying if the HFXT pin should be configured for HFXT function.
Definition: PowerMSP432.h:698
unsigned int HSMCLK
The expected HSMCLK frequency for this performance level, in Hz.
Definition: PowerMSP432.h:470
PowerMSP432_PerfLevel * customPerfLevels
Pointer to an optional array of custom performance levels.
Definition: PowerMSP432.h:654
struct PowerMSP432_Freqs PowerMSP432_Freqs
Structure holding device frequencies (in Hz)
bool enableInterruptsCS
Boolean specifying if interrupts from the Clock System (CS) should be enabled for catching clock and ...
Definition: PowerMSP432.h:741
unsigned int SELM
The MCLK source.
Definition: PowerMSP432.h:392
unsigned int DIVS
The SMCLK source divider.
Definition: PowerMSP432.h:420
void PowerMSP432_initPolicy(void)
The Power Policy initialization function.
unsigned int DCORESEL
The DCO frequency range selection.
Definition: PowerMSP432.h:385
void(* Power_PolicyFxn)(void)
Power policy function pointer.
Definition: Power.h:105
bool useExtendedPerf
Boolean specifying if extended performance scaling features are to be supported.
Definition: PowerMSP432.h:675
Power global configuration (MSP432-specific)
Definition: PowerMSP432.h:500
unsigned int VCORE
The core voltage level.
Definition: PowerMSP432.h:372
bool enableParking
Boolean specifying if pull resistors should be automatically applied to input pins during PowerMSP432...
Definition: PowerMSP432.h:637
unsigned int BCLK
The BCLK frequency for this performance level. Currently only 32768 Hz is supported.
Definition: PowerMSP432.h:482
unsigned int activeState
The active state for the device.
Definition: PowerMSP432.h:365
bool enablePolicy
Boolean specifying if the Power Policy function is enabled.
Definition: PowerMSP432.h:555
unsigned int BCLK
Definition: PowerMSP432.h:495
unsigned int DIVM
The MCLK source divider.
Definition: PowerMSP432.h:399
void PowerMSP432_deepSleepPolicy(void)
The DEEPSLEEP Power Policy.
unsigned int ACLK
The ACLK frequency for this performance level. Currently only 32768 Hz is supported.
Definition: PowerMSP432.h:487
unsigned int DIVHS
The HSMCLK source divider.
Definition: PowerMSP432.h:413
Power_PolicyFxn policyFxn
The Power Policy function.
Definition: PowerMSP432.h:530
unsigned int SELA
The ACLK source.
Definition: PowerMSP432.h:434
unsigned int priorityInterruptsCS
The interrupt priority to be configured for CS interrupts.
Definition: PowerMSP432.h:745
unsigned int SELS
The HSMCLK and SMCLK source.
Definition: PowerMSP432.h:406
unsigned int ACLK
Definition: PowerMSP432.h:496
bool enableFlashBuffer
Boolean specifying if Flash read buffering should be enabled for this performance level...
Definition: PowerMSP432.h:456
unsigned int HFXTFREQ
The high frequency crystal (HFXT) frequency.
Definition: PowerMSP432.h:682
bool configurePinLFXT
Boolean specifying if the LFXT pin should be configured for LFXT function.
Definition: PowerMSP432.h:716
bool bypassHFXT
Boolean specifying if the HFXT pin should be configured for HFXT bypass.
Definition: PowerMSP432.h:707
Power_PolicyInitFxn policyInitFxn
The Power Policy's initialization function.
Definition: PowerMSP432.h:507
struct PowerMSP432_PerfLevel PowerMSP432_PerfLevel
Structure defining a performance level.
unsigned int MCLK
The expected MCLK frequency for this performance level, in Hz.
Definition: PowerMSP432.h:463
Structure defining a performance level.
Definition: PowerMSP432.h:356
unsigned int SMCLK
Definition: PowerMSP432.h:494
unsigned int initialPerfLevel
The initial performance level to be established during Power Manager initialization.
Definition: PowerMSP432.h:542
Linked List interface for use in drivers.