Structure defining a performance level. More...

#include <PowerMSP432.h>

Data Fields
unsigned int	activeState
	The active state for the device. More...

unsigned int	VCORE
	The core voltage level. More...

unsigned int	clockSource
	The clock source for this performance level. More...

unsigned int	DCORESEL
	The DCO frequency range selection. More...

unsigned int	DIVM
	The MCLK source divider. More...

unsigned int	DIVHS
	The HSMCLK source divider. More...

unsigned int	DIVS
	The SMCLK source divider. More...

unsigned int	flashWaitStates
	The number of Flash wait-states to be used for this performance level. More...

bool	enableFlashBuffer
	Boolean specifying if Flash read buffering should be enabled for this performance level. More...

unsigned int	MCLK
	The expected MCLK frequency for this performance level, in Hz. More...

unsigned int	HSMCLK
	The expected HSMCLK frequency for this performance level, in Hz. More...

unsigned int	SMCLK
	The expected SMCLK frequency for this performance level, in Hz. More...

unsigned int	ACLK
	The ACLK frequency for this performance level. Currently only 32768 Hz is supported. More...

Detailed Description

Structure defining a performance level.

The MCU performance level can be set with Power_setPerformanceLevel(). A performance level is defined by this PowerMSP432_PerfLevel structure.

The Power driver currently supports four pre-defined performance levels:

Level    MCLK (MHz)    HSMCLK (MHz)    SMCLK (MHz)    ACLK (Hz)
-----    ----------    ------------    -----------    ---------
  0         12              3              3           32768
  1         24              6              6           32768
  2         48             24             12           32768
  3         48             48             24           32768

Up to four optional 'custom' performance levels can be defined by the user. Performance levels are designated by an index, starting with zero. Any custom performance levels will be indexed following the last pre-defined level. For example, if there are 4 pre-defined levels, they will have indices from '0' to '3'. If there are custom levels defined, they will be indexed starting with '4'.

Eight performance level constraints are supported, one for each of the four pre-defined levels:

PowerMSP432_DISALLOW_PERFLEVEL_0
PowerMSP432_DISALLOW_PERFLEVEL_1
PowerMSP432_DISALLOW_PERFLEVEL_2
PowerMSP432_DISALLOW_PERFLEVEL_3

plus four for the optional custom performance levels:

PowerMSP432_DISALLOW_PERFLEVEL_4
PowerMSP432_DISALLOW_PERFLEVEL_5
PowerMSP432_DISALLOW_PERFLEVEL_6
PowerMSP432_DISALLOW_PERFLEVEL_7

The parameters that are used to define a performance level are shown below. Note that there are limitations for some of the supported parameters. For example, currently the DCO is the only supported clock source.

Warning: There is very limited runtime error checking of the different parameters, and no checking that the ratios and parameter combinations do not result in an invalid device configuration (which could overclock or damage the device). It is therefore critical that the user ensures the values specified for a custom performance level are correct.

To define custom performance levels the user must add an array of PowerMSP432_PerfLevel structures to their board file, and then reference this array in the PowerMSP432_config structure. An example is shown below.

First, if not already included in the board file, add the includes of cs.h and pcm.h

#include <ti/devices/msp432p4xx/driverlib/cs.h>

#include <ti/devices/msp432p4xx/driverlib/pcm.h>

Next, add an array with two new performance levels:

PowerMSP432_PerfLevel myPerfLevels[] = {
  {
    .activeState = PCM_AM_DCDC_VCORE0,
    .VCORE = 0,
    .clockSource = CS_DCOCLK_SELECT,
    .DCORESEL = CS_DCO_FREQUENCY_12,
    .DIVM = CS_CLOCK_DIVIDER_1,
    .DIVHS = CS_CLOCK_DIVIDER_4,
    .DIVS = CS_CLOCK_DIVIDER_4,
    .flashWaitStates = 0,
    .enableFlashBuffer = false,
    .MCLK = 12000000,
    .HSMCLK = 3000000,
    .SMCLK = 3000000,
    .ACLK = 32768
  },
  {
    .activeState = PCM_AM_DCDC_VCORE0,
    .VCORE = 0,
    .clockSource = CS_DCOCLK_SELECT,
    .DCORESEL = CS_DCO_FREQUENCY_24,
    .DIVM = CS_CLOCK_DIVIDER_1,
    .DIVHS = CS_CLOCK_DIVIDER_4,
    .DIVS = CS_CLOCK_DIVIDER_4,
    .flashWaitStates = 1,
    .enableFlashBuffer = true,
    .MCLK = 24000000,
    .HSMCLK = 6000000,
    .SMCLK = 6000000,
    .ACLK = 32768
  }
};

And then reference the new custom levels by adding the following to the end of the PowerMSP432_config structure:

const PowerMSP432_ConfigV1 PowerMSP432_config = {
    ...
    .customPerfLevels = myPerfLevels,
    .numCustom = sizeof(myPerfLevels) / sizeof(PowerMSP432_PerfLevel)
};

Field Documentation

§ activeState

unsigned int PowerMSP432_PerfLevel::activeState

The active state for the device.

The states are identified by the enumerations in pcm.h. The supported active states are: PCM_AM_LDO_VCORE0, PM_AM_LDO_VCORE1, PCM_AM_DCDC_VCORE0, PCM_AM_DCDC_VCORE1. Usage of DCDC states requires that the DCDC is available for the device and board configuration.

§ VCORE

unsigned int PowerMSP432_PerfLevel::VCORE

The core voltage level.

The supported levels are '0' indicating VCORE0, and '1' indicating VCORE1.

§ clockSource

unsigned int PowerMSP432_PerfLevel::clockSource

The clock source for this performance level.

The only supported clock source is the DCO; all clocks will be derived from this source. The DCO is specified using the 'CS_DCOCLK_SELECT' enumeration from cs.h.

§ DCORESEL

unsigned int PowerMSP432_PerfLevel::DCORESEL

The DCO frequency range selection.

The nominal DCO frequency is specified via an enumerated value defined in cs.h, for example: CS_DCO_FREQUENCY_12, CS_DCO_FREQUENCY_24, etc.

§ DIVM

unsigned int PowerMSP432_PerfLevel::DIVM

The MCLK source divider.

The divide value is specified via an enumerated value from cs.h, for example: CS_CLOCKDIVIDER_1, CS_CLOCKDIVIDER_2, etc.

§ DIVHS

unsigned int PowerMSP432_PerfLevel::DIVHS

The HSMCLK source divider.

The divide value is specified via an enumerated value from cs.h, for example: CS_CLOCKDIVIDER_1, CS_CLOCKDIVIDER_2, etc.

§ DIVS

unsigned int PowerMSP432_PerfLevel::DIVS

The SMCLK source divider.

The divide value is specified via an enumerated value from cs.h, for example: CS_CLOCKDIVIDER_1, CS_CLOCKDIVIDER_2, etc.

§ flashWaitStates

unsigned int PowerMSP432_PerfLevel::flashWaitStates

The number of Flash wait-states to be used for this performance level.

The number of wait-states is specified as a positive integer value.

§ enableFlashBuffer

bool PowerMSP432_PerfLevel::enableFlashBuffer

Boolean specifying if Flash read buffering should be enabled for this performance level.

If 'true', buffering will be enabled; if 'false', buffering will be disabled.

§ MCLK

unsigned int PowerMSP432_PerfLevel::MCLK

The expected MCLK frequency for this performance level, in Hz.

Note that this is an informational value; it is the expected MCLK frequency given the DCO frequency and source dividers specified above.

§ HSMCLK

unsigned int PowerMSP432_PerfLevel::HSMCLK

The expected HSMCLK frequency for this performance level, in Hz.

Note that this is an informational value; it is the expected HSMCLK frequency given the DCO frequency and source dividers specified above.

§ SMCLK

unsigned int PowerMSP432_PerfLevel::SMCLK

The expected SMCLK frequency for this performance level, in Hz.

Note that this is an informational value; it is the expected SMCLK frequency given the DCO frequency and source dividers specified above.

§ ACLK

unsigned int PowerMSP432_PerfLevel::ACLK

The ACLK frequency for this performance level. Currently only 32768 Hz is supported.

The documentation for this struct was generated from the following file:

PowerMSP432.h

Data Fields

Detailed Description

Field Documentation

§ activeState

§ VCORE

§ clockSource

§ DCORESEL

§ DIVM

§ DIVHS

§ DIVS

§ flashWaitStates

§ enableFlashBuffer

§ MCLK

§ HSMCLK

§ SMCLK

§ ACLK