PowerMSP432.h
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1 /*
2  * Copyright (c) 2015-2017, Texas Instruments Incorporated
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
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12  * * Redistributions in binary form must reproduce the above copyright
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14  * documentation and/or other materials provided with the distribution.
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18  * from this software without specific prior written permission.
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31  */
48 #ifndef ti_drivers_power_PowerMSP432__include
49 #define ti_drivers_power_PowerMSP432__include
50 
51 #include <stdint.h>
52 
53 #include <ti/devices/DeviceFamily.h>
54 
55 #include <ti/drivers/utils/List.h>
56 #include <ti/drivers/Power.h>
57 
58 /* driverlib header files */
59 #include <ti/devices/msp432p4xx/driverlib/pcm.h>
60 #include <ti/devices/msp432p4xx/driverlib/cs.h>
61 
62 #ifdef __cplusplus
63 extern "C" {
64 #endif
65 
66 /* latency times in microseconds (derived from device datasheet) */
67 
69 #define PowerMSP432_RESUMETIMESLEEP 32
70 
72 #define PowerMSP432_TOTALTIMESLEEP 40
73 
75 #define PowerMSP432_RESUMETIMEDEEPSLEEP_0 16
76 
78 #define PowerMSP432_TOTALTIMEDEEPSLEEP_0 40
79 
81 #define PowerMSP432_RESUMETIMEDEEPSLEEP_1 16
82 
84 #define PowerMSP432_TOTALTIMEDEEPSLEEP_1 40
85 
86 /* Power resources (for declaring dependencies) */
87 #define PowerMSP432_PERIPH_ADC14 0
88 
90 #define PowerMSP432_PERIPH_DMA 1
91 
93 #define PowerMSP432_PERIPH_EUSCI_A0 2
94 
96 #define PowerMSP432_PERIPH_EUSCI_A1 3
97 
99 #define PowerMSP432_PERIPH_EUSCI_A2 4
100 
102 #define PowerMSP432_PERIPH_EUSCI_A3 5
103 
105 #define PowerMSP432_PERIPH_EUSCI_B0 6
106 
108 #define PowerMSP432_PERIPH_EUSCI_B1 7
109 
111 #define PowerMSP432_PERIPH_EUSCI_B2 8
112 
114 #define PowerMSP432_PERIPH_EUSCI_B3 9
115 
117 #define PowerMSP432_PERIPH_TIMER_A0 10
118 
120 #define PowerMSP432_PERIPH_TIMER_A1 11
121 
123 #define PowerMSP432_PERIPH_TIMER_A2 12
124 
126 #define PowerMSP432_PERIPH_TIMER_A3 13
127 
129 #define PowerMSP432_PERIPH_TIMER_T32 14
130 
133 /* Power constraints */
134 #define PowerMSP432_DISALLOW_SLEEP 0
135 
137 #define PowerMSP432_DISALLOW_DEEPSLEEP_0 1
138 
140 #define PowerMSP432_DISALLOW_DEEPSLEEP_1 2
141 
143 #define PowerMSP432_DISALLOW_SHUTDOWN_0 3
144 
146 #define PowerMSP432_DISALLOW_SHUTDOWN_1 4
147 
149 #define PowerMSP432_DISALLOW_PERFLEVEL_0 5
150 
152 #define PowerMSP432_DISALLOW_PERFLEVEL_1 6
153 
155 #define PowerMSP432_DISALLOW_PERFLEVEL_2 7
156 
158 #define PowerMSP432_DISALLOW_PERFLEVEL_3 8
159 
161 #define PowerMSP432_DISALLOW_PERFLEVEL_4 9
162 
164 #define PowerMSP432_DISALLOW_PERFLEVEL_5 10
165 
167 #define PowerMSP432_DISALLOW_PERFLEVEL_6 11
168 
170 #define PowerMSP432_DISALLOW_PERFLEVEL_7 12
171 
173 #define PowerMSP432_DISALLOW_PERF_CHANGES 13
174 
176 /* \cond */
177 #define PowerMSP432_NUMCONSTRAINTS 14
178 /* \endcond */
179 
180 /*
181  * Power events
182  *
183  * Each event ID must be a power of two and sequential without any gaps
184  */
185 #define PowerMSP432_ENTERING_SLEEP 0x1
186 
188 #define PowerMSP432_ENTERING_DEEPSLEEP 0x2
189 
191 #define PowerMSP432_ENTERING_SHUTDOWN 0x4
192 
194 #define PowerMSP432_AWAKE_SLEEP 0x8
195 
197 #define PowerMSP432_AWAKE_DEEPSLEEP 0x10
198 
200 #define PowerMSP432_START_CHANGE_PERF_LEVEL 0x20
201 
203 #define PowerMSP432_DONE_CHANGE_PERF_LEVEL 0x40
204 
206 /* \cond */
207 #define PowerMSP432_NUMEVENTS 7
208 /* \endcond */
209 
210 /* Power sleep states */
211 #define PowerMSP432_SLEEP 0x1
212 #define PowerMSP432_DEEPSLEEP_0 0x2
213 #define PowerMSP432_DEEPSLEEP_1 0x4
215 /* Power shutdown states */
216 #define PowerMSP432_SHUTDOWN_0 0x0
217 #define PowerMSP432_SHUTDOWN_1 0x1
329 typedef struct PowerMSP432_PerfLevel {
330 
338  unsigned int activeState;
345  unsigned int VCORE;
353  unsigned int clockSource;
360  unsigned int DCORESEL;
367  unsigned int DIVM;
374  unsigned int DIVHS;
381  unsigned int DIVS;
388  unsigned int flashWaitStates;
403  unsigned int MCLK;
410  unsigned int HSMCLK;
417  unsigned int SMCLK;
422  unsigned int ACLK;
424 
426 typedef struct PowerMSP432_Freqs {
427  unsigned int MCLK;
428  unsigned int HSMCLK;
429  unsigned int SMCLK;
430  unsigned int ACLK;
432 
434 typedef struct PowerMSP432_ConfigV1 {
476  unsigned int initialPerfLevel;
572  bool enableParking; /* enables automatic pin parking during LPM3 and LPM4 */
583  void (*resumeShutdownHookFxn)(void);
593  uint32_t numCustom;
595 
600 typedef struct PowerMSP432_ModuleState {
601  List_List notifyList;
602  uint32_t constraintMask;
603  unsigned int state;
604  unsigned int currentPerfLevel;
605  bool enablePolicy;
606  bool perfInitialized;
607  bool initialized;
608  uint8_t constraintCounts[PowerMSP432_NUMCONSTRAINTS];
609  Power_PolicyFxn policyFxn;
610 } PowerMSP432_ModuleState;
619 void PowerMSP432_initPolicy(void);
620 
636 void PowerMSP432_sleepPolicy(void);
637 
657 void PowerMSP432_deepSleepPolicy(void);
658 
665 void PowerMSP432_updateFreqs(PowerMSP432_Freqs *freqs);
666 
672 void PowerMSP432_schedulerDisable(void);
673 
679 void PowerMSP432_schedulerRestore(void);
680 
681 /* function to get the number of performance levels */
682 uint_fast16_t PowerMSP432_getNumPerfLevels(void);
683 
684 /* function to get the frequencies for a specific performance level */
685 int_fast16_t PowerMSP432_getFreqs(uint_fast16_t level,
686  PowerMSP432_Freqs * freqs);
687 
688 /*
689  * On MSP432 peripheral clocks are managed automatically by the device; there
690  * is no need for software control. Use #defines for the dependency APIs to
691  * eliminate any footprint.
692  */
693 /* \cond */
694 #define Power_getDependencyCount(resourceId) Power_EINVALIDINPUT
695 #define Power_releaseDependency(resourceId) Power_EINVALIDINPUT
696 #define Power_setDependency(resourceId) Power_EINVALIDINPUT
697 /* \endcond */
698 
699 #ifdef __cplusplus
700 }
701 #endif
702 
703 #endif /* ti_drivers_PowerMSP432_PowerMSP432__include */
unsigned int SMCLK
The expected SMCLK frequency for this performance level, in Hz.
Definition: PowerMSP432.h:417
bool enablePerf
Boolean specifying if performance scaling is enabled.
Definition: PowerMSP432.h:500
uint32_t numCustom
Number of custom performance levels.
Definition: PowerMSP432.h:593
unsigned int clockSource
The clock source for this performance level.
Definition: PowerMSP432.h:353
Structure holding device frequencies (in Hz)
Definition: PowerMSP432.h:426
void PowerMSP432_sleepPolicy(void)
The SLEEP Power Policy.
Definition: List.h:131
unsigned int MCLK
Definition: PowerMSP432.h:427
struct PowerMSP432_ConfigV1 PowerMSP432_ConfigV1
Power global configuration (MSP432-specific)
unsigned int HSMCLK
Definition: PowerMSP432.h:428
void(* Power_PolicyInitFxn)(void)
Power policy initialization function pointer.
Definition: Power.h:94
Power manager interface.
unsigned int flashWaitStates
The number of Flash wait-states to be used for this performance level.
Definition: PowerMSP432.h:388
unsigned int HSMCLK
The expected HSMCLK frequency for this performance level, in Hz.
Definition: PowerMSP432.h:410
PowerMSP432_PerfLevel * customPerfLevels
Pointer to an optional array of custom performance levels.
Definition: PowerMSP432.h:589
struct PowerMSP432_Freqs PowerMSP432_Freqs
Structure holding device frequencies (in Hz)
unsigned int DIVS
The SMCLK source divider.
Definition: PowerMSP432.h:381
void PowerMSP432_initPolicy(void)
The Power Policy initialization function.
unsigned int DCORESEL
The DCO frequency range selection.
Definition: PowerMSP432.h:360
void(* Power_PolicyFxn)(void)
Power policy function pointer.
Definition: Power.h:99
Power global configuration (MSP432-specific)
Definition: PowerMSP432.h:434
unsigned int VCORE
The core voltage level.
Definition: PowerMSP432.h:345
bool enableParking
Boolean specifying if pull resistors should be automatically applied to input pins during PowerMSP432...
Definition: PowerMSP432.h:572
unsigned int activeState
The active state for the device.
Definition: PowerMSP432.h:338
bool enablePolicy
Boolean specifying if the Power Policy function is enabled.
Definition: PowerMSP432.h:489
unsigned int DIVM
The MCLK source divider.
Definition: PowerMSP432.h:367
void PowerMSP432_deepSleepPolicy(void)
The DEEPSLEEP Power Policy.
unsigned int ACLK
The ACLK frequency for this performance level. Currently only 32768 Hz is supported.
Definition: PowerMSP432.h:422
unsigned int DIVHS
The HSMCLK source divider.
Definition: PowerMSP432.h:374
Power_PolicyFxn policyFxn
The Power Policy function.
Definition: PowerMSP432.h:464
unsigned int ACLK
Definition: PowerMSP432.h:430
bool enableFlashBuffer
Boolean specifying if Flash read buffering should be enabled for this performance level...
Definition: PowerMSP432.h:396
Power_PolicyInitFxn policyInitFxn
The Power Policy&#39;s initialization function.
Definition: PowerMSP432.h:441
struct PowerMSP432_PerfLevel PowerMSP432_PerfLevel
Structure defining a performance level.
unsigned int MCLK
The expected MCLK frequency for this performance level, in Hz.
Definition: PowerMSP432.h:403
Structure defining a performance level.
Definition: PowerMSP432.h:329
unsigned int SMCLK
Definition: PowerMSP432.h:429
unsigned int initialPerfLevel
The initial performance level to be established during Power Manager initialization.
Definition: PowerMSP432.h:476
Linked List interface for use in drivers.
Copyright 2017, Texas Instruments Incorporated