Hardware Architecture¶
ARM Cortex M0 (Radio Core)¶
The Cortex M0 (CM0) core within the CC26x2 is responsible for both interfacing to the radio hardware, and translating complex instructions from the Cortex M3 (CM3) core into bits that are sent over the air using the radio. For the Bluetooth low energy protocol, the CM0 implements the PHY layer of the protocol stack. Often, the CM0 is able to operate autonomously, which frees up the CM3 for higher-level protocol and application-layer processing.
The CM3 communicates with the CM0 through a hardware interface called the RF doorbell, which is documented in section 23.2 of the CC26x2 Technical Reference Manual. The radio core firmware is not intended to be used or modified by the application developer.
ARM Cortex M4F (System Core)¶
The system core (CM4F) is designed to run the wireless protocol stack from the link layer up to the user application. The link layer interfaces to the radio core through a software module called the RF driver, which sits above the RF doorbell. The RF driver runs on the CM3 and acts as an interface to the radio on the CC26x2, and also manages the power domains of the radio hardware and core. Documentation for the RF driver can be found at the TI-RTOS Drivers Reference.
The CC26x2¶
ARM Cortex M0 (Radio Core)¶
The Cortex M0 (CM0) core within the CC26x2 is responsible for both interfacing to the radio hardware, and translating complex instructions from the Cortex M4F (CM4F) core into bits that are sent over the air using the radio. For Z-Stack, the CM0 implements the PHY layer of the protocol stack. Often, the CM0 is able to operate autonomously, which frees up the CM4F for higher-level protocol and application-layer processing.
The CM4F communicates with the CM0 through a hardware interface called the RF doorbell, which is documented in the CC26x2 Technical Reference Manual. The radio core firmware is not intended to be used or modified by the application developer.
ARM Cortex M4F (System Core)¶
The system core (CM4F) is designed to run the wireless protocol stack from the link layer up to the user application. The link layer interfaces to the radio core through a software module called the RF driver, which sits above the RF doorbell. The RF driver runs on the CM4F and acts as an interface to the radio on the CC26x2, and also manages the power domains of the radio hardware and core. Documentation for the RF driver can be found at the TI-RTOS Drivers Reference.
Flash, RAM, and Peripherals¶
The CC26x2 contains 352KB of in-system programmable flash memory, 80KB of SRAM, and a full range of peripherals. The flash is split into erasable pages of 8KB. The CC26x2 also contains 8KB of cache SRAM that can be utilized to extend RAM capacity or can function as a normal cache to increase application performance. Other peripherals include UART, I2C, I2S, AES, TRNG, temperature and battery monitors, 4x 32-bit timers, 2x SSI, and an itegrated and autonomous sensor controller. See Sensor Controller for more information on the sensor controller.
Figure 2. SimpleLink™ CC26x2 Block Diagram
Programming Internal Flash With the ROM Bootloader¶
The CC26x2 internal flash memory can be programmed using the bootloader located in device ROM. Both UART and SPI protocols are supported. See chapter 8 of the CC26x2 Technical Reference Manual for more details on the programming protocol and requirements.
Note
Because the ROM bootloader uses predefined DIO pins for internal flash programming, allocate these pins in the board layout. The CC26x2 Technical Reference Manual has more details on the pins allocated to the bootloader based on the chip package type.
Startup Sequence¶
For a complete description of the CC26x2 reset sequence, see the CC26x2 Technical Reference Manual.
