[setup.h] Setup

Functions
void	SetupTrimDevice (void)
	Performs the necessary trim of the device which is not done in ROM boot code. More...

Detailed Description

This module contains functions for device setup which is not done in boot code.

Function Documentation

SetupTrimDevice()

void SetupTrimDevice

(

void

)

Performs the necessary trim of the device which is not done in ROM boot code.

This function should only execute coming from ROM boot.

The following is handled by this function:

• Checks if the driverlib variant used by the application is supported by the device. Execution is halted in case of unsupported driverlib variant.
• Configures VIMS cache mode based on setting in CCFG.
• Configures functionalities like DCDC and XOSC dependent on startup modes like cold reset, wakeup from shutdown and wakeup from from powerdown.
• Configures VIMS power domain control.
• Configures optimal wait time for flash FSM in cases where flash pump wakes up from sleep.

Note

The current implementation does not take soft reset into account. However, it does no damage to execute it again. It only consumes time.

This function is called by the compiler specific device startup codes that are integrated in the SimpleLink SDKs for CC13xx/CC26XX devices.

Returns

None

{
    uint32_t ui32Fcfg1Revision;
    uint32_t ui32AonSysResetctl;

    // Get layout revision of the factory configuration area
    // (Handle undefined revision as revision = 0)
    ui32Fcfg1Revision = HWREG(FCFG1_BASE + FCFG1_O_FCFG1_REVISION);
    if ( ui32Fcfg1Revision == 0xFFFFFFFF ) {
        ui32Fcfg1Revision = 0;
    }

    // This driverlib version and setup file is for the CC13x4, CC26x4 chips.
    // Halt if violated
    ThisLibraryIsFor_CC13x4_CC26x4_HaltIfViolated();

    // Select correct CACHE mode and set correct CACHE configuration
#if ( CCFG_BASE == CCFG_BASE_DEFAULT )
    SetupSetCacheModeAccordingToCcfgSetting();
#else
    NOROM_SetupSetCacheModeAccordingToCcfgSetting();
#endif

    // 1. Check for powerdown
    // 2. Check for shutdown
    // 3. Assume cold reset if none of the above.
    //
    // It is always assumed that the application will freeze the latches in
    // AON_IOC when going to powerdown in order to retain the values on the IOs.
    //
    // NB. If this bit is not cleared before proceeding to powerdown, the IOs
    //     will all default to the reset configuration when restarting.
    if( ! ( HWREG( AON_IOC_BASE + AON_IOC_O_IOCLATCH ) & AON_IOC_IOCLATCH_EN ))
    {
        // NB. This should be calling a ROM implementation of required trim and
        // compensation
        // e.g. TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown()
        TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown();
    }
    // Check for shutdown
    //
    // When device is going to shutdown the hardware will automatically clear
    // the SLEEPDIS bit in the SLEEP register in the AON_PMCTL module.
    // It is left for the application to assert this bit when waking back up,
    // but not before the desired IO configuration has been re-established.
    else if( ! ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_SLEEPCTL ) & AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS ))
    {
        // NB. This should be calling a ROM implementation of required trim and
        // compensation
        // e.g. TrimAfterColdResetWakeupFromShutDown()    -->
        //      TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown();
        TrimAfterColdResetWakeupFromShutDown(ui32Fcfg1Revision);
        TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown();
    }
    else
    {
        // Consider adding a check for soft reset to allow debugging to skip
        // this section!!!
        //
        // NB. This should be calling a ROM implementation of required trim and
        // compensation
        // e.g. TrimAfterColdReset()   -->
        //      TrimAfterColdResetWakeupFromShutDown()    -->
        //      TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown()
        TrimAfterColdReset();
        TrimAfterColdResetWakeupFromShutDown(ui32Fcfg1Revision);
        TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown();

    }

    // Set VIMS power domain control.
    // PDCTL1VIMS = 0 ==> VIMS power domain is only powered when CPU power domain is powered
    HWREG( PRCM_BASE + PRCM_O_PDCTL1VIMS ) = 0;

    // And finally at the end of the flash boot process:
    // SET BOOT_DET bits in AON_PMCTL to 3 if already found to be 1
    // Note: The BOOT_DET_x_CLR/SET bits must be manually cleared
    if ((( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) &
        ( AON_PMCTL_RESETCTL_BOOT_DET_1_M | AON_PMCTL_RESETCTL_BOOT_DET_0_M )) >>
        AON_PMCTL_RESETCTL_BOOT_DET_0_S ) == 1 )
    {
        ui32AonSysResetctl = ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) &
        ~( AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_M | AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_M |
           AON_PMCTL_RESETCTL_BOOT_DET_1_SET_M | AON_PMCTL_RESETCTL_BOOT_DET_0_SET_M | AON_PMCTL_RESETCTL_MCU_WARM_RESET_M ));
        HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = ui32AonSysResetctl | AON_PMCTL_RESETCTL_BOOT_DET_1_SET_M;
        HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = ui32AonSysResetctl;
    }

    // Reset the RTC
    AONRTCReset();
    // Configure the combined event
    IntPendClear(INT_AON_RTC_COMB);
    AONRTCCombinedEventConfig(AON_RTC_CH0 | AON_RTC_CH1 | AON_RTC_CH2);
    // Start the RTC
    AONRTCEnable();

    // Make sure there are no ongoing VIMS mode change when leaving SetupTrimDevice()
    // (There should typically be no wait time here, but need to be sure)
    while ( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_CHANGING ) {
        // Do nothing - wait for an eventual ongoing mode change to complete.
    }

    // Configure the NONSECWRn registers to allow manipulation of
    // ADI_3_REFSYS_DCDCCTL5_IPEAK and ADI_3_REFSYS_DCDCCTL5_DITHER from the
    // non-secure side. This is required by the radio for proper operation.
    // The ADI_3_REFSYS_O_DCDCCTL5 register byte-offset is divided by two
    // since the the ADDR field is encoded as a half-word index

    // Dither disabled, IPEAK = 0
    HWREG( ADI3_BASE + ADI_O_NONSECWR0) = (( 0x00 << ADI_NONSECWR0_DATA_S) & ADI_NONSECWR0_DATA_M ) |
                                          ((( ( ADI_3_REFSYS_O_DCDCCTL5) ) << ADI_NONSECWR0_ADDR_S ) & ADI_NONSECWR0_ADDR_M) |
                                          (( 0x0F << ADI_NONSECWR0_WR_MASK_S) & ADI_NONSECWR0_WR_MASK_M);

    // Dither enabled, IPEAK = 0
    HWREG( ADI3_BASE + ADI_O_NONSECWR1) = (( 0x08 << ADI_NONSECWR1_DATA_S) & ADI_NONSECWR1_DATA_M ) |
                                          ((( ( ADI_3_REFSYS_O_DCDCCTL5) ) << ADI_NONSECWR1_ADDR_S ) & ADI_NONSECWR1_ADDR_M) |
                                          (( 0x0F << ADI_NONSECWR1_WR_MASK_S) & ADI_NONSECWR1_WR_MASK_M);

    // Dither disabled, IPEAK = 3
    HWREG( ADI3_BASE + ADI_O_NONSECWR2) = (( 0x03 << ADI_NONSECWR2_DATA_S) & ADI_NONSECWR2_DATA_M ) |
                                          ((( ( ADI_3_REFSYS_O_DCDCCTL5)  ) << ADI_NONSECWR2_ADDR_S ) & ADI_NONSECWR2_ADDR_M) |
                                          (( 0x0F << ADI_NONSECWR2_WR_MASK_S) & ADI_NONSECWR2_WR_MASK_M);

    // Dither disabled, IPEAK = 7
    HWREG( ADI3_BASE + ADI_O_NONSECWR3) = (( 0x07 << ADI_NONSECWR3_DATA_S) & ADI_NONSECWR3_DATA_M ) |
                                          ((( ( ADI_3_REFSYS_O_DCDCCTL5) ) << ADI_NONSECWR3_ADDR_S ) & ADI_NONSECWR3_ADDR_M) |
                                          (( 0x0F << ADI_NONSECWR3_WR_MASK_S) & ADI_NONSECWR3_WR_MASK_M);

    // Configure Sensor Controller access to TDC clock control
    // Allow read and write ACLK_TDC_SRC_SEL and ACLK_REF_SRC_SEL fields in
    // DDI_0_OSC_O_CTL0 register.
    // The ADDR field is encoded as a half-word index. So we need to divide the
    // regular byte-offset by two.
    // Use NONSECDDIACC3 because if ADDR is 0 for multiple NONSECDDIACCn,
    // only the highest NONSECDIACCn takes effect. 0 is the reset value for
    // ADDR and DDI_0_OSC_O_CTL0 has an ADDR offset of 0. So to access this
    // Register, we should always aim to use the highest NONSECDDIACCn.
    HWREG( AUX_SCE_BASE + AUX_SCE_O_NONSECDDIACC3) = AUX_SCE_NONSECDDIACC3_RD_EN |
                                                     (( ( DDI_0_OSC_O_CTL0 / 2 ) << AUX_SCE_NONSECDDIACC3_ADDR_S ) & AUX_SCE_NONSECDDIACC3_ADDR_M ) |
                                                     (( DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_M | DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M ) & AUX_SCE_NONSECDDIACC3_WR_MASK_M );

    // Configure Sensor Controller access to COMPB 32 kHz clock enable
    // We want to read and write DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN.
    // This is a 16-bit write, so we need to add to the address offset since
    // DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN is in the upper half of the register.
    // The ADDR field is encoded as a half-word index. So we need to divide the
    // regular byte-offset by two.
    // The mask needs to be shifted down because the original register field
    // mask is provided as a 32-bit mask.
    HWREG( AUX_SCE_BASE + AUX_SCE_O_NONSECDDIACC1) = AUX_SCE_NONSECDDIACC1_RD_EN |
                                                     ((( ( DDI_0_OSC_O_ATESTCTL + 2 ) / 2 ) << AUX_SCE_NONSECDDIACC1_ADDR_S ) & AUX_SCE_NONSECDDIACC1_ADDR_M) |
                                                     (( DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_M >> 16 ) & AUX_SCE_NONSECDDIACC1_WR_MASK_M);

    // Enable output of RTC clock for Radio Timer Synchronization
    HWREG(AON_RTC_BASE + AON_RTC_O_CTL) |= AON_RTC_CTL_RTC_UPD_EN_M;
}

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