CC26xx Driver Library
[vims.h] Versatile Instruction Memory System

Functions

void VIMSConfigure (uint32_t ui32Base, bool bRoundRobin, bool bPrefetch)
 Configures the VIMS. More...
 
void VIMSModeSet (uint32_t ui32Base, uint32_t ui32Mode)
 Set the operational mode of the VIMS. More...
 
uint32_t VIMSModeGet (uint32_t ui32Base)
 Get the current operational mode of the VIMS. More...
 
void VIMSModeSafeSet (uint32_t ui32Base, uint32_t ui32NewMode, bool blocking)
 Set the operational mode of the VIMS in a safe sequence. More...
 
static void VIMSLineBufDisable (uint32_t ui32Base)
 Disable VIMS linebuffers. More...
 
static void VIMSLineBufEnable (uint32_t ui32Base)
 Enable VIMS linebuffers. More...
 

Detailed Description

Function Documentation

void VIMSConfigure ( uint32_t  ui32Base,
bool  bRoundRobin,
bool  bPrefetch 
)

Configures the VIMS.

This function sets general control settings of the VIMS system.

Note
The VIMS mode must be set using the VIMSModeSet() call.
Parameters
ui32Baseis the base address of the VIMS.
bRoundRobinspecifies the arbitration method.
  • true : Round Robin arbitration between the two available read/write interfaces (i.e. Icode/Dcode and Sysbus) is to be used.
  • false : Strict arbitration will be used, where Icode/Dcode is preferred over the Sysbus.
bPrefetchspecifies if prefetching is to be used.
  • true : Cache is to prefetch tag data for the following address.
  • false : No prefetch.
Returns
None
See also
VIMSModeSet()
65 {
66  uint32_t ui32Reg;
67 
68  // Check the arguments.
69  ASSERT(VIMSBaseValid(ui32Base));
70 
71  ui32Reg = HWREG(ui32Base + VIMS_O_CTL);
72  ui32Reg &= ~(VIMS_CTL_PREF_EN | VIMS_CTL_ARB_CFG);
73  if(bRoundRobin)
74  {
75  ui32Reg |= VIMS_CTL_ARB_CFG;
76  }
77  if(bPrefetch)
78  {
79  ui32Reg |= VIMS_CTL_PREF_EN;
80  }
81 
82  // Set the Arbitration and prefetch mode.
83  HWREG(ui32Base + VIMS_O_CTL) = ui32Reg;
84 }
#define ASSERT(expr)
Definition: debug.h:73
static void VIMSLineBufDisable ( uint32_t  ui32Base)
inlinestatic

Disable VIMS linebuffers.

Linebuffers should only be disabled when attempting to update the flash, to ensure that the content of the buffers is not stale. As soon as flash is updated the linebuffers should be reenabled. Failing to enable will have a performance impact.

Parameters
ui32Baseis the base address of the VIMS.
Returns
None.
300 {
301  // Disable line buffers
302  HWREG(ui32Base + VIMS_O_CTL) |= VIMS_CTL_IDCODE_LB_DIS_M |
304 }
static void VIMSLineBufEnable ( uint32_t  ui32Base)
inlinestatic

Enable VIMS linebuffers.

Linebuffers should only be disabled when attempting to update the flash, to ensure that the content of the buffers is not stale. As soon as flash is updated the linebuffers should be reenabled. Failing to enable will have a performance impact.

Parameters
ui32Baseis the base address of the VIMS.
Returns
None.
322 {
323  // Enable linebuffers
324  HWREG(ui32Base + VIMS_O_CTL) &= ~(VIMS_CTL_IDCODE_LB_DIS_M |
326 }
uint32_t VIMSModeGet ( uint32_t  ui32Base)

Get the current operational mode of the VIMS.

This function returns the operational mode of the VIMS.

Parameters
ui32Baseis the base address of the VIMS.
Returns
Returns one of:
See also
VIMSModeSet()

Referenced by SysCtrlStandby(), and VIMSModeSafeSet().

118 {
119  uint32_t ui32Reg;
120 
121  // Check the arguments.
122  ASSERT(VIMSBaseValid(ui32Base));
123 
124  ui32Reg = HWREG(ui32Base + VIMS_O_STAT);
125  if(ui32Reg & VIMS_STAT_MODE_CHANGING)
126  {
127  return (VIMS_MODE_CHANGING);
128  }
129  else
130  {
131  return (ui32Reg & VIMS_STAT_MODE_M);
132  }
133 }
#define ASSERT(expr)
Definition: debug.h:73
#define VIMS_MODE_CHANGING
Definition: vims.h:95
void VIMSModeSafeSet ( uint32_t  ui32Base,
uint32_t  ui32NewMode,
bool  blocking 
)

Set the operational mode of the VIMS in a safe sequence.

This function sets the operational mode of the VIMS in a safe sequence

Upon reset the VIMS will be in VIMS_MODE_CHANGING mode. In this mode the VIMS will initialize the cache (GP) RAM (to all zeros). The GP RAM will not be operational (read/write will result in bus fault). The Cache will not be operational (read/write to flash will be uncached). After a short delay (approx. 1029 clock cycles) the VIMS will automatically switch mode to VIMS_MODE_DISABLED (GPRAM enabled).

In VIMS_MODE_DISABLED mode, the cache is disabled but the GP RAM is accessible: The GP RAM will be accessible. The Cache will not be operational. Reads from flash will be uncached. From this mode, the VIMS may be put in VIMS_MODE_ENABLED (CACHE mode).

In VIMS_MODE_ENABLED mode, the cache is enabled for USERCODE space. The GP RAM will not be operational (read/write will result in bus fault). The Cache will be operational for SYSCODE space. Reads from flash in USERCODE space will be uncached.

In VIMS_MODE_OFF the cache RAM is off to conserve power.

Note
The VIMS must be invalidated when switching mode. This is done by setting VIMS_MODE_OFF before setting any new mode. This is automatically handled in this function.
It is highly recommended that the VIMS is put in disabled mode before writing to flash, since the cache will not be updated nor invalidated by flash writes. The line buffers should also be disabled when updating the flash.
Access from System Bus is never cached. Only access through ICODE DCODE bus from the System CPU is cached.
Parameters
ui32Baseis the base address of the VIMS.
ui32NewModeis the new operational mode:
blockingshall be set to TRUE if further code execution shall be blocked (delayed) until mode change is completed.
Returns
None
See also
VIMSModeSet() and VIMSModeGet()
144 {
145  uint32_t currentMode;
146 
147  // Check the arguments.
148  ASSERT(VIMSBaseValid(ui32Base));
149  ASSERT((ui32NewMode == VIMS_MODE_DISABLED) ||
150  (ui32NewMode == VIMS_MODE_ENABLED) ||
151  (ui32NewMode == VIMS_MODE_OFF));
152 
153  // Make sure that only the mode bits are set in the input parameter
154  // (done just for security since it is critical to the code flow)
155  ui32NewMode &= VIMS_CTL_MODE_M;
156 
157  // Wait for any pending change to complete and get current VIMS mode
158  // (This is a blocking point but will typically only be a blocking point
159  // only if mode is changed multiple times with blocking=0)
160  do {
161  currentMode = VIMSModeGet( ui32Base );
162  } while ( currentMode == VIMS_MODE_CHANGING );
163 
164  // First check that it actually is a mode change request
165  if ( ui32NewMode != currentMode ) {
166  // Set new mode
167  VIMSModeSet( ui32Base, ui32NewMode );
168 
169  // Wait for final mode change to complete - if blocking is requested
170  if ( blocking ) {
171  while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) {
172  // Do nothing - wait for change to complete.
173  }
174  }
175  }
176 }
void VIMSModeSet(uint32_t ui32Base, uint32_t ui32Mode)
Set the operational mode of the VIMS.
Definition: vims.c:92
#define VIMS_MODE_ENABLED
Definition: vims.h:98
uint32_t VIMSModeGet(uint32_t ui32Base)
Get the current operational mode of the VIMS.
Definition: vims.c:117
#define ASSERT(expr)
Definition: debug.h:73
#define VIMS_MODE_DISABLED
Definition: vims.h:97
#define VIMS_MODE_CHANGING
Definition: vims.h:95
#define VIMS_MODE_OFF
Definition: vims.h:99

Here is the call graph for this function:

void VIMSModeSet ( uint32_t  ui32Base,
uint32_t  ui32Mode 
)

Set the operational mode of the VIMS.

This function sets the operational mode of the VIMS.

Upon reset the VIMS will be in VIMS_MODE_CHANGING mode. In this mode the VIMS will initialize the cache (GP) RAM (to all zeros). The GP RAM will not be operational (read/write will result in bus fault). The Cache will not be operational. Reads and writes to flash will be uncached. After a short delay (approx. 1029 clock cycles) the VIMS will automatically switch mode to VIMS_MODE_DISABLED (GPRAM enabled).

In VIMS_MODE_DISABLED mode, the cache is disabled but the GP RAM is accessible: The GP RAM will be accessible. The Cache will not be operational. Reads from flash will be uncached. From this mode, the VIMS may be put in VIMS_MODE_ENABLED (CACHE mode).

In VIMS_MODE_ENABLED mode, the cache is enabled for USERCODE space. The GP RAM will not be operational (read/write will result in bus fault). The Cache will be operational for SYSCODE space. Reads from flash in USERCODE space will be uncached.

In VIMS_MODE_OFF the cache RAM is off to conserve power.

Note
The VIMS must be invalidated when switching mode. This is done by setting VIMS_MODE_OFF before setting any new mode. This is automatically handled in VIMSModeSafeSet()
It is highly recommended that the VIMS is put in disabled mode before writing to flash, since the cache will not be updated nor invalidated by flash writes. The line buffers should also be disabled when updating the flash. Once VIMSModeSet() is used to set the VIMS in VIMS_MODE_CHANGING mode, the user should check using VIMSModeGet() when the mode switches to VIMS_MODE_DISABLED. Only when the mode has changed the cache has been completely invalidated.
Access from System Bus is never cached. Only access through ICODE DCODE bus from the System CPU is cached.
Parameters
ui32Baseis the base address of the VIMS.
ui32Modeis the operational mode.
Returns
None
See also
VIMSModeGet() and VIMSModeSafeSet()

Referenced by SysCtrlStandby(), and VIMSModeSafeSet().

93 {
94  uint32_t ui32Reg;
95 
96  // Check the arguments.
97  ASSERT(VIMSBaseValid(ui32Base));
98 
99  ASSERT((ui32Mode == VIMS_MODE_DISABLED) ||
100  (ui32Mode == VIMS_MODE_ENABLED) ||
101  (ui32Mode == VIMS_MODE_OFF));
102 
103  // Set the mode.
104  ui32Reg = HWREG(ui32Base + VIMS_O_CTL);
105  ui32Reg &= ~VIMS_CTL_MODE_M;
106  ui32Reg |= (ui32Mode & VIMS_CTL_MODE_M);
107 
108  HWREG(ui32Base + VIMS_O_CTL) = ui32Reg;
109 }
#define VIMS_MODE_ENABLED
Definition: vims.h:98
#define ASSERT(expr)
Definition: debug.h:73
#define VIMS_MODE_DISABLED
Definition: vims.h:97
#define VIMS_MODE_OFF
Definition: vims.h:99

Macro Definition Documentation

#define VIMS_MODE_CHANGING   0x4
#define VIMS_MODE_DISABLED   (VIMS_CTL_MODE_GPRAM)

Referenced by VIMSModeSafeSet(), and VIMSModeSet().

#define VIMS_MODE_ENABLED   (VIMS_CTL_MODE_CACHE)
#define VIMS_MODE_OFF   (VIMS_CTL_MODE_OFF)