soc_rcm.h File Reference

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Macros
#define	SOC_RCM_FREQ_HZ2MHZ(hz)   ((hz)/(1000000U))
#define	SOC_RCM_FREQ_MHZ2HZ(mhz)   ((mhz)*(1000000U))
#define	SOC_RCM_MEMINIT_APPSS_RAM1A_INIT   (1U << 0U)
#define	SOC_RCM_MEMINIT_APPSS_RAM2A_INIT   (1U << 1U)
#define	SOC_RCM_MEMINIT_APPSS_RAM3A_INIT   (1U << 2U)
#define	SOC_RCM_MEMINIT_APPSS_ALL_INIT

Enumerations
enum	SOC_rcmM4ClockSrc { SOC_rcmM4ClockSrc_OSC_CLK = 0x000, SOC_rcmM4ClockSrc_SLOW_CLK = 0x111, SOC_rcmM4ClockSrc_MDLL_CLK = 0x222, SOC_rcmM4ClockSrc_FAST_CLK = 0x333 }
enum	SOC_RcmResetCause {   SOC_RcmResetCause_POWER_CAUSE_CLEAR = 0x0U, SOC_RcmResetCause_POWER_ON_RESET = 0x1U, SOC_RcmResetCause_WARM_RESET = 0x2U, SOC_RcmResetCause_STC_RESET = 0x4U,   SOC_RcmResetCause_CPU_ONLY_RESET = 0x10U, SOC_RcmResetCause_CORE_RESET = 0x20U, SOC_RcmResetCause_MAX_VALUE = 0xFFFFFFFFu }
	Reset Causes. More...
enum	SOC_RcmPeripheralId {   SOC_RcmPeripheralId_APPSS_MCAN, SOC_RcmPeripheralId_APPSS_LIN, SOC_RcmPeripheralId_APPSS_QSPI, SOC_RcmPeripheralId_APPSS_RTI,   SOC_RcmPeripheralId_APPSS_WDT, SOC_RcmPeripheralId_APPSS_MCSPIA, SOC_RcmPeripheralId_APPSS_MCSPIB, SOC_RcmPeripheralId_APPSS_I2C,   SOC_RcmPeripheralId_APPSS_UART0, SOC_RcmPeripheralId_APPSS_UART1, SOC_RcmPeripheralId_APPSS_ESM, SOC_RcmPeripheralId_APPSS_EDMA,   SOC_RcmPeripheralId_APPSS_CRC, SOC_RcmPeripheralId_APPSS_PWM, SOC_RcmPeripheralId_APPSS_GIO, SOC_RcmPeripheralId_HWASS,   SOC_RcmPeripheralId_MAX_VALUE = 0xFFFFFFFFu }
	Peripheral IDs. More...
enum	SOC_RcmPeripheralClockSource {   SOC_RcmPeripheralClockSource_OSC_CLK, SOC_RcmPeripheralClockSource_SLOW_CLK, SOC_RcmPeripheralClockSource_MDLL_CLK, SOC_RcmPeripheralClockSource_FAST_CLK,   SOC_RcmPeripheralClockSource_XREF_IN_CLK, SOC_RcmPeripheralClockSource_OSC_CLKX2, SOC_RcmPeripheralClockSource_RC_CLK_10M, SOC_RcmPeripheralClockSource_RCCLK32K,   SOC_RcmPeripheralClockSource_MAX_VALUE = 0xFFFFFFFFu }
	Peripheral Clock Sources. More...
enum	SOC_RcmM4ClockSource {   SOC_RcmM4ClockSource_OSC_CLK, SOC_RcmM4ClockSource_SLOW_CLK, SOC_RcmM4ClockSource_MDLL_CLK, SOC_RcmM4ClockSource_FAST_CLK,   SOC_RcmM4ClockSource_MAX_VALUE = 0xFFFFFFFFu }
	M4 Clock Sources. More...
enum	SOC_RcmQspiClockFreqId { SOC_RcmQspiClockFreqId_CLK_40MHZ = 0x0, SOC_RcmQspiClockFreqId_CLK_60MHZ = 0x1, SOC_RcmQspiClockFreqId_CLK_80MHZ = 0x2, SOC_RcmQspiClockFreqId_MAX_VALUE = 0xFFFFFFFFu }
	QSPI frequency values. More...
enum	SOC_RcmPeripheralClockGate { SOC_RcmPeripheralClockGateEnable, SOC_RcmPeripheralClockGateDisable }
	Peripheral Clock Gate Status. More...

Functions
void	SOC_rcmEnableADPLLClock ()
	Enable ADPLL. More...
int32_t	SOC_rcmSetM4Clock (uint32_t m4FreqHz)
	Set M4 frequency. More...
int32_t	SOC_rcmSetM4ClockSrc (SOC_rcmM4ClockSrc m4Src)
	Set M4 Clock Source. More...
uint32_t	SOC_rcmGetM4Clock (void)
	Get M4 frequency. More...
int32_t	SOC_rcmSetPeripheralClock (SOC_RcmPeripheralId periphId, SOC_RcmPeripheralClockSource clkSource, uint32_t freqHz)
	Set peripheral frequency. More...
uint32_t	SOC_rcmGetPeripheralClock (SOC_RcmPeripheralId periphId)
	Get peripheral frequency. More...
SOC_RcmResetCause	SOC_rcmGetResetCause (void)
	Get SOC reset cause. More...
int32_t	SOC_rcmEnablePeripheralClock (SOC_RcmPeripheralId periphId, SOC_RcmPeripheralClockGate enable)
	Enable/Disable peripheral Clock gating. More...
void	SOC_rcmStartMemInitHwassShared (void)
	Start memory initialization for HWASS Shared Memory RAM0, RAM1. More...
void	SOC_rcmWaitMemInitHwassShared (void)
	Wait memory initialization to complete HWASS Shared Memory RAM0, RAM1. More...
void	SOC_rcmStartMemInitTpcc (void)
	Start memory initialization for TPCCA and TPCCB. More...
void	SOC_rcmWaitMemInitTpcc (void)
	Wait memory initialization to complete TPCCA and TPCCB. More...