soc_rcm.h

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/*
 *  Copyright (C) 2021 Texas Instruments Incorporated
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#ifndef SOC_RCM_XWRL64XX_H
#define SOC_RCM_XWRL64XX_H
 
#include <stdint.h>
 
#ifdef __cplusplus
extern "C"
{
#endif
 
#include <kernel/dpl/SystemP.h>
 
#define SOC_RCM_FREQ_HZ2MHZ(hz)     ((hz)/(1000000U))
#define SOC_RCM_FREQ_MHZ2HZ(mhz)    ((mhz)*(1000000U))
 
#define SOC_RCM_MEMINIT_APPSS_RAM1A_INIT      (1U << 0U)
#define SOC_RCM_MEMINIT_APPSS_RAM2A_INIT      (1U << 1U)
#define SOC_RCM_MEMINIT_APPSS_RAM3A_INIT      (1U << 2U)
#define SOC_RCM_MEMINIT_APPSS_ALL_INIT        (SOC_RCM_MEMINIT_APPSS_RAM1A_INIT | \
                                               SOC_RCM_MEMINIT_APPSS_RAM2A_INIT | \
                                               SOC_RCM_MEMINIT_APPSS_RAM3A_INIT)
 
typedef enum  SOC_rcmM4ClockSrc_e {SOC_rcmM4ClockSrc_OSC_CLK = 0x000,
                                   SOC_rcmM4ClockSrc_SLOW_CLK = 0x111,
                                   SOC_rcmM4ClockSrc_MDLL_CLK = 0x222,
                                   SOC_rcmM4ClockSrc_FAST_CLK = 0x333} SOC_rcmM4ClockSrc;
 
typedef enum SOC_RcmResetCause_e
{
    SOC_RcmResetCause_POWER_CAUSE_CLEAR = 0x0U,
    SOC_RcmResetCause_POWER_ON_RESET = 0x1U,
    SOC_RcmResetCause_WARM_RESET = 0x2U,
    SOC_RcmResetCause_STC_RESET = 0x4U,
    SOC_RcmResetCause_CPU_ONLY_RESET = 0x10U,
    SOC_RcmResetCause_CORE_RESET = 0x20U,
    SOC_RcmResetCause_MAX_VALUE = 0xFFFFFFFFu,
 
} SOC_RcmResetCause;
 
typedef enum SOC_RcmPeripheralId_e
{
    SOC_RcmPeripheralId_APPSS_MCAN,
    SOC_RcmPeripheralId_APPSS_LIN,
    SOC_RcmPeripheralId_APPSS_QSPI,
    SOC_RcmPeripheralId_APPSS_RTI,
    SOC_RcmPeripheralId_APPSS_WDT,
    SOC_RcmPeripheralId_APPSS_MCSPIA,
    SOC_RcmPeripheralId_APPSS_MCSPIB,
    SOC_RcmPeripheralId_APPSS_I2C,
    SOC_RcmPeripheralId_APPSS_UART0,
    SOC_RcmPeripheralId_APPSS_UART1,
    SOC_RcmPeripheralId_APPSS_ESM,
    SOC_RcmPeripheralId_APPSS_EDMA,
    SOC_RcmPeripheralId_APPSS_CRC,
    SOC_RcmPeripheralId_APPSS_PWM,
    SOC_RcmPeripheralId_APPSS_GIO,
    SOC_RcmPeripheralId_HWASS,
    SOC_RcmPeripheralId_MAX_VALUE = 0xFFFFFFFFu,
 
} SOC_RcmPeripheralId;
 
typedef enum SOC_RcmPeripheralClockSource_e
{
    SOC_RcmPeripheralClockSource_OSC_CLK,
    SOC_RcmPeripheralClockSource_SLOW_CLK,
    SOC_RcmPeripheralClockSource_MDLL_CLK,
    SOC_RcmPeripheralClockSource_FAST_CLK,
    SOC_RcmPeripheralClockSource_XREF_IN_CLK,
    SOC_RcmPeripheralClockSource_OSC_CLKX2,
    SOC_RcmPeripheralClockSource_RC_CLK_10M,
    SOC_RcmPeripheralClockSource_RCCLK32K,
    SOC_RcmPeripheralClockSource_MAX_VALUE = 0xFFFFFFFFu,
 
} SOC_RcmPeripheralClockSource;
 
typedef enum SOC_RcmM4ClockSource_e
{
    SOC_RcmM4ClockSource_OSC_CLK,
    SOC_RcmM4ClockSource_SLOW_CLK,
    SOC_RcmM4ClockSource_MDLL_CLK,
    SOC_RcmM4ClockSource_FAST_CLK,
    SOC_RcmM4ClockSource_MAX_VALUE = 0xFFFFFFFFu,
} SOC_RcmM4ClockSource;
 
typedef enum SOC_RcmQspiClockFreqId_e {
    SOC_RcmQspiClockFreqId_CLK_40MHZ = 0x0,
    SOC_RcmQspiClockFreqId_CLK_60MHZ = 0x1,
    SOC_RcmQspiClockFreqId_CLK_80MHZ = 0x2,
    SOC_RcmQspiClockFreqId_MAX_VALUE = 0xFFFFFFFFu,
 
} SOC_RcmQspiClockFreqId;
 
typedef enum SOC_RcmPeripheralClockGate_e {
    SOC_RcmPeripheralClockGateEnable,
    SOC_RcmPeripheralClockGateDisable
 
}SOC_RcmPeripheralClockGate;
 
void SOC_rcmEnableADPLLClock();
 
int32_t SOC_rcmSetM4Clock(uint32_t m4FreqHz);
 
int32_t SOC_rcmSetM4ClockSrc(SOC_rcmM4ClockSrc m4Src);
 
uint32_t SOC_rcmGetM4Clock(void);
 
int32_t SOC_rcmSetPeripheralClock(SOC_RcmPeripheralId periphId, SOC_RcmPeripheralClockSource clkSource, uint32_t freqHz);
 
uint32_t SOC_rcmGetPeripheralClock(SOC_RcmPeripheralId periphId);
 
SOC_RcmResetCause SOC_rcmGetResetCause(void);
 
int32_t SOC_rcmEnablePeripheralClock(SOC_RcmPeripheralId periphId, SOC_RcmPeripheralClockGate enable);
 
void SOC_rcmStartMemInitHwassShared(void);
 
void SOC_rcmWaitMemInitHwassShared(void);
 
void SOC_rcmStartMemInitTpcc(void);
 
void SOC_rcmWaitMemInitTpcc(void);
 
#ifdef __cplusplus
}
#endif
 
#endif