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xWRL6432 MMWAVE-L-SDK
05.01.00.04
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xWRL6432 MMWAVE-L-SDK
05.01.00.04
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Go to the source code of this file.
| #define CSL_CORE_ID_M4FSS0_0 (0U) |
| #define CSL_CORE_ID_MAX (1U) |
| #define CSL_APSS_UART_PER_CNT (1U) |
Number of UART instances.
| #define CSL_APPSS_MIBSPI_PER_CNT (2U) |
Number of MIBSPI instances.
| #define CSL_APPSS_I2C_CNT (1U) |
Number of I2C instances.
| #define SOC_EDMA_NUM_DMACH (64U) |
Number of Memory Addresses.
Number of DMA Channels
| #define SOC_EDMA_NUM_QDMACH (8U) |
Number of QDMA Channels.
| #define SOC_EDMA_NUM_PARAMSETS (128U) |
Number of PaRAM Sets available.
| #define SOC_EDMA_NUM_EVQUE (2U) |
Number of Event Queues available.
| #define SOC_EDMA_CHMAPEXIST (1U) |
Support for Channel to PaRAM Set mapping.
| #define SOC_EDMA_NUM_REGIONS (8) |
Number of EDMA Regions.
| #define SOC_EDMA_MEMPROTECT (1U) |
Support for Memory Protection.
| #define MCAN_MSG_RAM_MAX_WORD_COUNT (4352U) |
| #define ESM_NUM_GROUP_MAX (3U) |
| #define ESM_NUM_INTR_PER_GROUP (128U) |
| #define EDMA_APPSS_TPCC_A_EVT_SPI1_DMA_RX_REQ0 0 |
DSP TPCC A EVENT MAP.
| #define EDMA_APPSS_TPCC_B_EVT_FRAMETIMER_FRAME_START 0 |
DSP TPCC B EVENT MAP.
| #define EDMA_APPSS_TPCC_B_EVT_CHIRP_AVAIL_IRQ 1 |
| #define EDMA_APPSS_TPCC_B_EVT_CHIRPTIMER_CHIRP_END 2 |
| #define EDMA_APPSS_TPCC_B_EVT_CHIRPTIMER_CHIRP_START 3 |
| #define EDMA_APPSS_TPCC_B_EVT_CHIRPTIMER_FRAME_END 4 |
| #define EDMA_APPSS_TPCC_B_EVT_ADC_VALID_START 5 |
| #define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ0 6 |
| #define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ1 7 |
| #define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ2 8 |
| #define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ3 9 |
| #define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ4 10 |
| #define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ5 11 |
| #define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ6 12 |
| #define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ7 13 |
| #define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ8 14 |
| #define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ9 15 |
| #define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ10 16 |
| #define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ11 17 |
| #define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ12 18 |
| #define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ13 19 |
| #define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ14 20 |
| #define EDMA_APPSS_TPCC_B_EVT_HWA_DMA_REQ15 21 |
| #define EDMA_APPSS_TPCC_B_EVT_HWA_LOOP_INT 22 |
| #define EDMA_APPSS_TPCC_B_EVT_HWA_PARAMDONE_INT 23 |
| #define EDMA_APPSS_TPCC_B_EVT_SPI1_DMA_RX_REQ 24 |
| #define EDMA_APPSS_TPCC_B_EVT_SPI1_DMA_TX_REQ 25 |
| #define EDMA_APPSS_TPCC_B_EVT_SPI2_DMA_RX_REQ 26 |
| #define EDMA_APPSS_TPCC_B_EVT_SPI2_DMA_TX_REQ 27 |
| #define EDMA_APPSS_TPCC_B_EVT_FREE_0 28 |
| #define EDMA_APPSS_TPCC_B_EVT_FREE_1 29 |
| #define EDMA_APPSS_TPCC_B_EVT_FREE_2 30 |
| #define EDMA_APPSS_TPCC_B_EVT_FREE_3 31 |
| #define EDMA_APPSS_TPCC_B_EVT_FREE_4 32 |
| #define EDMA_APPSS_TPCC_B_EVT_FREE_5 33 |
| #define EDMA_APPSS_TPCC_B_EVT_FREE_6 34 |
| #define EDMA_APPSS_TPCC_B_EVT_FREE_7 35 |
| #define EDMA_APPSS_TPCC_B_EVT_FREE_8 36 |
| #define EDMA_APPSS_TPCC_B_EVT_FREE_9 37 |
| #define EDMA_APPSS_TPCC_B_EVT_FREE_10 38 |
| #define EDMA_APPSS_TPCC_B_EVT_FREE_11 39 |
| #define EDMA_APPSS_TPCC_B_EVT_FREE_12 40 |
| #define EDMA_APPSS_TPCC_B_EVT_FREE_13 41 |
| #define EDMA_APPSS_TPCC_B_EVT_FREE_14 42 |
| #define EDMA_APPSS_TPCC_B_EVT_FREE_15 43 |
| #define EDMA_APPSS_TPCC_B_EVT_FREE_16 44 |
| #define EDMA_APPSS_TPCC_B_EVT_FREE_17 45 |
| #define EDMA_APPSS_TPCC_B_EVT_FREE_18 46 |
| #define EDMA_APPSS_TPCC_B_EVT_FREE_19 47 |
| #define EDMA_APPSS_TPCC_B_EVT_FREE_20 48 |
| #define EDMA_APPSS_TPCC_B_EVT_FREE_21 49 |
| #define EDMA_APPSS_TPCC_B_EVT_FREE_22 50 |
| #define EDMA_APPSS_TPCC_A_NUM_PARAM_SETS (128U) |
| #define EDMA_APPSS_TPCC_A_NUM_DMA_CHANS (64U) |
| #define EDMA_APPSS_TPCC_A_NUM_TC (2U) |
| #define EDMA_APPSS_TPCC_B_NUM_PARAM_SETS (128U) |
| #define EDMA_APPSS_TPCC_B_NUM_DMA_CHANS (64U) |
| #define EDMA_APPSS_TPCC_B_NUM_TC (2U) |
| #define EDMA_TPCC_ERRAGG_TPCC_EERINT__POS (0U) |
| #define EDMA_TPCC_INTAGG_TPCC_INTG__POS (0U) |
| #define EDMA_TPCC_ERRAGG_TPTC_MIN_ERR__POS (2U) /* position of the lowest TC Id, others are higher */ |
| #define EDMA_APPSS_NUM_CC 4 |
| #define EDMA_APPSS_MAX_NUM_TC |
| #define EDMA_MSS_NUM_CC 6 |
| #define EDMA_MSS_MAX_NUM_TC |
| #define HWA_NUM_INSTANCES (1U) |
| #define SOC_HWA_NUM_MEM_BANKS (4U) |
number of HWA memory banks
| #define SOC_HWA_NUM_PARAM_SETS (32U) |
number of HWA parameter sets
| #define SOC_HWA_NUM_DMA_CHANNEL (16U) |
number of HWA MDA channels
| #define SOC_HWA_MEM_SIZE (CSL_APP_HWA_BANK_SIZE * SOC_HWA_NUM_MEM_BANKS) |
number of HWA memory size in bytes
| #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_0_LINE_END (0U) |
| #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_1_LINE_END (1U) |
| #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_2_LINE_END (2U) |
| #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_3_LINE_END (3U) |
| #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_4_LINE_END (4U) |
| #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_5_LINE_END (5U) |
| #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_6_LINE_END (6U) |
| #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_CONTEXT_7_LINE_END (7U) |
| #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_FRAME_START_0 (8U) |
| #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2B_FRAME_START_1 (9U) |
| #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_0_LINE_END (10U) |
| #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_1_LINE_END (11U) |
| #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_2_LINE_END (12U) |
| #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_3_LINE_END (13U) |
| #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_4_LINE_END (14U) |
| #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_5_LINE_END (15U) |
| #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_6_LINE_END (16U) |
| #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_CONTEXT_7_LINE_END (17U) |
| #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_FRAME_START_0 (18U) |
| #define HWA_HARDWARE_TRIGGER_SOURCE_CSI2A_FRAME_START_1 (19U) |
| #define APPSS_SYS_VCLK 160000000U |
1.8.20