9.1.2.1. Software¶

• Processor SDK RTOS for your platform
  • AM335x
  • AM437x
  • AM57x
  • AM65x
• CCS Version associated with your SDK Release
  • A download link for CCS is located on the same page as the SDK download.

9.1.2.2. Hardware¶

• A supported Sitara Evaluation Module
  • AM335x EVM
  • AM437x EVM
  • AM572x EVM
  • AM654x EVM
• JTAG Debug Probe if using AM572x EVM
  • XDS100-class JTAG debug probes
    • Low cost, low performance
    • XDS100v1 is not supported.
  • XDS200-class JTAG debug probes
    • Recommended
  • XDS560v2-class JTAG debug probes
    • High performance
• Serial UART cable provided in the EVM kit

9.1.2.3. Recommended Training Videos¶

• Processor SDK Training Series
  • Introduction to the Processor SDK Training Series
  • Processor SDK Overview
  • Introduction to Processor SDK RTOS Part 1
  • Introduction to Processor SDK RTOS Part 2
  • Application Development Using Processor SDK RTOS
• AM437x Sitara Processors Training Series
• AM57x Sitara Processors Training Series
• AM65x Sitara Processors Training Series

9.1.3.1. Components Used¶

• SYS/BIOS
• XDCTools
• Processor SDK RTOS PDK
  • Drivers, OSAL, etc.

9.1.3.2. Software Design¶

The Template Application is designed to provide a foundational project with a clean separation of the application-specific submodule from the startup and initialization code. This gives users the ability to focus on application-specific code and quickly get it up and running. This separation is achieved by splitting the “main” and “app” submodules into different files.

The source files are organized as follows:

└── template_app
    ├── main.c --> Main file including startup and init code
    ├── main.cfg --> Main BIOS config file
    ├── app.c  --> Application tasks are here
    ├── app.h  --> Application header file
    ├── app.cfg --> Application specific config file
    ├── app.defs --> Definitions (Currently empty)
    ├── rtos_template_app_<SOC>_<core>_<board>.projectspec --> Project spec file

In general, to write a new application app.c and app.h can be modified, recompiled, and run.

9.1.4.1. Task 1 - Installing the Processor SDK into CCS¶

Before using the Processor SDK, we must install its components into Code Composer Studio (CCS). Typically – if you chose to install the Software Development Kit (SDK) into the default $HOME/ti or C:\ti location – CCS will automatically detect the new products the next time it is opened and prompt you to install them. If you are not prompted to install the new products, you can do so manually through the Window –> Preferences –> Code Composer Studio –> Products menu. This menu will allow you define product discovery paths and rediscover, install, and unistall products.

For more info on setting up CCS. Check out Setup CCS for EVM and Processor-SDK RTOS in the How To Guides.

9.1.4.2. Task 2 - Importing and Building the RTOS Template Application¶

We begin the lab by importing the RTOS Template Application into CCS. The Template Application is delivered as a preconfigured CCS Project, making this process very simple. We will also use this as an opportunity to briefly dive into the structure of the SDK.

To import a project into CCS, go to the Project –> Import CCS Projects... menu. Typically, you will import SDK projects from either the pdk_<platform>_<version> or processor_sdk_rtos_<platform>_<version> directories. The pdk_<platform>_<version> directory contains Chip Support Library (CSL), Low Level Drivers (LLDs), Boot, Diagnostics, and other functions. It is also where LLD example projects are created. The processor_sdk_rtos_<platform>_<version> directory contains demos (including the RTOS Template App), documentation, and resources for creating bootable SD cards.

Now that you have an understanding of these directories, let us move on to importing the Template Application.

To import a project into CCS open the Project –> Import CCS Projects... menu. Then click Browse... to locate the template app which can be found at: processor_sdk_rtos_<platform>_<version>/demos/rtos_template_app/<soc_name>/<evm_name>/<core_name>. This will create a copy of the project in your CCS workspace.

After project import is complete you will see the Template Application under the Project Explorer on the left side of CCS. Next, right click on the project and select Build Project. You should get a message that says **** Build Finished **** in the CCS Console.

9.1.4.3. Task 3 - Hardware Setup¶

Hardware setup will vary depending on which EVM you are using. Generally, you need to make sure that the boot switches are set correctly and that serial, a JTAG debug probe, and power are connected to the board.

Refer to the Quick Start Guide that came with your board and the Hardware User’s Guide for more detailed hardware setup information.

• AM335x EVM:
  • Quick Start Guide
  • HW User’s Guide
• AM437x EVM:
  • Quick Start Guide
  • HW User’s Guide
• AM572x EVM:
  • Quick Start Guide
  • HW User’s Guide
• AM654x EVM - Quick Start Guide

Example connections for the AM572x EVM are provided below:

9.1.4.3.1. Front¶

9.1.4.3.2. Back¶

9.1.4.4. Task 4 - Loading and Running the RTOS Template Application¶

9.1.4.4.1. Creating a Target Configuration File¶

In order to connect to the target platform we first need to create a target configuration file. To do this, open CCS and go to the File –> New –> Target Configuration File menu and create a new target configuration file named after your board. For example, am572x-evm.ccxml. Next, you need to choose your connection and board on the target configuration file page. The connection is your chosen JTAG Debug Probe (for example, the XDS200) and the board is the name of your EVM (either EVMAM3358, EVMAM437X, or GPEVM_AM572x_SiRevA).

For example, here is the target configuration for the AM572x EVM using an XDS200 Debug Probe:

After setup is complete, clike the Save button to save your target configuration. Then click Test Connection to verify that you can connect to the board. If the test is successful you should receive the following message:

The JTAG DR Integrity scan-test has succeeded.

9.1.4.4.2. Connecting to the Target¶

With our target configuration confirmed, we can now move on to connecting to the target and loading our application.

First, set up the UART connection using the following host configuration in your favorite serial terminal program (e.g. Tera Term, screen, Minicom):

• Baud Rate: 115200
• Data Bits: 8
• Parity: None
• Flow Control: Off

Next, click on View –> Target Configurations in CCS. Then, right click on the target configuration that you created earlier and click Launch Selected Configuration. This action will switch CCS into the debug perspective. Your CCS instance should look similar to below:

In the top left corner of CCS you should see a list of all of the available cores on your device. Right click on the primary core (listed below) and choose the Connect Target option. During this process you should see GEL output in the CCS console and the status of the core should change from “Disconnected” to “Suspended”.

Primary cores for each target:

AM335x	AM437x	AM572x	AM654x
A8	A9	A15_0	A53_0

Note

For AM572x EVM, the template application can also run on the M4 and DSP cores. If you intend to run the application on one of these cores you must still connect to the main A15_0 core first. After connecting to the A15_0 core you can then follow the same procedure as above to connect to the secondary core where you would like to run the application. Do not attempt to load and run the template application on two cores simultaneously as the Template Application is not designed to run this way.

9.1.4.4.3. Running the Application¶

Now that we are connected to the target, it is time to load the application. To do this, go to the Run –> Load –> Load Program menu in CCS. Then, click the Browse project... button and choose the rtos_template_app_<board>_<core>.out executable. Then click OK to load the executable.

You should now see the main.c file open in CCS and the program halted at the beginning of the main() function. At this point you can click on the Resume (F8) button to start executing the Template Application.

The application will begin running and print progress over the UART. You should see the following text printed to your serial terminal:

Board Init complete
Uart Init complete
I2C Init complete
Gpio Init complete
MCSPI Init complete
======== Peripheral Initialization complete ========

======== Starting to create application tasks ========

gpio_toggle_led_task task created.
uart_task task created.
spi_test_task task created.
i2c_eeprom_read_and_display_task task created.
======== Application tasks created successfully ========

gpio_toggle_led task started
uart_task task started

i2c_eeprom_read_and_display task started
spi_test task started
Board Name read: AM572PM_
Board version read: A.30
spi_test task ended
i2c_eeprom_read_and_display task ended
uart_task :Enter a word or Esc to quit >

Type a word into the serial terminal. It should be echoed back to you. Then, enter the ESC character to exit the Template Application. For example:

uart_task :Enter a word or Esc to quit >hello
Data received is:hello

uart_task :Enter a word or Esc to quit >test
Data received is:test

uart_task :Enter a word or Esc to quit >^[

uart_task task ended
Template app ended

Next, click the Terminate button to disconnect from the target. At this point you have successfully imported, built, and run the Template Application.

9.1.4.5. Task 5 - Examining the RTOS Template Application¶

Now that you’re familiar with using the Template Application, let us look into the code to see how it all works.

/* Standard header files */
#include <string.h>

/* XDCtools Header files */
#include <xdc/std.h>
#include <xdc/cfg/global.h>
#include <xdc/runtime/System.h>
#include <xdc/runtime/Error.h>

/* BIOS Header files */
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/knl/Task.h>

/* Board header file */
#include <ti/board/board.h>

/* Local template app header file */
#include "app.h"

void myTaskFunc(UArg arg0, UArg arg1)

9.1.4.6. Task 6 - Modifying the Template Application¶

Now that you have an understanding of how to use the drivers and create RTOS tasks, let us make some simple modifications to create our own application.

We will create a simple application which allows the user to control the LED blink rate over the UART terminal. The user should be able to enter an LED blink period (between 0 and 5 seconds) and the user LED should blink at that rate.

This part of the lab is broken down into several sections. In each section, you will be given general instructions for modifications to make to the source files. After you make your own modifications they will be verified against provided code examples. Try to make the modifications on your own before looking at the answers!

var Mailbox = xdc.useModule('ti.sysbios.knl.Mailbox');

#include <ti/sysbios/knl/Mailbox.h>

Mailbox_Handle Mailbox_create(SizeT             bufsize,
                              UInt              numBufs,
                              Mailbox_Params    *params,
                              Error_Block       *eb)

9.1.5.1. Porting to a Custom Board¶

The Template Application can be easily modified to run on a custom board. The major change required is to link in a new Board Library. Modifying the Template Application for your custom Board can be achieved by simply removing the ti.board library and PATH from the project and replacing with your specific board libraty and PATH under the linker build options in CCS by right clicking on the project and selecting Properties –> GNU Linker –> Libraries.

For example, currently the library linked for AM572x is specified in the .projectspec file as follows:

linkerBuildOptions=
    -L${TI_PDK_INSTALL_DIR}/packages/ti/board/lib/evmAM572x/a15/release/
    -l:ti.board.aa15fg

9.2.3.1. More about processing algorithms¶

The application will use IMGLIB APIs for its core image processing needs. The following steps are performed for edge detection:

• Split input image into multiple overlapping slices
• If it is a RGB image, separate out the Luma component (Y) for processing (See YCbCr for further details)
• Run Sobel operator (IMG_sobel_3x3_8) to get the gradient image of each slices
• Run the thresholding operation ( IMG_thr_le2min_8) on the slices to get the edges
• Combine the slices to get the final output

9.2.3.2. Framework for multicore¶

The current framework for multicore is IPC (Message Queue). The following are the overall steps (the master and threads will be run on one or more cores):

• The master thread will preprocess the input image to make a gray scale or luma image
• The master thread signal each slave thread to start processing and wait for processing complete signal from all slave threads
• The slave threads run edge detection function to generate output edge image of the slice
• Then the slave threads signal master thread indicating the processing completed
• Once master thread receives completion signal from all threads it proceeds with further user interface processing

9.2.3.3. How to Build the Demo¶

source ./setupenv.sh
make demo_clean
make demo
the OUT files for A15, DSP1 and DSP2 will be built at
   ~/ti/processor_sdk_rtos_am57xx_x_0x_xx_xx/demos/image_processing/ipc/evmam572x/host/build,
   ~/ti/processor_sdk_rtos_am57xx_x_0x_xx_xx/demos/image_processing/ipc/evmam572x/dsp1/build, and
   ~/ti/processor_sdk_rtos_am57xx_x_0x_xx_xx/demos/image_processing/ipc/evmam572x/dsp2/build respectively

setupenv.bat
gmake demo_clean
gmake demo
the OUT files for A15, DSP1 and DSP2 will be built at
   C:\ti\processor_sdk_rtos_am57xx_x_0x_xx_xx\demos\image_processing\ipc\evmam572x\host\build,
   C:\ti\processor_sdk_rtos_am57xx_x_0x_xx_xx\demos\image_processing\ipc\evmam572x\dsp1\build, and
   C:\ti\processor_sdk_rtos_am57xx_x_0x_xx_xx\demos\image_processing\ipc\evmam572x\dsp2\build respectively

source ./setupenv.sh
make demo_clean
make demo
the OUT files for DSPs will be built at
   ~/ti/processor_sdk_rtos_c665x_x_0x_xx_xx/demos/image_processing/ipc/evmc6657l/master/build,
   ~/ti/processor_sdk_rtos_c665x_x_0x_xx_xx/demos/image_processing/ipc/evmc6657l/slave/build respectively

setupenv.bat
gmake demo_clean
gmake demo
the OUT files for DSPs will be built at
   C:\ti\processor_sdk_rtos_c665x_x_0x_xx_xx\demos\image_processing\ipc\evmc6657l\master\build,
   C:\ti\processor_sdk_rtos_c665x_x_0x_xx_xx\demos\image_processing\ipc\evmc6657l\slave\build respectively

source ./setupenv.sh
make demo_clean
make demo
the OUT files for DSPs will be built at
   ~/ti/processor_sdk_rtos_c667x_x_0x_xx_xx/demos/image_processing/ipc/evmc6678l/master/build,
   ~/ti/processor_sdk_rtos_c667x_x_0x_xx_xx/demos/image_processing/ipc/evmc6678l/slave/build respectively

setupenv.bat
gmake demo_clean
gmake demo
the OUT files for DSPs will be built at
   C:\ti\processor_sdk_rtos_c667x_x_0x_xx_xx\demos\image_processing\ipc\evmc6678l\master\build,
   C:\ti\processor_sdk_rtos_c667x_x_0x_xx_xx\demos\image_processing\ipc\evmc6678l\slave\build respectively

source ./setupenv.sh
make demo_clean
make demo
the OUT files for A15, DSPs will be built at
   ~/ti/processor_sdk_rtos_k2hk_x_0x_xx_xx/demos/image_processing/ipc/evmk2hk/master/build,
   ~/ti/processor_sdk_rtos_k2hk_x_0x_xx_xx/demos/image_processing/ipc/evmk2hk/slave/build respectively

setupenv.bat
gmake demo_clean
gmake demo
the OUT files for A15, DSPs will be built at
   C:\ti\processor_sdk_rtos_k2hk_x_0x_xx_xx\demos\image_processing\ipc\evmk2hk\master\build,
   C:\ti\processor_sdk_rtos_k2hk_x_0x_xx_xx\demos\image_processing\ipc\evmk2hk\slave\build respectively

9.2.3.4. How to Run the Demo¶

9.2.3.4.1. AM572x GP EVM (Using CCS)¶

The CCS is used to load the program and run on ARM-A15 (HOST), C66x Core 1 (DSP1) and C66x Core 2 (DSP2) by following the steps below:

• Launch CCS and connect to AM572 GP EVM using proper target configuration
• Connect to CortexA15_0 (Host) [Push “Power” button right before connect to CortexA15_0]

• Connect to C66xx_DSP1

• Connect to C66xx_DSP2

• Load image_processing_evmam572x_dsp1.out to C66xx_DSP1 using JTAG

• Run image_processing_evmam572x_dsp1.out on C66xx_DSP1
• Load image_processing_evmam572x_dsp2.out to C66xx_DSP2 using JTAG

• Run image_processing_evmam572x_dsp2.out on C66xx_DSP2
• Loaded image_processing_evmam572x_host.out to CortexA15_0

• Run image_processing_evmc6678l_master.out on CortexA15_0
• The HOST will display the IP address on CCS CIO

• Users can use internet browser to access this IP address
• The Image Processing Demo page will be displayed
• Provide values for the “Number of Cores” and “Select Image to Process” fields

The HOST will read the image via NDK, partition it according to the number of cores, send the messages to DSP cores (Slaves) via IPC MessageQ. The DSP cores will start processing the partitioned images concurrently. The resulting output image will be stored in DDR and the HOST will be notified by DSP cores via IPC MessageQ. Subsequently, the HOST will write the input and output images to the Image Processing Demo page using NDK.

9.2.3.4.2. AM572x GP EVM (Using SBL)¶

The SBL is used to load the program from SD card and run on ARM-A15 (HOST), C66x Core 1 (DSP1) and C66x Core 2 (DSP2) by following the steps below:

• Copy “app” and “MLO” from processor_sdk_rtos_am57xx_x_0x_00_0x\prebuilt-sdcards\evmAM572x\sd_card_files on Windows or processor_sdk_rtos_am57xx_x_0x_00_0x/prebuilt-sdcards/evmAM572x/sd_card_files on Linux to the root directory of a formatted micro SD card
• Plug in the micro SD card into uSD slot on AM572x GP EVM
• Connect “Serial Debug” on AM572x GP EVM to a PC USB port via a “Serial to USB” cable
• Launch a terminal emulator like Tera Term and open the local COM port corresponding to the “Serial Debug” (Set it to 115200 bps, 8 bit, none parity, one bit stop, no flow control)
• Plug power adapter (12V) into the AM572x GP EVM (DC-In) and power on the EVM
• There the IP address will be displayed on the “Serial Debug”
• Users can use internet browser to access this IP address
• The Image Processing Demo page will be displayed
• Provide values for the “Number of Cores” and “Select Image to Process” fields

The HOST will read the image via NDK, partition it according to the number of cores, send the messages to DSP cores (Slaves) via IPC MessageQ. The DSP cores will start processing the partitioned images concurrently. The resulting output image will be stored in DDR and the HOST will be notified by DSP cores via IPC MessageQ. Subsequently, the HOST will write the input and output images to the Image Processing Demo page using NDK.

9.2.3.4.3. C6678 EVM or C6657 EVM¶

CCS is used to load the program and Core 0 will be configured as the host. The following steps show C667x but a similar process applies for C665x.

• Launch CCS and connect to C6678 EVM using proper target configuration
• Connect to C66x Core 0 (Host)

• Loaded image_processing_evmc6678l_master.out to C66x Core 0

• Run image_processing_evmc6678l_master.out on C66xx_0
• Group C66x Core 1-N into a group (Group 1, Slave)
• Connect to Group 1

• Load image_processing_evmc6678l_slave.out to Group 1 using JTAG

• Run image_processing_evmc6678l_slave.out on Group 1
• The HOST will display the IP address on CCS CIO

• Users can use internet browser to access this IP address
• The Image Processing Demo page will be displayed
• Provide values for the “Number of Cores” and “Select Image to Process” fields

The HOST will read the image via NDK, partition it according to the number of cores, send the messages to DSP cores (Slaves) via IPC MessageQ. The DSP cores will start processing the partitioned images concurrently. The resulting output image will be stored in DDR and the HOST will be notified by DSP cores via IPC MessageQ. Subsequently, the HOST will write the input and output images to the Image Processing Demo page using NDK.

9.2.3.4.4. K2H EVM¶

CCS is used to load the program and arm_A15_0 will be configured as the master and C66xx_0 - C66xx_7 will be configured as slaves.

• Launch CCS and connect to K2H EVM using proper target configuration
• Connect to arm_A15_0 (Host)

• Group C66xx_0 to C66xx_7 into a group (Group 1, Slaves)

• Connect to Group 1

• Load image_processing_evmk2hk_slave.out to Group 1 using JTAG

• Run image_processing_evmk2hk_slave.out on Group 1

• Loaded image_processing_evmk2hk_master_arm.out to arm_A15_0

• Run image_processing_evmk2hk_master_arm.out on arm_A15_0

• The HOST will display the IP address on CCS CIO

• Users can use internet browser to access this IP address
• The Image Processing Demo page will be displayed
• Provide values for the “Number of Cores” and “Select Image to Process” fields

The HOST will read the image via NDK, partition it according to the number of cores, send the messages to DSP cores (Slaves) via IPC MessageQ. The DSP cores will start processing the partitioned images concurrently. The resulting output image will be stored in DDR and the HOST will be notified by DSP cores via IPC MessageQ. Subsequently, the HOST will write the input and output images to the Image Processing Demo page using NDK.

9.3.5.1. Processor-SDK RTOS¶

To build the project manually, first navigate to the top level makefile:

<SDK_INSTALL_PATH>/processor_sdk_rtos_<platform>_2_00_xx_xx/demos/posix-smp/makefile

Edit the makefile to include the paths to BIOS, XDC, PDK packages, and the toolchains for the cores being used.

#DEPOT = <ROOT_INSTALL_PATH>
#### BIOS-side dependencies ####
#BIOS_INSTALL_PATH ?= $(DEPOT)\bios_n_nn_nn_nn
#XDC_INSTALL_PATH ?= $(DEPOT)\xdctools_n_nn_nn_nn_core
#### BIOS-side toolchains ####
#TOOLCHAIN_PATH_A15 ?= $(DEPOT)\ccsv6\tools\compiler\gcc-arm-none-eabi-n_n-xxxxqn
#TOOLCHAIN_PATH_M4 ?= $(DEPOT)\ccsv6\tools\compiler\ti-cgt-arm_x.x.x

Navigate to the demo directory and run “make”. The steps to run the demo will be the same.

9.3.5.2. Processor-SDK Linux¶

The Posix-SMP demo has been added to the Linux SDK matrix starting in Processor-SDK 3.0. Simply run the example from the Matrix and the output will be displayed on the console.

For the documentation on the Linux Matrix, please see: link.

9.4.7.1. Using Makefile¶

Step1 : Setup Processor SDK RTOS build Environment.

Developers are required to setup the Processor SDK RTOS build environment as described in Processor SDK RTOS Setup environment

1. set SDK_INSTALL_PATH = C:\ti\<Install directory>
2. setupenv.bat

Step2 : Invoke Make from root directory

The make file in the root director of the audio-starterkit can be used to build the entire package. To build the benchmark examples:

1. cd <PROC_SDK_INSTALL_PATH>/demos/audio-benchmark-starterkit
2. make all

For Other supported options, please type

For Windows:

gmake help

For Linux :

make help

All available options are provided below:

9.4.7.2. Using CCS Projects¶

The audio benchmark starterkit does not provide pre-canned CCS Projects as it is difficult to set up projects to be portable across various developer build environments. To create CCS Projects with the benchmarks, developers are required to run the BenchmarkProjectCreate script provided in the root directory of the starterkit.

Step1 : Setup Processor SDK RTOS build Environment.

1. set SDK_INSTALL_PATH = C:\ti\<Install directory>
2. set TOOLS_INSTALL_PATH = C:\ti\<CCS Install directory>
3. setupenv.bat

Developers are required to setup the Processor SDK RTOS build environment as described in Processor SDK RTOS Setup environment

If developers install CCS or Processor SDK RTOS under a Custom path then they need to refer to the setup instructions described under Setup environment when installing to a custom path

Step 2: Run BenchmarkProjectCreate script to generate CCS Projects

To generate the CCS Projects

1. cd $PROC_SDK_INSTALL_PATH/demos/audio-benchmark-starterkit
2. BenchmarkProjectCreate [Options]

The Project create script can be run using the following syntax

BenchmarkProjectCreate.bat <soc> <board> <all>

Description of arguments:

• soc - K2G (Default) / K2H/ K2E/ C6678/ C6657/ AM572X/ AM571x/ OMAPL138
• board - all (Default) / <SOC supported EVMs>
• module - all / (FFT / FIR / IIR)

Example:
 a) BenchmarkProjectCreate.bat
             - Creates all module projects for the K2G soc for evmK2G platform
 b) BenchmarkProjectCreate.bat AM572x
             - Creates all module projects for AM572x soc for evmAM572x and idkAM572x platform
 c) BenchmarkProjectCreate.bat C6657 evmC6657
             - Creates all modules for C6657 DSP for evmC6657 platform
 d) BenchmarkProjectCreate.bat K2H evmK2H FFT
             - Creates FFT module project for K2H soc for evmK2H

Step 3: Import Generated CCS Projects in CCS Workspace

Launch CCS and Import the CCS Project using the Project->Import Existing CCS Project and browse to the audio-benchmark-starterkit folder

Step 4: Build Imported CCS Benchmark Projects

Right click on the Benchmark Project File and Build the project as shown below:

9.4.8.1. Using CCS¶

Step 1: Connect Emulator and UART to Hardware

• Refer to the Hardware Setup guide and connect the onboard or external emulator to the Hardware and Host machine with CCS installed.
• Connect the UART cable from the EVM to the Host machine and configure the Serial console with following settings:
  • Baud Rate: 115200
  • Data Bits: 8
  • Parity: None
  • Flow Control: Off

Step 2: Create Target configuration and connect to the DSP

To connect to the SOC, developers need to create a Target configuration by following the procedure described in wiki Create_Target_Configuration_File_for_EVM

Instructions specific to supported EVMs:

• K2G GP EVM CCS Setup
• AM572x GP EVM CCS Setup

Step 3: Loading and Running Benchmark application on the DSP

• Load the out file using Run -> Load -> Load Program and browse to the output binary.
• After loading the out file, run the benchmark app by Pressing F8 or Run -> Resume

9.4.8.2. Using SD card (Supported only on AM57xx and K2G)¶

Step 1: Run Create SD script to generate SD bootable binaries

The root directory in the audio-benchmark-starterkit contains a create-sd.bat file that will convert the .out files installed int the bin folder into SD bootable images which will be installed in the path bin/sd_card_files/<EVM>

The syntax to run the create-sd script is as follows:

create-sd.bat <EVM>

EVM : refers to evaluation platfom on which the binaries are meant to be run

Eg: create-sd evmK2G - Creates SD bootable images for K2G EVM.

Step 2 : Format and copy the SD card binaries to the SD card

Create an SD card using the procedure described in Creating SD card in Windows and Create SD card in Linux

Copy the “MLO” and “Singleprecision_<Module>_app” to the boot partition on the SD card.

Step 3: Boot the Benchmark app by configuring SD boot on the EVM

• Configure the boot switches on the evaluation hardware to SD boot.
• Insert the SD card in the microSD or SD card slot on the board.
• Connect the UART on the hardware to the Host and configure the host to Baud Rate= 115200, Data Bits= 8 , Parity= None, Flow Control= Off
• Power on the EVM to view the output on the Serial console on the host

9.4.9.1. Benchmark Starterkit Implementation¶

Signal Processing functions used in Starterkit

Single Precision FFT: DSPF_sp_fftSPxSP (Mixed Radix Forward FFT )

The audio benchmark kit uses the FFT implementation(DSPF_sp_fftSPxSP) from the TI DSP Library. The DSPF_sp_fftSPxSP kernel calculates the discrete Fourier transform of complex input array ptr_x using a mixed radix FFT algorithm. The result is stored in complex output array ptr_y in normal order. Each complex array contains real and imaginary values at even and odd indices, respectively. DSPF_sp_fftSPxSP kernel is implemented in assembly to maximize performance, but a natural C implementation is also provided. The demonstration app for this kernel includes the required bit reversal coefficients, brev, and additional code to calculate the twiddle factor coefficients, ptr_w.

Single Precision FIR: DSPF_sp_fir_cplx (Complex FIR Filter)

The audio benchmark kit uses the FFT implementation(DSPF_sp_fftSPxSP) from the TI DSP Library. The DSPF_sp_fir_cplx kernel performs complex FIR filtering on complex input array x with complex coefficient array h. The result is stored in complex output array y. For each complex array, real and imaginary elements are respectively stored at even and odd index locations.

The API reference and the implementation details can found in the TI DSPLIB documentation included in the Processor SDK.

Single Precision IIR : tisigCascadeBiquadSP_2c_3s_kernel (Cascade Biquad Filter for Multichannel input)

The Cascade biquad filtering function in the audio benchmark starterkit is an improved biquad infinite impulse response filter Patent US20160112033 Pending. The new filter structure modifies the feedback path in the filter, resulting in a significant reduction in execution cycles. One of the most-used digital filter forms is the biquad. A biquad is a second order (two poles and two zeros) Infinite Impulse Response (IIR) filter. It is high enough order to be useful on its own, and because of the coefficient sensitivities in higher order filters the biquad is often used as the basic building block for more complex filters. For instance, a biquad low pass filter has a cutoff slope of 12 dB/octave, useful for tone controls; if a 24 dB/octave filter is needed, you can cascade two biquads and it will have less coefficient sensitivity problems than a single fourth-order design.

For implementation details please check the USTO link

API reference:

int tisigCascadeBiquad32f_2c_3skernel(CascadeBiquad_FilParam *pParam)

where CascadeBiquad_FilParam is defined as

CascadeBiquad_FilParam {
     float *restrict pin1;    // Input Data Channel 1
     float *restrict pin2;    // Input Data Channel 2
     float  *restrict pOut1;  // Output Data Channel 1
     float  *restrict pOut2;  // Output Data Channel 1
     float  *restrict pCoef;  // Filter Coefficients a, b for 3 stages
     float  *restrict pVar0;  // Filter Variables d0, d1 for 3 stages channel 0
     float  *restrict pVar1;  // Filter Variables d0, d1 for 3 stages channel 1
     int      sampleCount;    // Number of samples
}  CascadeBiquad_FilParam;

9.4.12.1. Configuring device clocks¶

Every SOC with TI DSP requires users to enable the DSP clocks by setting up the PLL and or enabling the DSP through Power Sleep Controller or Power and Control (PRCM) module. The way the clocks are set up differs depending on the environment setup

• Development environment with emulator:In this case the SOC clocks are setup using GEL files which are added to the target configuration file. For audio benchmark starterkit, this done using GEL files setup explained in the Hardware Setup section
• Application Boot from boot mediaIf you are booting application from a boot media like SD/MMC or flash device, the ROM bootloader or a secondary level bootloader performs the clock configuration. For audio starterkit, this initialization is done using board library which is linked to the secondary bootloader and the benchmark tests.

9.5.3.1. More about processing algorithms¶

The application will use AER & VOLIB APIs for its noise reduction processing needs. The following steps are performed for noise reduction:

• Use 7 canned audio inputs to generate 12 virtual mics using BF(Beamforming) (30° apart)
• Apply ASNR(Adaptive Spectral Noise Reduction) on each virtual mic
• Use MSS(Multiple Source Selection)to select the best virtual mic from the 12 virtual mics
• Do VAD(Voice Activity Detection) on the best virtual mic
• Write 1 processed audio channel into the buffer in DDR

9.5.3.2. Framework for Audio Pre-processing¶

The current framework is based on SYS/BIOS. The following are the overall steps:

• The CLK object in SYS/BIOS will be configured to generate a Software Interrupt(SWI) every 10 ms
• The SWI will prepare the audio frame buffer pointers for further processing
• The SWI will also send a semaphore to wake up the main thread
• When woke up, the main thread will perform the BF, ASNR, MSS and DRC
• The main thread will also output the final processing audio frame to the DDR
• After completed the audio frame processing, the main thread will wait on semaphore for next audio frames to come

9.5.4.1. How to Build the Demo¶

source ./setupenv.sh
make audio_preproc_clean
make audio_preproc
the OUT files for DSP1 will be built at
   processor_sdk_rtos_am57xx_4_xx_xx_xx/demos/audio-preprocessing/file_demo_bios/am572x/build

setupenv.bat
gmake audio_preproc_clean
gmake audio_preproc
the OUT files for DSP1 will be built at
   processor_sdk_rtos_am57xx_4_xx_xx_xx\demos\audio-preprocessing\file_demo_bios\am572x\build

source ./setupenv.sh
make audio_preproc_clean
make audio_preproc
the OUT files for DSP will be built at
   processor_sdk_rtos_k2g_4_xx_xx_xx/demos/audio-preprocessing/file_demo_bios/k2g/build

setupenv.bat
gmake audio_preproc_clean
gmake audio_preproc
the OUT files for DSP will be built at
   processor_sdk_rtos_k2g_4_xx_xx_xx\demos\audio-preprocessing\file_demo_bios\k2g\build

source ./setupenv.sh
make audio_preproc_clean
make audio_preproc
the OUT files for DSP will be built at
   processor_sdk_rtos_omapl137_4_xx_xx_xx/demos/audio-preprocessing/file_demo_bios/omapl137/build

setupenv.bat
gmake audio_preproc_clean
gmake audio_preproc
the OUT files for DSP will be built at
   processor_sdk_rtos_omapl137_4_xx_xx_xx\demos\audio-preprocessing\file_demo_bios\omapl137\build

9.5.4.2. How to Run the Demo¶

The demo along with the audio input files will be loaded onto the target using JTAG. After executing, the output file can be read from target. Play both input and output audio files to compare effect of audio pre-processing.

The following sections provide detailed steps for each EVM.

9.5.5.1. How to Build the Demo¶

source ./setupenv.sh
make audio_preproc_clean
make audio_preproc
the OUT files for DSP will be built at
   processor_sdk_rtos_k2g_4_xx_xx_xx/demos/audio-preprocessing/realtime_demo_bios/k2g/build

setupenv.bat
gmake audio_preproc_clean
gmake audio_preproc
the OUT files for DSP will be built at
   processor_sdk_rtos_k2g_4_xx_xx_xx\demos\audio-preprocessing\realtime_demo_bios\k2g\build

source ./setupenv.sh
make audio_preproc_clean
make audio_preproc
the OUT files for DSP will be built at
   processor_sdk_rtos_omapl137_4_xx_xx_xx/demos/audio-preprocessing/realtime_demo_bios/omapl137/make

setupenv.bat
gmake audio_preproc_clean
gmake audio_preproc
the OUT files for DSP will be built at
   processor_sdk_rtos_omapl137_4_xx_xx_xx\demos\audio-preprocessing\realtime_demo_bios\omapl137\make

9.5.5.2. How to Run the Demo¶

The demo works with the real time audio input from CMB. After processing is complete, the audio output will be sent to the line-out(left channel) of the K2G EVM on-board audio codec. For the purpose of comparison, the unprocessed center microphone (mic 8) will be sent out to the line-out (right channel) of the K2G EVM on-board audio codec.

The following sections provide detailed steps for each EVM.

9.5.6.1. Import Raw Audio Data File using Adobe Audition¶

• Launch the Adobe Audition CS5.5
• File –> Import –> Raw Data...
• The following dialog will pop up

• Select the raw audio file and input the correct parameters
• Click OK

9.5.6.2. Before and After Comparison¶

• Before audio pre-processing (t8/y16L7g3m7090_1.pcm)

• After audio pre-processing (t8/fileOutput.bin)

9.6.3.1. Hardware Setup¶

• Setup K2G EVM according to the Quick Start Guide
• Setup Audio Daughter Card according to the Quick Start Guide and attach it to the K2G EVM. The Audio Daughter Card connects to the EVM through the JP1 “Audio Expansion” and J12 “Serial Expansion” connectors on EVM.
• Connect an analog player output to the ADC_IN0-3 input jacks on the Audio Daughter Card.
• Connect a DVD/Blue-Ray player digital output (S/PDIF) to the MOD1 Digital Input (Optical) connector on the Audio Daughter Card.
• Connect speakers to DAC_OUT0-3 output jacks on the Audio Daughter Card.
• Connect a COM port on PC to UART0 port on K2G EVM using a RS-232 cable.
• Connect XDS2xx USB Onboard Debug Probe to a PC USB port using the USB cable delivered with the EVM.

9.6.3.2. Optional Setup for HDMI¶

• Connect the MDS HSR41P to the MDS IFB.
  • Connect HSR41P J4 “Main” header to the IFB J5 “Main” header using the short 26-wire ribbon cable. Ensure the red wire on the ribbon cable is connected between HSR41P J4 Pin1 and IFB J5 Pin1.
  • Connect HSR41P J7 “Sec” header to the IFB J2 “Sec” header using the short 34-wire ribbon cable. Ensure the red wire on the ribbon cable is connected between HSR41P J7 Pin1 and IFB J2 Pin1.
• Connect the MDS IFB to the Audio Daughter Card. Connect IFB J3 “McASP0” header to Audio Daughter Card “I2S Header” using the supplied long 34-wire ribbon cable. Ensure the red wire on the ribbon cable is connected between IFB J3 Pin1 and Audio Daughter Card “I2S Header” Pin1 (note the “I2S Header” is only 32 pins, so the two wires on the ribbon cable opposite Pin1 are unused).
• Connect HDMI cable from audio source (e.g. Blu-ray player) to HSR41P J6 “IN”. Connect HDMI cable to audio sink (e.g. HDMI enabled monitor) from HSR41P J8 “HDMI OUT”.
• Connect 5V AC to USB power supply to IFB power connector J1.

9.6.3.3. Software and Tools Setup¶

CCS is required to load the binaries and run the demo. Sed and Python are required for run time reselection of input/output, control and reconfiguration of decoding and/or audio stream procesing, etc. One may choose to run the demo first and then install Sed and Python for run-time reconfiguration.

• Download and Install CCS (download link available at Processor SDK download page)
• Obtain Sed 4.2.1 from https://gnuwin32.sourceforge.net/packages/sed.htm, executable installer, sed-4.2.1-setup.exe (click on Setup next to “Complete package, except sources” and download will start). Install it to c:/PA_Tools/GnuWin32 (or change installation location in <process-sdk installation root>/demos/performance-audio/src/setup_build_env/setup_env.bat.
• Obtain Python 2.7.14 from https://www.python.org/downloads/release/python-2714/ (click on Windows x86 MSI installer, and the installer python-2.7.14.msi will be downloaded automatically). Install it to c:/PA_Tools/Python27 (or change installation location in <process-sdk installation root>/demos/performance-audio/src/setup_build_env/setup_env.bat.
• Once Python is installed, open a Command Prompt and go to <process-sdk installation root>/demos/performance-audio/src/setup_build_env. Run setup_env.bat, and then go to <process-sdk installation root>/demos/performance-audio/tools/ and run setup.bat to install PyAlpha dependencies. Note: since tools/setup.bat will download Python packages from the web, one needs to make sure that the proxy environment variables are set properly.

9.6.3.4. Load and Run Pre-built Binaries¶

This demo can be run by loading and running the DSP and ARM binaries through CCS:

1. Click View -> Target Configurations.
2. In the Target Configurations window, right click and then click Import Target Configurations.
3. Browse to <process-sdk installation root>/demos/performance-audio/src/pasrc/test_dsp/targetConfigs, click K2GEVM.ccxml and then click Open.
4. In the Target Configurations window, right-click on K2GEVM.ccxml and select Launch Selected Configuration.
5. In the Debug window, right-click on the C66x and select Connect Target. The output from the GEL code invoked on the target connection can be observed in the Console output window. The final line of this output should read “C66xx: GEL Output: DDR3A initialization complete”.
6. In the Debug window, right-click on the CortexA15 and select Connect Target. The output from the GEL code invoked on the target connection can be observed in the Console output window. The final line of this output should read “CortexA15: GEL Output: A15 non secure mode entered”.
7. In the Debug Window, click on the C66x. Then open Run->Load->Load Program. In the Load Program window, click on Browse and double click <process-sdk installation root>/demos/performance-audio/prebuilt-binaries/test_dsp.xe66. Then click OK to load the C66x binary.
8. In the Debug Window, click on the CortexA15. Then open Run->Load->Load Program. In the Load Program window, click on Browse and double click <process-sdk installation root>/demos/performance-audio/prebuilt-binaries/test_arm.xa15fg. Then click OK to load the CortexA15 binary.
9. In the Debug window, click on the C66x. Then Open Run->Resume to execute the C66x code.
10. In the Debug window, click on the CortexA15. Then Open Run->Resume to execute the CortexA15 code.
11. The CIO Console output window should display memory usage statistics. The final line of output should display the memory usage summary for the EXT NC SHM heap.
12. Default input interface is S/PDIF. Play music on the media player with S/PDIF output. Sound should come out of speakers connected to analog out DAC_OUT0.

Limitations:

• If code needs to be reload and rerun, one must terminate the CCS debugging session, power cycle the EVM, and start a new CCS debugging session. Then repeat from step 4 listed above.

9.6.3.5. Run-time Reconfiguration (in Windows only)¶

Please make sure src/setup_build_env/setup_env.bat and tools/setup.bat have both been run to setup the tools path.

Output volume can be changed at run-time via Python scripts through UART:

• Open a windows command prompt, go to tools folder and use the following command to change output volume:
  • python.exe pyalpha -I alpha -h pa_i13_evmk2g_io_a -p COM1 writeVOLControlMasterN(<volume level>), where <volume level> is level adjustment from default in units of 0.5dB. For example, python.exe pyalpha -I alpha -h pa_i13_evmk2g_io_a -p COM1 writeVOLControlMasterN(-24) lowers the level by 12dB from default.

Input interface is S/PDIF by default and can be reslected at run-time (Note: interface can be reselected only when playing is stopped):

• Switch to HDMI input:
  • Stop playing
  • Issue command to change to HDMI input: python.exe pyalpha -I alpha -h pa_i13_evmk2g_io_a -p COM1 execPAIInHDMI
  • Play again using digital player with HDMI output
• Switch to analog input:
  • Stop playing
  • Issue command to change output to ADC slave: python.exe pyalpha -I alpha -h pa_i13_evmk2g_io_a -p COM1 execPAIOutAnalogSlave
  • Issue command to change input to analog: python.exe pyalpha -I alpha -h pa_i13_evmk2g_io_a -p COM1 execPAIInAnalog
  • Play again using analog player

Limitations of run-time reconfiguration as of this release:

• Input interface reselection can only be done when input is mute.
• Once analog input is selected, S/PDIF can NOT be selected anymore. One must reload the code and rerun the demo.

9.6.4.1. Setup Environment Variables in Linux¶

A bash shell script, <process-sdk installation root>/demos/performance-audio/src/setup_build_env/setup_env.sh, can be used to set up the environment variables:

• set the TI tools path and performance audio demo path in setup_env.sh properly.
• set version numbers of each component to what’s going to be used for the build (default is what’s delivered in PRSDK).
• run the shell script using command “source setup_env.sh”.

9.6.4.2. Setup Environment Variables in Windows¶

Batch file <process-sdk installation root>/demos/performance-audio/src/setup_build_env/setup_env.bat can be used to set up the environment variables.

• set variable TI_TOOLS_DIR in setup_env.bat properly (default is C:ti).
• set version numbers of each component to what’s going to be used for the build (default is what’s delivered in PRSDK).
• go to folder <process-sdk installation root>/demos/performance-audio/src/setup_build_env and run setup_env.bat (Note: this script MUST be run in the setup_build_env folder.)
• after running setup_env.bat, run setup_paf.bat in the same folder (Note: setup_env.bat MUST be run before setup_paf.bat).

9.6.4.3. Rebuild the Demo¶

• Go to source folder: <process-sdk installation root>/demos/performance-audio/src
• Issue command “make clean” and “make install” for Linux
• Issue command “gmake clean” and “gmake install” for Windows
• The rebuilt binaries are placed in src/install/pasdk/debug. They can also be found at src/pasdk/test_dsp/bin/debug and src/pasdk/test_arm/bin/debug

9.7.4.1. Architecture Updates for Linux¶

The following block diagram shows the various functional blocks used in the example on the host running linux.

The SharedRegion and HeapMem modules are not currently supported for Linux in the TI Standard IPC package.

The example provides these modules with same/similar API implemented for Linux with some limitations.

The CMEM APIs provide user space allocation of contiguous memory for the Big data buffers.

9.7.4.2. How to Run the Example¶

The Processor SDK Linux release includes the pre-built binaries for the host_linux example as part of the tisdk-rootfs-image filesystem.

Step 1 : To run the demo, the first step is to make sure there is no other default applications using the same resources. For example, the following command is needed to disable the default OpenCL applications.

systemctl stop ti-mct-daemon.service

Step 2: Switch the firmware running in the DSP. This can be done by using the following steps. Unbind dsp

echo 40800000.dsp > /sys/bus/platform/drivers/omap-rproc/unbind

Update firmware symbolic link

ln -sf /usr/bin/simple_buffer_example/release/server_dsp.xe66 /lib/firmware/dra7-dsp1-fw.xe66

Bind dsp

echo 40800000.dsp > /sys/bus/platform/drivers/omap-rproc/bind

Step 3: Now the Host side application can be run using the following command

/usr/bin/simple_buffer_example/release/app_host

The DSP side log can be checked by typing the following command to dump the trace.

cat /sys/kernel/debug/remoteproc/remoteproc2/trace0

Here is a sample log.

root@am57xx-evm:~# /usr/bin/simple_buffer_example/release/app_host DSP1
--> main:
[523682.897761] omap_hwmod: mmu0_dsp2: _wait_target_disable failed
[523682.903751] omap-iommu 41501000.mmu: 41501000.mmu: version 3.0
[523682.911797] omap-iommu 41502000.mmu: 41502000.mmu: version 3.0
--> Main_main:
--> App_create:
App_create: Host is ready
<-- App_create:
--> App_exec:
CMEM_init success
CMEM_getPool success
CMEM_allocPool success: Allocated buffer 0xaa641000
SharedRegion_setup success
App_taskFxn: SR_1, base 0xaa641000, len=1000000
HeapMem_setup success
HeapMem_create success
App_taskFxn: SR_1 heap, totalSize=16777216,totalFreeSize=16777216,largestFreeSize=16777216
App_taskFxn: SR_1 heap, buf=0x0xaa641080,size=16777216
App_exec: sending message 1
Shared memory phys Addr ffffffffa0000000
App_exec: sending message 2
App_exec: sending message 3
App_exec: message received 1
App_exec: Preparing message 4
App_exec: Sending message 4
App_exec: message received 2
App_exec: Preparing message 5
App_exec: Sending message 5
App_exec: message received 3
App_exec: Preparing message 6
App_exec: Sending message 6
App_exec: message received 4
App_exec: Preparing message 7
App_exec: Sending message 7
App_exec: message received 5
App_exec: Preparing message 8
App_exec: Sending message 8
App_exec: message received 6
App_exec: Preparing message 9
App_exec: Sending message 9
App_exec: message received 7
App_exec: Preparing message 10
App_exec: Sending message 10
App_exec: message received 8
App_exec: Preparing message 11
App_exec: Sending message 11
App_exec: message received 9
App_exec: Preparing message 12
App_exec: Sending message 12
App_exec: message received 10
App_exec: Preparing message 13
App_exec: Sending message 13
App_exec: message received 11
App_exec: Preparing message 14
App_exec: Sending message 14
App_exec: message received 12
App_exec: Preparing message 15
App_exec: Sending message 15
App_exec: message received 13
App_exec: Preparing message 16
App_exec: Sending message 16
App_exec: message received: 14
App_exec: message received: 15
App_exec: message received: 16
App_exec: Data check clean
<-- App_exec: 0
--> App_delete:
<-- App_delete:
<-- Main_main:

 Host: Test Passed
<-- main:
root@am57xx-evm:~#

root@am57xx-evm:~# cat /sys/kernel/debug/remoteproc/remoteproc2/trace0
[      0.000] 18 Resource entries at 0x95000000
[      0.000] [t=0x0002122e] xdc.runtime.Main: --> main:
[      0.000] registering rpmsg-proto:rpmsg-proto service on 61 with HOST
[      0.000] [t=0x003c5d7b] xdc.runtime.Main: NameMap_sendMessage: HOST 53, port=61
[      0.000] [t=0x003d5186] xdc.runtime.Main: --> smain:
[      0.000] [t=0x003e8259] Server: Server_create: server is ready
[      0.000] [t=0x003ecc97] Server: <-- Server_create: 0
[      0.000] [t=0x003f04a4] Server: --> Server_exec:
[     51.571] [t=0x00000008:a56e6a9a] Server: Message received...1
[     51.571] [t=0x00000008:a56f9b77] Server: Shared region entry configured...
[     51.571] [t=0x00000008:a5700cb1] Server: Server_exec: processed id 1, cmd=0x1
[     51.571] [t=0x00000008:a570aea5] Server: Message received...2
[     51.571] [t=0x00000008:a57119fd] Server: Server_exec: processed id 2, cmd=0x0
[     51.571] [t=0x00000008:a571b1e9] Server: Message received...3
[     51.571] [t=0x00000008:a5721eac] Server: Server_exec: processed id 3, cmd=0x0
[     51.571] [t=0x00000008:a5755f6b] Server: Message received...4
[     51.573] [t=0x00000008:a583e61b] Server: Server_exec: processed id 4, cmd=0x2
[     51.573] [t=0x00000008:a584a087] Server: Message received...5
[     51.574] [t=0x00000008:a592c2cc] Server: Server_exec: processed id 5, cmd=0x2
[     51.574] [t=0x00000008:a5937d8c] Server: Message received...6
[     51.575] [t=0x00000008:a5a19aeb] Server: Server_exec: processed id 6, cmd=0x2
[     51.575] [t=0x00000008:a5a2543d] Server: Message received...7
[     51.577] [t=0x00000008:a5b07d15] Server: Server_exec: processed id 7, cmd=0x2
[     51.577] [t=0x00000008:a5b137c0] Server: Message received...8
[     51.578] [t=0x00000008:a5bf5d83] Server: Server_exec: processed id 8, cmd=0x2
[     51.578] [t=0x00000008:a5c019cc] Server: Message received...9
[     51.579] [t=0x00000008:a5ce3dca] Server: Server_exec: processed id 9, cmd=0x2
[     51.579] [t=0x00000008:a5cef75e] Server: Message received...10
[     51.581] [t=0x00000008:a5dd247a] Server: Server_exec: processed id 10, cmd=0x2
[     51.581] [t=0x00000008:a5dde2d9] Server: Message received...11
[     51.582] [t=0x00000008:a5ec04df] Server: Server_exec: processed id 11, cmd=0x2
[     51.582] [t=0x00000008:a5ecc1a3] Server: Message received...12
[     51.583] [t=0x00000008:a5fae91c] Server: Server_exec: processed id 12, cmd=0x2
[     51.583] [t=0x00000008:a5fba4c6] Server: Message received...13
[     51.585] [t=0x00000008:a609d1c1] Server: Server_exec: processed id 13, cmd=0x2
[     51.585] [t=0x00000008:a60a8dd4] Server: Message received...14
[     51.585] [t=0x00000008:a60af96e] Server: Server_exec: processed id 14, cmd=0x0
[     51.585] [t=0x00000008:a60b9229] Server: Message received...15
[     51.585] [t=0x00000008:a60bffd3] Server: Server_exec: processed id 15, cmd=0x0
[     51.585] [t=0x00000008:a60e179b] Server: Message received...16
[     51.585] [t=0x00000008:a60e9727] Server: Server_exec: processed id 16, cmd=0x2000000
[     51.585] [t=0x00000008:a60f3fb7] Server: Server_exec: Data check clean
[     51.585] [t=0x00000008:a60fb280] Server: <-- Server_exec: 0
[     51.585] [t=0x00000008:a6101708] xdc.runtime.Main: DSP: Test Passed
[     51.585] [t=0x00000008:a6109170] Server: --> Server_delete:
[     51.585] [t=0x00000008:a6114fa2] Server: <-- Server_delete: 0
[     51.586] [t=0x00000008:a6127d48] Server: Server_create: server is ready
[     51.586] [t=0x00000008:a612ff93] Server: <-- Server_create: 0
[     51.586] [t=0x00000008:a613620c] Server: --> Server_exec:
root@am57xx-evm:~#

9.7.4.3. How to Re-Build the example¶

Also source code for the example is included in the Processor SDK Linux release. Once installed the source files can be found in the directory example-applications/big-data-ipc-demo-linux_<version>.

Prerequisites: Also need to have the Processor SDK RTOS release installed to build the DSP side RTOS image. See the instruction in RTOS SDK Getting Started Guide

The example can be rebuilt by using the following commands.

export TI_RTOS_PATH=<TI_RTOS_PROC_SDK_INSTALL_DIR>
make big-data-ipc-demo

(e.g)

export TI_RTOS_PATH=$HOME/ti
make big-data-ipc-demo

The test binaries can be installed into the default filesystem using the command.

make big-data-ipc-demo_install

<processor-sdk_linux-<platform>-<version>/example-applications/big-data-ipc-demo-linux-<version>/host_linux/simple_buffer_example.

9.7.5.1. How to Run the Example¶

The Processor SDK RTOS release include the pre-built binaries for the host_bios example under:

processor_sdk_<platform>_<version>/demos/bigdataipc/prebuilt-binaries/<board-name>/simple_buffer_example/release/

Also for the platforms that support boot through SDcard, pre-built boot image or ‘app’ bootable through SBL is located under:

processor_sdk_<platform>_<version>/demos/bigdataipc/prebuilt-binaries/bootimages/host_bios/simple_buffer_example/<board-name>/app

9.7.5.1.1. AM57xx & K2G boards¶

Pre-requisites

1. Create a bootable SDCard using the procedure here: Creating SD card in Windows or Create SD card in Linux

2. Connect the UART on the hardware to the Host. ( Configure the terminal/console to Baud Rate= 115200, Data Bits= 8 , Parity= None, Flow Control= Off )

Procedure

• Copy/overwrite the pre-built boot image ‘app’ corresponding to the board to a bootable SD Card
• Insert the SD card into the board
• Boot/Reboot the board

The application will be loaded and run automatically and the “Host: Test Passed” message will be printed to the UART console.

9.7.5.2. How to Re-Build the Example¶

The bigdata ipc examples can be built from the Processor SDK top level directory using the following steps

1. Build environment setup

Linux host

cd  <processor_sdk_<platform>_<version>
export SDK_INSTALL_PATH=<Base directory where Processor SDK is installed>
source setupenv.sh

Windows host

cd  <processor_sdk_<platform>_<version>
set SDK_INSTALL_PATH=<Base directory where Processor SDK is installed>
setupenv.bat

2. Build

make bigdataipc_examples

This creates the elf binaries for both the host and DSP cores. And the binaries can be installed using

make bigdataipc_examples_install

(NOTE: The above command installs the elf binaries under the prebuilt-binaries location mentioned above. Need to convert the prebuilt elf binaries into bootable images refer to Processor SDK RTOS Boot)

Source files

The source files for the example are located at

<processor_sdk_<platform>_<version>/demos/bigdataipc/host_bios/simple_buffer_example.

The host directory and dsp directory has the corresponding sources. The shared folder contains some common sources. The main sequence for big data IPC can be followed by looking at host/App.c and dsp/Server.c.

9.8.4. ARM Cortex-A9¶

The hello example serves as a basic sanity check program for SYS/BIOS. It demonstrates how to print the string ‘hello world’ to stdout.

1. Create a work space folder (\ti\am_437x_hello_workspace) under ti folder to be used for Hello Example project, and start CCS. You may be prompted with New Products Discovered, so select all and click on Finish

2. On CCS click View –> Resource Explorer (Examples).

3. On SYS/BIOS scroll down to AM4378 –> Cortex A –> Generic Example –> click on Hello Example.

4. To import Hello Example, on the right window click on step 1. Import The Example to CCS Project.

5. On New CCS Project window enter project name and then click Next.

6. On RSTC window select platform name: ti.platforms.evmAM437X and check that the target is set to gnu.targets.arm.A9F

7. Click Finish. Your project should show up on Project Explorer window.

8. To get log message to print on console add this variable to hello.cfg file:

var SemiHostSupport = xdc.useModule('ti.sysbios.rts.gnu.SemiHostSupport');

Right click on project –> Show Build Settings... –> Build –> GNU Linker –> Libraries

9. Build Hello Example project by Right click on Hello Project and click Build project.

10. Create new target configuration (if one doesn`t exist) as described here Create Target Configuration File for EVM

11. Right click on the target configuration and Launch target configurations.

12. Right click CortexA9_0 and connect target.

13. Load and run Hello Example out file. You should see Hello World string displayed on console window.

9.8.5. ARM Cortex-A8¶

The hello example serves as a basic sanity check program for SYS/BIOS. It demonstrates how to print the string ‘hello world’ to stdout.

1. Create a work space folder (\ti\am_335x_hello_workspace) under ti folder to be used for Hello Example project, and start CCS. You may be prompted with New Products Discovered, so select all and click on Finish

2. On CCS click View –> Resource Explorer (Examples).

3. On SYS/BIOS scroll down to AM3352 –> Cortex A –> Generic Example –> click on Hello Example.

4. To import Hello Example, on the right window click on step 1. Import The Example to CCS Project.

5. On New CCS Project window enter project name and then click Next.

6. On RSTC window select platform name: ti.platforms.evmAM335X and check that the target is set to gnu.targets.arm.A8F

7. Click Finish. Your project should show up on Project Explorer window.

8. To get log message to print on console add this variable to hello.cfg file:

var SemiHostSupport = xdc.useModule('ti.sysbios.rts.gnu.SemiHostSupport');

Right click on project –> Show Build Settings... –> Build –> GNU Linker –> Libraries

9. Build Hello Example project by Right click on Hello Project and click Build project.

10. Create new target configuration (if one doesn`t exist) as described here Create Target Configuration File for EVM

11. Right click on the target configuration and Launch target configurations.

12. Right click CortexA8_0 and connect target.

13. Load and run Hello Example out file. You should see Hello World string displayed on console window.

9.8.6. ARM Cortex-R5¶

The hello example serves as a basic sanity check program for SYS/BIOS. It demonstrates how to print the string ‘hello world’ to stdout.

1. Create a work space folder (/ti/am65x_r5_hello_workspace) under ti folder to be used for Hello Example project, and start CCS. You may be prompted with New Products Discovered, so select all and click on Finish

2. On CCS click View –> Resource Explorer Classic.

3. On SYS/BIOS scroll down to AM65x - Cortex A53 –> AM6548 –> Cortex R –> TI Target Examples –> Generic Examples –> click on Hello Example.

4. To import Hello Example, on the right window click on step 1. Import The Example to CCS Project.

5. On New CCS Project window enter project name, set the device endianness to little, and add the linker command file located at (PDK INSTALL PATH)/packages/ti/build/am65xx/linker_r5_sysbios.lds and click Next.

6. On RSTC window, make sure the correct XDCtools version is selected and select the correct versions of the SYS/BIOS and PDK packages.

7. Set the platform to ti.platforms.cortexR:AM65X and set the target to ti.targets.arm.elf.R5F.

8. Click Finish. Your project should appear in Project Explorer window.
9. Launch the target configuration using the appropriate emulator to connect to AM65x EVM as described in the AM65x EVM Hardware Setup Guide.
10. Right click on DMSC_Cortex_M3_0 and click Connect Target.
11. Connect to the MCU_PULSAR_Cortex_R5_0 core. Load and run Hello Example out file. You should see Hello World string displayed on console window.

9.8.7. ARM Cortex-M4¶

The hello example serves as a basic sanity check program for SYS/BIOS. It demonstrates how to print the string ‘hello world’ to stdout.

1. Create a work space folder (/ti/am_572x_hello_workspace) under ti folder to be used for Hello Example project, and start CCS. You may be prompted with New Products Discovered, so select all and click on Finish

2. On CCS click View –> Resource Explorer (Examples).

3. on SYS/BIOS scroll down to AM572X –> Cortex M –> Generic Example –> click on Hello Example.

4. To import Hello Example, on the right window click on step 1. Import The Example to CCS Project.

5. Go to Project Explorer window and click on project properties.

6. On RSTC window select platform name: ti.platforms.evmAM572X and check that the target is set to gnu.targets.arm.elf.M4

7. Click Finish. Your project should show up on Project Explorer window.

8. Build Hello Example project by Right click on Hello Project and click Build project.

9. Launch target configurations using appropriate emulator to connect to AM572X EVM.

10. Right click CortexA15_0 and connect target. From the Scripts menu select AM572x Multicore Initialization->IPU1SSClkEnable_API.

11. Connect to the Cortex_M4_IPU1_C0. Load and run Hello Example out file. You should see Hello World string displayed on console window.

9.8.8. DSP C66x¶

The hello example serves as a basic sanity check program for SYS/BIOS. It demonstrates how to print the string ‘hello world’ to stdout. As a sample we will use the AM572x device to describe the steps but the same steps can be used for create hello world examples for C66x cores in Keystone I and Keystone 2 family of devices.

1. Create a work space folder (tiam_572x_hello_workspace) under ti folder to be used for Hello Example project, and start CCS. You may be prompted with New Products Discovered, so select all and click on Finish

2. On CCS click View –> Resource Explorer (Examples).

3. on SYS/BIOS scroll down to AM572X –> C66x –> Generic Example –> click on Hello Example.

4. To import Hello Example, on the right window click on step 1. Import The Example to CCS Project.

5. On New CCS Project window enter project name and then click Next.

6. On RSTC window select platform name: ti.platforms.evmAM572X and check that the target is set to ti.targets.elf.C66 (Auto populated)

7. Click Finish. Your project should show up on Project Explorer window.

8. Build Hello Example project by Right click on Hello Project and click Build project.

10. Create new target configuration (if one doesn`t exist) as described here.

11. Right click on the target configuration and Launch target configurations.

12. Right click CortexA15_0 and connect target. From the Scripts menu select AM572x Multicore Initialization->DSP1SSClkEnable_API.

13. Route the GPTimer5 suspend ctrl signal to the DSP using the Scripts menu GP timer Suspend Ctrl -> GPTimer5SuspendCtl_DSP1SS_BIOS as described here.

14. Connect to C66x_DSP1 Load and run Hello Example out file. You should see Hello World string displayed on console window.

9.8.9. DSP C674x¶

The hello example serves as a basic sanity check program for SYS/BIOS. It demonstrates how to print the string ‘hello world’ to stdout. As a sample we will use the C6748 device to describe the steps but the same steps can be used for create hello world examples for C674x cores in OMAPL1x/DA8x family of devices.

1. Create a work space folder ( Eg. tirtos_hello_workspace) that can be used for Hello Example project, and start CCS. You may be prompted with New Products Discovered, so select all and click on Finish Note: at this stage the version of SYSBIOS and corresponding dependencies are assumed to be discovered by CCS. If not please follow the steps described here: Discovering_SDK_products

2. On CCS click View –> Resource Explorer Classic (Examples).

3. on SYS/BIOS scroll down to C6748 /OMAPL1x and select –> C674x –> Generic Example –> click on Hello Example.

4. To import Hello Example, on the right window click on step 1. Import The Example to CCS Project.

5. On New CCS Project window enter project name and then click Next.

6. On RSTC window select platform name: ti.platforms.evmc6748 and check that the target is set to ti.targets.elf.C674 (Auto populated)

7. Click Finish. Your project should show up on Project Explorer window.

8. Build Hello Example project by Right click on Hello Project and click Build project.

10. Create new target configuration (if one doesn`t exist) as described here.

11. Right click on the target configuration and Launch target configurations.

12. Developers can Connect to the C674x on OMAPL137/C6747/C6748 can connect directly to the DSP. For OMAPL138 device, you will need to connect to the ARM as this is ARM master boot device and ARM needs to power up the DSP You should see the following log in the Console

C674X_0: Output:   Target Connected.
C674X_0: Output:    ---------------------------------------------
C674X_0: Output:    Memory Map Cleared.
C674X_0: Output:    ---------------------------------------------
C674X_0: Output:    Memory Map Setup Complete.
C674X_0: Output:    ---------------------------------------------
C674X_0: Output:    PSC Enable Complete.
C674X_0: Output:    ---------------------------------------------
C674X_0: Output:    PLL0 init done for Core:300MHz, EMIFA:25MHz
C674X_0: Output:    DDR initialization is in progress....
C674X_0: Output:    PLL1 init done for DDR:150MHz
C674X_0: Output:    Using DDR2 settings
C674X_0: Output:    DDR2 init for 150 MHz is done
C674X_0: Output:    ---------------------------------------------

13. Connect to C674x_DSP1 Load and run Hello Example out file. You should see Hello World string displayed on console window.

9.8.10. Usage Notes¶

After execution of the hello world examples on the core, the CCS Editor may report “Can’t find a source file” error messages when you pause or the application exits/aborts after completion. This occurs due to source files from SYSBIOS or XDC packages not being in the default search path of the CCS Editor. when you run into this issue, you can navigate to the file using Locate file option in the Editor. Once you provide the location the CCS Editor will be able to locate all the other required files from that package based on relative path.

For example, when running SYS/BIOS Hello Example using AM57x-GP EVM if you see the message

Can't find a source file at "/db/ztree/library/trees/xdctargets/xdctargets-i02/src/gnu/targets    /arm/rtsv7A/syscalls.c"
Locate the file or edit the source lookup path to include its location. The above file is located  under file path ${PROC_SDK_DIR}\bios_6_42_02_29\packages\gnu\targets\arm\rtsv7A

You can also prevent these issues by adding the Processor SDK components to file search path under Windows->Preferences options in CCS GUI.

9.8.11. Known Issues¶

• SYS/BIOS examples for Cortex-A15 generate linker errors due to the FPU related flags

Some versions of CCS are impacted by linker setting used in CCS RTOS templates and may need some manual modification to set the correct -mfpu, -mcpu and -march. If you are seeing VFP errors in the link step, you are most likely running into this issue. To correct this issue please check the resolution here: https://e2e.ti.com/support/development_tools/code_composer_studio/f/81/t/539973

9.8.12. Useful Resources¶

• TI RTOS training
• SYS/BIOS Information
• SYS/BIOS FAQ

9.9.1. Overview¶

The bare-metal examples gets user started with development of code without an operating system. These are simple examples that does not get into details of software components provided in the SDK. Consequently, make sure there are no SD cards installed on the EVM with an OS prior to exploring the following examples.

If you face any problems with CCS or JTAG, try these troubleshooting steps.

9.9.2. ARM Cortex-A53¶

In this article, we take a look at creating bare-metal hello world examples for the Cortex-A53 core in CCS. We will be using the AM654x device as an example.

1. Start CCS and create a workspace for generating the project.

2. Navigate to File -> New -> CCS Project.

3. Select Target as AM65x - Cortex A53 and GPEVM_AM65x as shown in the image below.

4. Select Cortex A setting in the options below and provide a name for the project. Use the default advanced settings for the project. Select GNU v7.2.1 (Linaro aarch64) (or higher) for the Compiler Version. Under Tool-chain, for the Linker Command file, select the file (PDK INSTALL PATH)/packages/ti/build/am65xx/linker_a53.lds.

Under Project templates and examples, select Empty Project (with main.c).

Click Finish after you are done to allow CCS to auto generate the project from the template.

5. The generated CCS project contains source file main.c, ARM assembly code startup_ARMCA53.S and a linker command file AM65X.lds. Remove startup_ARMCA53.S and AM65X.lds from the project.

6. Add the following linker command file to the project.

(PDK INSTALL PATH)/packages/ti/build/am65xx/linker_a53.lds

7. Modify main.c to include the following:

/* Header files */
#include <stdint.h>
#include "stdio.h"

int main(void)
{
        printf("Hello World\n");
        while(1);
}

8. Navigate to Project Properties -> CCS Build -> GNU Linker and add “Entry” to the “Set start address” field.

9. Navigate to CCS Build -> GNU Linker -> Libraries and add the following libraries.

ti.csl.init.aa53fg
ti.csl.aa53fg
rdimon
stdc++
gcc
c
m

10. Add the following library search path.

(PDK INSTALL PATH)/ti/csl/lib/am65xx/a53/release

11. Save all changes, and right click on the project and select Build Project to build the project and generate hello_world.out.

12. Launch the target configuration using your emulator to connect to the AM65x EVM as described in the Processor SDK RTOS Getting Started Guide.

13. Right click on DMSC_Cortex_M3_0 and click connect to target. After connecting to the M3, right click on CortexA53_0_0 and connect to it.

14. Load and run hello_world.out example file on the Cortex-A53. You should see a Hello_world string displayed in the CCS console window.

9.9.3. ARM Cortex-A15¶

In this article, we take a look at creating bare-metal hello world examples for Cortex A15 core using pre-built templates in CCS. As a sample we will use the AM572x device to describe the steps but the same steps can be used for create hello world examples for Cortex A15 cores in the Keystone 2 family of devices.

1. Start CCS and create a work space for generating the project.
2. Click on File menu option and select New–> CCS Project.

3. Select Target as AM572x -Cortex A15 and GPEVM_AM572x as shown in the image

4. Select Cortex A setting in the options below and provide name of the project as “hello_world” and use default Advanced settings for the project. If the Default settings uses “TI ARM compiler 5.x.x” switch to GNU Linaro 4.8.4 (or higher) tool chain for A15 and check the build little endian ELF binary for the A15 core. Under Project templates and examples, select Basic Examples-> Hello World

Click Finish after you are done to allow CCS to auto generate the project from the template Basic Examples-> Hello World.

5. The generated CCS project contains source file main.c, ARM assembly code startup_ARMCA15.S and a linker command file AM572x.lds. Please modify the main.c file by adding the following highlighted code lines and save main.c file.

 /*
 * hello.c
 */
 #include <stdio.h>

 int main(void) {

     printf("Hello_world\n");
     return 0;
}

6. Ensure that CCSv6 generated linker command file AM572x.lds contains the following Memory configurations.

MEMORY
{
   OCMC_RAM1 :  o = 0x40300000,  l = 0x00080000  /* 512kB L3 OCMC RAM1 */
   OCMC_RAM2 :  o = 0x40400000,  l = 0x00100000  /* 1MB L3 OCMC RAM2 */
   OCMC_RAM3 :  o = 0x40500000,  l = 0x00100000  /* 1MB L3 OCMC RAM3 */
   DDR0 :       o = 0x80000000,  l = 0x40000000  /* 1GB external DDR Bank 0 */
   DDR1 :       o = 0xC0000000,  l = 0x40000000  /* 1GB external DDR Bank 1 */
}

MSMC  :      o=0x0c000000,    l = 0x00600000  /* 6MB Muticore shared memory */

STACKSIZE=10000
HEAPSIZE=400

7. Right click on the project and select Build Project, to build the project and generate hello_world.out.

8. Launch target configuration using your emulator to connect to AM572X EVM as described in the Processor SDK RTOS Getting Started Guide.

9. Right click CortexA15_0 and select connect target.

10. Initialize DDR configuration. On CCS –> Scripts –> DDR configurations –> AM572_DDR3_532MHz_config

11. Load and run hello_world.out example file. You should see Hello_world string displayed on CCS console window.

9.9.4. ARM Cortex-A9¶

1. Start CCSv6 and create a work space for generating the project.

2. Click on File menu option and select New–> CCS Project. Steps assume that user is using GN Linaro tool chain for Cortex A9.

3. Select Target as AM33xx -Cortex A8 and appropriate target Board setting as shown in the image

4. Select Cortex A8 setting in the options below and provide name of the project as “hello_world_a9” and use default Advanced settings for the project. If the Default settings uses “TI ARM compiler 5.x.x” switch to GNU Linaro 4.8.4 (or higher) tool chain for A9 and check the build little endian ELF binary for the A9 core. Click Finish after you are done to allow CCS to auto generate the project from the template Basic Examples-> Hello World.

5. The generated CCS project contains source file main.c, ARM assembly code startup_ARMCA8.S and a linker command file AM335x.lds. The startup file does some basic setup and there is no difference between A8 and A9, so it can be used directly on A9 target. Ensure the main.c file contains the following code

 /*
 * hello.c
 */
 #include <stdio.h>

 int main(void) {

     printf("Hello_world\n");
     return 0;
}

6. Ensure that CCSv6 generates the linker command file AM335x.lds.

MEMORY
{
   SRAM :     o = 0x402F0400,  l = 0x0000FC00  /* 64kB internal SRAM */
   L3OCMC0 :  o = 0x40300000,  l = 0x00010000  /* 64kB L3 OCMC SRAM */
   M3SHUMEM : o = 0x44D00000,  l = 0x00004000  /* 16kB M3 Shared Unified Code Space */
   M3SHDMEM : o = 0x44D80000,  l = 0x00002000  /* 8kB M3 Shared Data Memory */
   DDR0 :     o = 0x80000000,  l = 0x40000000  /* 1GB external DDR Bank 0 */
}

7. Now build the project to generate hello_world.out file.

8. Launch target configurations using your emulator to connect to AM335X EVM as described in the Getting Started Guide.

9. Right click CortexA9 and connect target. The on target functionality in the GEL will initialize the clocks and DDR.

10. Load and run hello_world_a9.out file. You should see Hello World! string displayed on CCS console window.

9.9.5. ARM Cortex-A8¶

1. Start CCSv6 and create a work space for generating the project.
2. Click on File menu option and select New–> CCS Project.

3. Select Target as AM33xx -Cortex A8 and appropriate target Board setting as shown in the image

4. Select Cortex A8 setting in the options below and provide name of the project as “hello_world_a8” and use default Advanced settings for the project. If the Default settings uses “TI ARM compiler 5.x.x” switch to GNU Linaro 4.8.4 (or higher) tool chain for A8 and check the build little endian ELF binary for the A8 core. Click Finish after you are done to allow CCS to auto generate the project from the template Basic Examples-> Hello World.

5. The generated CCS project contains source file hello.c, ARM assembly code startup_ARMCA8.S and a linker command file AM335x.lds. Ensure the main.c file contains the following code

 /*
 * hello.c
 */
 #include <stdio.h>

 int main(void) {

     printf("Hello_world\n");
     return 0;
}

6. Ensure that CCSv6 generates the linker command file AM335x.lds.

MEMORY
{
   SRAM :     o = 0x402F0400,  l = 0x0000FC00  /* 64kB internal SRAM */
   L3OCMC0 :  o = 0x40300000,  l = 0x00010000  /* 64kB L3 OCMC SRAM */
   M3SHUMEM : o = 0x44D00000,  l = 0x00004000  /* 16kB M3 Shared Unified Code Space */
   M3SHDMEM : o = 0x44D80000,  l = 0x00002000  /* 8kB M3 Shared Data Memory */
   DDR0 :     o = 0x80000000,  l = 0x40000000  /* 1GB external DDR Bank 0 */
}

7. Now build the project to generate hello_world_a8.out file.

8. Launch target configurations using your emulator to connect to AM335X EVM as described in the Getting Started Guide.

9. Right click CortexA8 and select connect target. The on target functionality in the GEL will initialize the clocks and DDR.

10. Load and run hello_world_a8.out file. You should see Hello World! string displayed on CCS console window.

9.9.6. ARM Cortex-R5¶

In this article, we take a look at creating bare-metal hello world examples for the Cortex-R5 core in CCS. We will be using the AM654x device as an example.

1. Start CCS and create a workspace for generating the project.

2. Navigate to File -> New -> CCS Project.

3. Select Target as AM65x - Cortex R5 and GPEVM_AM65x as shown in the image below.

4. Select the Cortex R tab and provide a name for the project. Select TI v16.9.4.LTS (or higher) for the Compiler Version. Under Tool-chain, set the Device Endianness to little, and for the Linker Command file, select linker_r5.lds located in the folder (PDK INSTALL PATH)/packages/ti/build/am65xx/.

Under Project templates and examples, select Basic Examples -> Hello World

Click Finish after you are done to allow CCS to auto generate the project from the template.

5. The generated CCS project contains source file hello.c, and linker command file linker_r5.lds.

6. Navigate to CCS Build -> ARM Linker -> File Search Path and add the following libraries.

ti.csl.aer5f
ti.csl.init.aer5f
libc.a

7. Add the following library search path.

(PDK INSTALL PATH)/ti/csl/lib/am65xx/r5f/release

8. Save all changes, and right click on the project and select Build Project to build the project and generate hello_world.out.

9. Launch the target configuration using your emulator to connect to the AM65x EVM as described in the Processor SDK RTOS Getting Started Guide.

10. Right click on DMSC_Cortex_M3_0 and click connect to target. After connecting to the M3, right click on MCU_PULSAR_Cortex_R5_0 and connect to it.

11. Load and run hello_world.out example file on the Cortex-R5. You should see a Hello_world string displayed in the CCS console window.

9.9.7. ARM Cortex-M4¶

1. Start CCSv6 and create a work space for generating the project.
2. Click on File menu option and select New–> CCS Project.

3. Select Target as AM572x -Cortex M4 and GPEVM_AM572x as shown in the image

4. Select Cortex M setting in the options below and provide name of the project as “hello_world_m4” and use default Advanced settings for the project. Click Finish after you are done to allow CCS to auto generate the project from the template Basic Examples-> Hello World. The Default settings uses “TI ARM compiler 5.x.x” tool chain for cortex M4 and sets the build for little endian ELF binary for the M4 core.

5. The generated CCS project contains only one source file hello.c. Ensure the main.c file contains the following code

 /*
 * hello.c
 */
 #include <stdio.h>

 int main(void) {

     printf("Hello_world\n");
     return 0;
}

6. CCSv6 includes a default linker command file(AM57xx_CM4.cmd) for the M4 (IPU) core which will place code into appropriate device memory. The linker command file has the following memory sections.

MEMORY
{
    IRAM:      o = 0x00000000 l = 0x00001000   /* 4kB internal SRAM */
    OCMC_RAM1: o = 0x40300000 l = 0x00080000   /* 512kB L3 OCMC SRAM1 */
    OCMC_RAM2: o = 0x40400000 l = 0x00100000   /* 1MB L3 OCMC SRAM2 */
    OCMC_RAM3: o = 0x40500000 l = 0x00100000   /* 1MB L3 OCMC SRAM3 */
    DDR0:      o = 0x80000000 l = 0x40000000   /* 1GB external DDR Bank 0 */
}

The linker command file is designed to place code in OCMC memory with interrupt vectors and .intc_txt generated by the compiler being place in device internal memory.

7. Now build the project to generate hello_world_m4.out.

8. Launch target configurations using your emulator to connect to AM572X EVM as described in the Getting Started Guide

9. In order to wake up the M4 core from A15, Go to Menu option Scripts->AM572x_Multicore_Initialization->IPU1SSClkEnable_API. Refer to the Processor_SDK_RTOS_Setup_CCS.

You should see the following log in the Console

CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<---

11. Select and Connect to Cortex_M4_IPU1_C0. Load and run Hello_Example_m4.out file. You should see Hello World string displayed on console window.

9.9.8. DSP C66x¶

In this article, we take a look at creating bare-metal hello world examples for C66x core using pre-built templates in CCS. As a sample we will use the AM572x device to describe the steps but the same steps can be used for create hello world examples for C66x cores in the Keystone 2 family of devices.

1. Start CCSv6 and create a work space for generating the project.
2. Click on File menu option and select New–> CCS Project.
3. Select Target as AM572x -C66xx and GPEVM_AM572x as shown in the image

4. Select C66XX [C6000] DSP setting in the options below and provide name of the project as “hello_world_dsp” and use default Advanced settings for the project. Click Finish after you are done to allow CCS to auto generate the project from the template Basic Examples-> Hello World. The Default settings uses “TI CG Tools compiler 8.x.x” tool chain for C66x and sets the build for little endian ELF binary for the C66x core.

5. The generated CCS project contains only one source file hello.c. Ensure the main.c file contains the following code

 /*
 * hello.c
 */
 #include <stdio.h>

 int main(void) {

     printf("Hello_world\n");
     return 0;
}

6. CCSv6 includes a default linker command file(AM57xx_C66.cmd) for the C66x DSP core which will place code into appropriate device memory. The linker command file has the following memory sections.

MEMORY
{
    IRAM_MEM:  o = 0x00800000 l = 0x00008000   /* 32kB internal SRAM */
    OCMC_RAM1: o = 0x40300000 l = 0x00080000   /* 512kB L3 OCMC SRAM1 */
    OCMC_RAM2: o = 0x40400000 l = 0x00100000   /* 1MB L3 OCMC SRAM2 */
    OCMC_RAM3: o = 0x40500000 l = 0x00100000   /* 1MB L3 OCMC SRAM3 */
    DDR0:      o = 0x80000000 l = 0x40000000   /* 1GB external DDR Bank 0 */
}

The linker command file is designed to place code in OCMC memory.

MSMC  :      o=0x0c000000,    l = 0x00600000  /* 6MB Muticore shared memory */

7. Now build the project to generate hello_world_dsp.out.

8. Launch target configurations using your emulator to connect to AM572X EVM as described in the Getting Started Guide

9. In order to wake up the DSP1 core from A15, Go to Menu option Scripts->AM572x_Multicore_Initialization->DSP1SSClkEnable_API. Refer to the Processor_SDK_RTOS_Setup_CCS.

You should see the following log in the Console

CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ...
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ...
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful!
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<---

10. Select and Connect to C66x_DSP1. Load and run hello_world_dsp.out file. You should see Hello World string displayed on console window.

9.9.9. DSP C674x¶

In this article, we take a look at creating bare-metal hello world examples for C674x core using pre-built templates in CCS. As a sample we will use the C6748 LCDK device to describe the steps but the same steps can be used for create hello world examples for C674x cores in the OMAPL13x/C647x/DA8x family of devices.

1. Start CCS and create a work space for generating the project.
2. Click on File menu option and select New–> CCS Project.
3. Select Target as OMAPLx -C674xx and LCDK674x as shown in the image

4. Select C67XX [C6000] DSP setting in the options below and provide name of the project as “hello_world_lcdk674x” and use default Advanced settings for the project. Click Finish after you are done to allow CCS to auto generate the project from the template Basic Examples-> Hello World. The Default settings uses “TI CG Tools compiler 8.x.x” tool chain for C674x and sets the build for little endian ELF binary for the C674x core.

5. The generated CCS project contains only one source file hello.c. Ensure the main.c file contains the following code

 /*
 * hello.c
 */
 #include <stdio.h>

 int main(void) {

     printf("Hello_world\n");
     return 0;
}

6. CCS includes a default linker command file(C6748.cmd) for the C674x DSP core which will place code into appropriate device memory. The linker command file has the following memory sections.

MEMORY
{
    DSPL2ROM     o = 0x00700000  l = 0x00100000   /* 1MB L2 Internal ROM */
    DSPL2RAM     o = 0x00800000  l = 0x00040000   /* 256kB L2 Internal RAM */
    DSPL1PRAM    o = 0x00E00000  l = 0x00008000   /* 32kB L1 Internal Program RAM */
    DSPL1DRAM    o = 0x00F00000  l = 0x00008000   /* 32kB L1 Internal Data RAM */
    SHDSPL2ROM   o = 0x11700000  l = 0x00100000   /* 1MB L2 Shared Internal ROM */
    SHDSPL2RAM   o = 0x11800000  l = 0x00040000   /* 256kB L2 Shared Internal RAM */
    SHDSPL1PRAM  o = 0x11E00000  l = 0x00008000   /* 32kB L1 Shared Internal Program RAM */
    SHDSPL1DRAM  o = 0x11F00000  l = 0x00008000   /* 32kB L1 Shared Internal Data RAM */
    EMIFACS0     o = 0x40000000  l = 0x20000000   /* 512MB SDRAM Data (CS0) */
    EMIFACS2     o = 0x60000000  l = 0x02000000   /* 32MB Async Data (CS2) */
    EMIFACS3     o = 0x62000000  l = 0x02000000   /* 32MB Async Data (CS3) */
    EMIFACS4     o = 0x64000000  l = 0x02000000   /* 32MB Async Data (CS4) */
    EMIFACS5     o = 0x66000000  l = 0x02000000   /* 32MB Async Data (CS5) */
    SHRAM        o = 0x80000000  l = 0x00020000   /* 128kB Shared RAM */
    DDR2         o = 0xC0000000  l = 0x20000000   /* 512MB DDR2 Data */
}

The linker command file is designed to place code in OCMC memory.

 SECTIONS
{
 .text          >  SHRAM
 .stack         >  SHRAM
 .bss           >  SHRAM
  .......
}

7. Now build the project by right clicking on the Project and selecting “Build Project” to generate hello_world_lcdk674x.out.

8. Launch target configurations using your emulator to connect to OMAPLx/C674x LCDK as described in the Getting Started Guide.

9. Developers on OMAPL137/C6747/C6748 can connect directly to the DSP. For OMAPL138 device, you will need to connect to the ARM as this is ARM master boot device and ARM needs to power up the DSP. You should see the following log in the console.

C674X_0: Output:   Target Connected.
C674X_0: Output:    ---------------------------------------------
C674X_0: Output:    Memory Map Cleared.
C674X_0: Output:    ---------------------------------------------
C674X_0: Output:    Memory Map Setup Complete.
C674X_0: Output:    ---------------------------------------------
C674X_0: Output:    PSC Enable Complete.
C674X_0: Output:    ---------------------------------------------
C674X_0: Output:    PLL0 init done for Core:300MHz, EMIFA:25MHz
C674X_0: Output:    DDR initialization is in progress....
C674X_0: Output:    PLL1 init done for DDR:150MHz
C674X_0: Output:    Using DDR2 settings
C674X_0: Output:    DDR2 init for 150 MHz is done
C674X_0: Output:    ---------------------------------------------

11. Select and Connect to C674x. Load and run hello_world_dsp.out file. You should see Hello World string displayed on console window.

9.10.1. Overview¶

This demo showcases a simple video display with Processor SDK RTOS. This demo uses Gravit, a GPL-licensed open-sourced library, to simulate gravity of particles in space.

9.10.2. Version Details¶

Latest version: 1.0.0

Supported platforms: idkAM572x

Available in: Processor SDK RTOS 4.0.0.4

9.10.3. Components Used¶

Open Sourced Libraries:

• Gravit

RTOS Components:

• SYSBIOS
• XDC

Processor SDK RTOS Drivers:

• VPS
• PM
• I2C
• UART
• Board
• OSAL
• CSL

9.10.4. Building the Demo¶

The demo is available pre-built for Processor SDK RTOS version 4.0.0.4 or higher. You must first set up your development environment. Refer to the Processor SDK RTOS Building page for information on setting up your build environment.

The following are steps to clean the demo:

cd [SDK Install Path]/processor_sdk_rtos_[soc]_[version]/demos/gravit
make clean BOARD=idkAM572x

The following are steps to compile the demo:

cd [SDK Install Path]/processor_sdk_rtos_[soc]_[version]/demos/gravit
make BOARD=idkAM572x

9.10.5. Running the Demo¶

You will need the following:

1. Code Composer Studio to load and run the demo. Refer to Processor SDK RTOS Getting Started Guide for installing CCS.
2. idkAM572x board with attached LCD screen
3. USB cable for JTAG and serial terminal (micro USB port)

To load and run the demo:

1. Connect the USB cable from your computer to the idkAM572x’s JTAG port
2. Power on the idkAM572x board. Ensure that no boot mode is entered (do not have SD card loaded or QSPI flashed)
3. Open up a serial terminal for UART communication (Refer to Processor SDK RTOS Getting Started Guide, setup EVM hardware)
4. Open CCS and launch target config file for idkAM572x (Refer to Processor SDK RTOS Setup CCS for setting up CCS)
5. Connect to CortexA15_0
6. Load and launch the demo executable:

[SDK Install Path]/processor_sdk_rtos_[soc]_[version]/demos/gravit/bin/idkAM572x/gravit_a15_0_release.xa15fg

9.10.6. Terminal Screenshot¶

• When launched, you will be prompt for number of particles to simulate. Enter a value up to 1000.
• Use w-a-s-d for display rotation
• Use i-j-k-l for display translation
• Press Esc to end current simulation and display accumulated statistics
• Frames per second (FPS) and floating point operations per second (FLOPS) are displayed on the terminal

Below is a screenshot of the terminal after one simulation:

9.10.7. Display Output¶

• Particles are set to rotate around a gravity center positioned at the center of the LCD screen
• Particles are represented with 3D coordinates, projected to a 2D LCD screen. The projection is simplified such that the camera (or the viewer) does not change display angles.

Below is an example display of a 500-particle simulation:

9.10.8. Useful References¶

Main Gravit website: https://gravit.slowchop.com/

Gravit github: https://github.com/gak/gravit

Physics algorithm behind gravit, Barnes-hut: https://en.wikipedia.org/wiki/Barnes-Hut_simulation

Bresenham’s line algorithm: https://en.wikipedia.org/wiki/Bresenham’s_line_algorithm

9.14.1. Overview¶

This page describes the SimpleLink WiFi Demo provided in the Processor-SDK for RTOS. This demo illustrates the integration of CC3120 BoosterPack and AMIC110 ICE using components in the SDK to provides a low cost WiFi solution for application development.

9.14.2. Supported platforms¶

• iceAMIC110 ( A8 )

9.14.3. Requirements¶

Following are required to run the application:

Hardware

• TI CC3120 BoosterPack
• TI EVM (see list above)
• Blue wires between CC3120 BP and AMIC110 ICE
• Serial UART cable (provided in EVM kit)
• Connection Diagram

• Picture of connected EVMs

Software

• Processor-SDK RTOS 5.1.0 and later
• Code Composer Studio 8.0 and later

9.14.4. Components Used¶

RTOS Components:

• SYS/BIOS
• XDCTools
• Processor SDK RTOS PDK: SPI, UART, GPIO LLDs, OSAL, Board etc.

9.14.5. Software Design¶

The demo implemented a network terminal application to illustrate how the SimpleLink WiFi Plugin for Processor SDK RTOS can be used to provide a low cost solution for Sitara devies (AM3/4/5). The AMIC110 ICE and CC3120 BoosterPack are connected via SPI and GPIO pins. The SPI interface will provide The data and command channels for SimpleLink WiFi Plugin, while the GPIO pins are providing the INT and RESET signals.

The following diagram shows the overview of the demo:

The source files are organized as follows:

└── simplelink-wifi-demo
    ├── bin --> Folder for the executables
    ├── examples --> Demo source code, projectspec file and makefile
    ├── lib --> Folder for SimpleLink WiFi Plugin liraray
    ├── source --> Folder for SimpleLink WiFi Plugin source

9.14.6. How to Build the SimpleLink WiFi Plugin Demo using CCS¶

Please follow below step by step procedure to build the application.

1. Install Code Composer Studio.
2. Install Processor SDK RTOS for the respective platform needed, in a location where CCS expects: (by default $HOME/ti or c:/ti) Refer Processor SDK RTOS Getting Started Guide for details.
3. Open CCS:
4. Click Project–>Import CCS Projects and select network_terminal_AMIC110_ICE_RTOS_ccs under directory : processor_sdk_rtos_<platform>_<version>/demos/simplelink-wifi-demo/
5. Build the application . ( By right clicking on imported project and clicking “Build project”)

9.14.7. How to Build the SimpleLink WiFi Plugin Demo using makefile on Windows¶

Please follow below step by step procedure to build the application.

1. Install Processor SDK RTOS for the respective platform needed, in a location where CCS expects: (by default c:/ti) Refer Processor SDK RTOS Getting Started Guide for details.
2. Under DOS command prompt type:
3. cd processor_sdk_rtos_<platform>_<version>/ folder
4. setupenv.bat
5. cd processor_sdk_rtos_<platform>_<version>/demos/simplelink-wifi-demo/examplesrtos/AMIC110_ICE/demos/network_terminal/tirtos/ccs
6. gmake clean
7. gmake all
8. The executable binary will be generated under processor_sdk_rtos_<platform>_<version>/demos/simplelink-wifi-demo/examplesrtos/AMIC110_ICE/demos/network_terminal/tirtos/ccs and The executable network_terminal.out, boot image files network_terminal.bin and app will be under processor_sdk_rtos_<platform>_<version>/demos/simplelink-wifi-demo/bin/am335x/a8/debug

9.14.8. How to Build the SimpleLink WiFi Plugin Demo using makefile on Linux¶

Please follow below step by step procedure to build the application.

1. Install Processor SDK RTOS for the respective platform needed, in a location where CCS expects: (by default $HOME/ti) Refer Processor SDK RTOS Getting Started Guide for details.
2. Under Linux command prompt type:
3. cd processor_sdk_rtos_<platform>_<version>/ folder
4. source setupenv.sh
5. cd processor_sdk_rtos_<platform>_<version>/demos/simplelink-wifi-demo/examplesrtos/AMIC110_ICE/demos/network_terminal/tirtos/ccs
6. make clean
7. make all
8. The executable binary will be generated under processor_sdk_rtos_<platform>_<version>/demos/simplelink-wifi-demo/examplesrtos/AMIC110_ICE/demos/network_terminal/tirtos/ccs

9.14.9. How to Run the SimpleLink WiFi Plugin Demo using CCS¶

You will need the following:

1. Install Code Composer Studio to load and run the Template Application. Refer to Processor SDK RTOS Getting Started Guide for installing CCS.
2. AMIC110 ICE board
3. JTAG Emulator

To load and run SimpleLink WiFi Plugin Demo:

1. Connect the computer to the JTAG port on the board using the JTAG emulator.
2. Power on the EVM/board. Ensure that no boot mode is entered (do not have SD card loaded or QSPI flashed)
3. Open up a serial terminal for UART communication (Refer to Processor SDK RTOS Getting Started Guide, setup EVM hardware)
4. Open CCS and launch target config file for the EVM (Refer to Processor SDK RTOS Setup CCS for setting up CCS)
5. Connect to the primary core to make sure on connect gels are run A8 core for AM335x
6. Connect to core where the application is expected to run, if not the primary core.
7. Load executable by clicking(“Run –> Load –> Load Program.). Click on Browse Project and select outfile under: <CCS_Workspace>/network_terminal_AMIC110_ICE_RTOS_RTOS_ccs/Debug/network_terminal_AMIC110_ICE_RTOS_RTOS_ccs.out
8. Run application by clicking the Run icon. ( Or Click Run –> Resume)

Now the network terminal demo will run and print progress through the UART.

• The inital display on the UART

• Enter “help” at UART prompt

• Enter “scan -n 10” at UART prompt

• Enter ” wlanconnect -s “dir645” -t WPA/WPA2 -p “12345678” ” at UART prompt

• Enter “ping 192.168.0.1” at UART prompt

9.14.10. How to Run the SimpleLink WiFi Plugin Demo using UART Boot¶

To load and run SimpleLink WiFi Plugin Demo:

1. Connect the J3 to the USB port on a PC via the UART to USB cable.
2. Power on the EVM/board.
3. Open up a serial terminal for UART communication (Refer to Processor SDK RTOS Getting Started Guide, setup EVM hardware)
4. Send the bootloader_boot_uart_a8host_debug.bin under pdk_<platform>_<version>/packages/ti/starterware/binary/bootloader/bin/am335x-evm/gcc using the XMODEM.

1. Upon completion, then send the network_terminal.bin under processor_sdk_rtos_<platform>_<version>/demos/simplelink-wifi-demo/bin/am335x/a8/debug using the XMODEM.

Now the network terminal demo will run and print progress through the UART.

• The inital display on the UART

• Enter “help” at UART prompt

• Enter “scan -n 10” at UART prompt

• Enter ” wlanconnect -s “dir645” -t WPA/WPA2 -p “12345678” ” at UART prompt

• Enter “ping 192.168.0.1” at UART prompt

9.15.1. Overview¶

Gateway is one of the major use-cases in the modern cars. Performance requirements for Gateway applications are ever increasing due to advanced connected car architecture having multiple domain controllers. The CAN - Ethernet gateway demo showcases P2P (Protocol to Protocol) translation i.e. translating data and control information between incompatible networks like Ethernet and CAN for communication on AM65xx device. The demo enables full duplex routing between CAN and Ethernet (CAN to Ethernet & Ethernet to CAN). The gateway demo shows handling of high bandwidth data traffic on Cortex-R5 with low CPU load and latency for bridging application leaving cortex A53 free for application processing.

9.15.2. Architecture Overview¶

The following block diagram shows the various functional blocks & the data flow used in the gateway application. As shown in the diagram the PC Ethernet applications are used for transmitting & receiving the Ethernet frames from/to PC, similarly for CAN message reception & transmission, any compatible CAN tool can be used.

9.15.3. Software Features¶

• Routing application for CAN to Eth and Eth to CAN.
• Network APIs for creating TCP/IP applications.
• CPU load benchmark utils.

9.15.4. Directory Structure¶

The CAN_ETH Gateway demo is located in the Processor SDK RTOS release under the directory path

[SDK Install Path]/processor_sdk_rtos_[soc]_[version]/demos/gateway-demos/can-eth-gateway

Detailed description of the directory structure is given below:

• output - directory contains prebuilt out file and PC tools executables.
• build - directory contains makefiles and SYSBIOS configuration, linker files for build
• pctools - directory contains Ethernet PC tools
• src - Source files for gateway application, utils and network APIs.

9.15.5. Components Used¶

RTOS Components:

• SYSBIOS
• XDC
• NDK

Processor SDK RTOS Drivers:

• EMAC
• NIMU
• UART
• Board
• OSAL
• CSL
• udma
• sciclient

9.15.6. Building the Demo¶

The demo application is built using makefile. Also the demo is available pre-built for Processor SDK RTOS version 5.3.0.0 or higher.

You must first set up your development environment. Refer to the Processor SDK RTOS Building page for information on setting up your build environment.

The following are steps to clean the demo:

cd [SDK Install Path]/processor_sdk_rtos_[soc]_[version]/demos/gateway-demos/can-eth-gateway/build
make clean BOARD=am65xx_idk

The following are steps to compile the demo:

cd [SDK Install Path]/processor_sdk_rtos_[soc]_[version]/demos/gateway-demos/can-eth-gateway/build
make all BOARD=am65xx_idk

9.15.7. Host Applications¶

The PC tools for Ethernet reception and transmission are located under pctools directory. These tools can be built for Linux and Windows.

cd [SDK Install Path]/processor_sdk_rtos_[soc]_[version]/demos/gateway-demos/can-eth-gateway/pctools
make all

9.15.8. Running the Demo¶

You will need the following:

9.15.9. Terminal Screen-shot¶

Below is a terminal output after one simulation:

Board_init success

GatewayApp: BOARD IP address I/F 1: 192.168.1.14

GatewayApp: Starting GATEWAY Tasks...
Gateway Tx: Server listening (port=1000) !!!

GatewayApp: Network Tx socket open done..
Gateway Tx: Server listening (port=2000) !!!

GatewayApp: Network Rx socket open done..
GatewayApp: CrossBar/Interrupt Configuration done.
GatewayApp: MCANSS Revision ID:
GatewayApp: scheme:0x1
GatewayApp: Business Unit:0x2
GatewayApp: Module ID:0x8e0
GatewayApp: RTL Revision:0x5
GatewayApp: Major Revision:0x1
GatewayApp: Custom Revision:0x0
GatewayApp: Minor Revision:0x1
GatewayApp: CAN-FD operation is enabled through E-Fuse.
GatewayApp: Endianess Value: 0x87654321

GatewayApp: MCAN Transmitter app started..

Received 0 Transmitted 0
LOAD: CPU: 0.6% HWI: 0.1%, SWI:0.1%
LOAD: TSK: Gateway Tx: 0.1%
MISC: 0.3%

GatewayApp: CAN stats - Received 500 Transmitted 500
LOAD: CPU: 6.6% HWI: 0.5%, SWI:0.1%
LOAD: TSK: Gateway Rx: 1.6%
LOAD: TSK: Gateway Tx: 0.6%
MISC: 3.8%