3.2.2.11.4. S/W Architecture of System Suspend

3.2.2.11.4.1. Overview

The user can deliberately force the system to a low power state. There are various levels: Suspend to memory (RAM), Suspend to disk, etc. In Upcoming releases we will support even more modes like MCU Only mode, Partial I/O mode, etc.

First, let’s try to understand what we mean by deep sleep. In AM62, Deep Sleep is the state of the SoC in which it is consuming very low power overall yet it is not completely shut off. During Deep Sleep, Certain IPs (depending on power domain to which then belong) will lose register context on suspend. SW should save and restore the context as required across state transitions. DDR is in self- refresh. This mode is primarily used for Suspend to RAM for battery lifetime or backup operation.

Here, we will try to cover the overall high level Software Flow of how the system suspends when a user issues a deep sleep.

3.2.2.11.4.2. System diagram and components

../../../../../_images/AM62x_Deep_Sleep_Flow.png

Above diagram has software sequence for how deep sleep (ie. Suspend to RAM) works on AM25-SK-EVM.

  1. The user first instructs the System to Suspend. This triggers a suspend sequence from linux side (which runs on the A53 cluster of the SoC).

  2. Linux then suspends all the drivers in the order that they are probed. After ensuring that there were no faults in suspending the drivers, linux then issues core system suspend which ultimately is a PSCI system suspend call. Read more about PSCI here

  3. At this point only ATF is running on A53 cores and it does the job of sending a TISCI Message to the TIFS Core telling it to enter deep sleep and then it puts A53 into standby.

  4. The TIFS Core then encrypts and writes the contents of it’s own SRAM to DDR.

  5. Further it stops tick timer, disables interrupts that are not needed, and suspends local drivers. After the above steps it sends TISCI To DM for Suspend Finish and enters WFI.

  6. The DM (Device Manager) who is the final entity in this entire deep sleep sequence. The procedure followed is:

    1. now starts to save it’s own context to DDR
    2. Disable Security IP LPSCs, such as LPSC_SAUL.
    3. Disable non-critical”IP-less” LPSCs, such as LPSC_main_test.
    4. Save MAIN PADCONF MMRs
    5. Save GTC counter and Disable it.
    6. Finally, Suspend OS.

    The OS in this case is the Free RTOS based Device Manager firmware itself. After this step it starts performing final Steps toward completion of Suspend to RAM.

  7. These steps include the following:

    1. Place DDR into Self Refresh
    2. Place USB into reset isolation
    3. Disable all LPSCs in MAIN except Debug, Always ON
    4. Disable all HSDIVs in MAIN_PLL.
    5. Bypass all MAIN PLLs.
    6. Configure selected wake sources, Enable MAIN IO Isolation.
    7. Disable MCU Core LPSCs, PDs
    8. Bypass MCU PLL

  8. Finally, DM R5 Enters WFI with all the other power domains turned OFF except WKUP Always ON. DM in WFI will basically wait for the configured wakeup source to trigger an interrupt that will act as the wakeup signal.