AM243x Motor Control SDK  09.02.00
ICSS SDFM Examples

Table of Contents

This page lists all the examples of ICSSG SDFM available in this SDK. Following sections describe the features available in each of the examples.

The ICSS SDFM driver provides a well defined set of APIs to expose sigma delta interface.

The ICSS SDFM examples invoke these APIs to

  • Set SDFM channels
  • Set Accumulator (ACC) source, Normal Current (NC) Over-sampling Ratio (OSR), Over-current (OC) OSR, Clock source and Clock inversion
  • Enable/disable threshold comparators
  • Set high and low threshold values
  • Enable Zero Cross and set Zero cross threshold value
  • configure normal current sample trigger time (time for read sample)
  • Enable and disable double update
  • Inform firmware to enable SDFM mode
  • Configure and fast detect block
  • Enable PRU load share mode
  • Enable Phase Compensation

Once these steps are executed

  • ICSS SDFM example waits for a interrupt (trigger by SDFM firmware) to read sample data
  • when interrupt occurs, example reads sample data from DMEM and again comes back to waiting loop

SDFM SysConfig

SDFM has SysConfig support to initialize SDFM parameters and configure SDFM pins.

%SDFM SysConfig view

SysConfig is used to configure things mentioned below:

  • Selecting the ICSSG instance. (Tested on ICSSG0)
  • Selecting the ICSSG PRU slice.(Tested on ICSSG0-PRU0)
  • Configuring PINMUX.
  • Channel selection.
  • SDFM Channel parameters initialization
    SDFM Channel parameters SysConfig view
    • Clock parameters Configuration
      SDFM Channel clk parameters SysConfig view
    • Normal Current Configuration
      SDFM Channel Normal Current parameters

    • Comparator configuration
      SDFM Channel Over Current parameters

    • Fast Detect Configuration
      SDFM Channel Fast Detect parameters

    • SD modulator Settings
      SDFM Channel SD modulator parameters

SDFM SysConfig Features

SD Clock Options

ICSSG SDFM driver supports three methods to generate clock which can be fed externally to modulator and SD_CLK pins. All SDFM sdk examples are using SDFM clock generated from eCAP, other two options has some trade-off as you will lose SD channel due to pin conflict.

  • Clock form ICSSG PRU GPO1
  • Clock from ICSSG eCAP
  • Clock from ICSSG IEP

Note: SysConfig only provides the clock selection option. Dividers have to be configured via API calls.

ICSSG PRU GPO1

The PRG<k>_PRU1/0_GPI1 signal (muxed with SD0_D) can be used as SD_CLKOUT when PRU ICSSG generates clock. This is a trade-off as PRU application will lose one SD channel. Based on dividers value API SDFM_configClockFromGPO1 does configuration of PRU registers and enables pru to generate clock.

  • Generated clock comes out on PRG<k>_PRU1/0_GPI1 signal that can be fed externally to modulator and SD_CLK pins
  • Dividers value settings for given PRU core clock and SD clock values
    SD clock (MHz) PRU core clock (MHz) First divider(div0) Second divider(div1) Description
    20 300 15 (0x1C) 1 (0x00) 20 = 300/(15*1)
    20 300 7.5 (0x0E) 2 (0x01) 20 = 300/(7.5*1)
    10 300 15 (0x1C) 2 (0x01) 10 = 300/(15*2)
    5 200 10 (0x) 4 (0x01) 5 = 200/(10*4)

ICSSG eCAP

ICSSG eCAP can be used for SDFM clock generation. Based on divider value API SDFM_configEcap does configuration of eCAP registers and enables eCAP to generate output clock on PRGx_ECAP0_IN_APWM_OUT pin.

  • Generated clock comes out on PRGx_ECAP0_IN_APWM_OUT signal that can be fed externally to modulator and SD_CLK pins
  • Divider value settings for given PRU core clock and SD clock values
    SD clock (MHz) PRU core clock (MHz) divider
    20 300 15
    15 300 20
    10 200 20

ICSSG IEP

ICSSG IEP has Sync0/Sync1 cyclic generation mode to generate clock which can be used for SDFM clock. The generated clock comes out on two pin corresponding SYNC0 and SYNC1. IEP also has SYNC1 delay feature which can be used to define delay between SYNC1 and SYNC0 output.

  • APIs related to IEP SYNC0 and SYNC1 configuration
    API Description Parameters
    SDFM_configIepSyncMode Configures IEP SYNC0 and SYNC1 registers to generate free running clock highPulseWidth: Number of clock cycles SYNC0/1 will be high, periodTime: Period between the rising edges of output clock, syncStartTime: starting time of free running clock
    SDFM_enableIep Enables IEP timer 20
    SDFM_configSync1Delay Defines clock cycles from the start of SYNC0 to the start of SYNC1 delay: Delay before the start of SYNC1
  • SDFM_configIepSyncMode params value configuration for given PRU core clock and SD clock values
    SD clock (MHz) IEP clock (MHz) highPulseWidth periodTime syncStartTime Description
    20 300 6 (7-1) 14 (15-1) Any unsigned integer value IEP clock 300MHz, SD clk = 20Mhz, Div = 300/20 = 15, one period time = 15 IEP cycles, high plus time = 7 IEP cycles
    10 200 9 (10-1) 19 (20-1) Any unsigned integer value IEP clock 300MHz, SD clk = 10Mhz, Div = 200/10 = 20, one period time = 20 IEP cycles, high plus time = 10 IEP cycles (50% duty cycle)

It is a better clock option to handle phase compensation. SDK has an example icss_sdfm_three_channel_with_phase_compensation for showing phase compensation.

Note : There is pin conflict between SDFM channel 8 data PIN and IEP0 SYNC_OUT1

SDFM Channel Clock Configuration

Three parameters needs to configure for each SDFM channel.

  • Clock source: Option to source clock on sdfm channel
  • Clock value: SDFM input clock value
  • Clock inversion: It is a board specific feature that is used to configure the accumulator input clock polarity. Enable this if the input sdfm clock is reverse otherwise keep it inactive

SDFM Channel SINC filter

PRU ICSSG SDFM interface supports three SINC filters to filter SD bit streams.

  • SINC1/SINC2/SINC3
  • Current SDFM firmware uses common SINC filter for comparator as well as data filter.(Different sinc filters for data filter and comparator filter are not supported)

SDFM Channel Normal Current

Normal current is used for SDFM data filter. It has features mentioned below

  • OSR
  • Trigger points: Sampling points in each EPWM cycle
    • First sample point: One time sampling in each EPWM cycle
    • Second sample point: If double update is enabled then SDFM firmware does two times SDFM sampling in each EPWM cycle
  • Continuous mode: SDFM firmware does continuous sampling of SD data once it started.
  • EPWM Synchronization: Synchronization between SDFM and EPWM.

Note:

  • All SDK examples have EPWM synchronization enabled
  • The current PRU firmware imposes certain restrictions, which effectively means that certain normal current features are specific to one axis, so they have to be same for all three SD channels of one axis.
    • Normal current OSR
    • Trigger points
    • EPWM source

SDFM Channel Comparator

Over current is used for comparator filter to detect low threshold, high threshold and zero cross and generate PWM trips. It has features mentioned below

  • OSR
  • High threshold
  • Low threshold
  • Zero Cross detection

SDFM Channel Fast Detect

The Fast Detect is used for fast over current detection and trip generation. It has features mentioned below

  • Fast Detect window size
  • Zero count maximum limit in fast detect window
  • Zero count minimum limit in fast detect window

ICSS SDFM Examples Implementation

Following section describes the flow of the examples.

ICSS SDFM Examples

Important files and directory structure

Folder/Files Description
${SDK_INSTALL_PATH}/examples/current_sense/icss_sdfm_nine_channel_with_continuous_mode Application specific sources for ICSS SDFM for continuous normal current sampling for nine channels
${SDK_INSTALL_PATH}/examples/current_sense/icss_sdfm_nine_channel_load_share_mode Application specific sources for ICSS SDFM for trigger based normal current sampling for nine channels
${SDK_INSTALL_PATH}/examples/current_sense/icss_sdfm_three_channel_single_pru_mode Application specific sources for ICSS SDFM for trigger based normal current sampling for three channels
${SDK_INSTALL_PATH}/examples/current_sense/icss_sdfm_three_channel_with_continuous_mode

Application specific sources for ICSS SDFM for continuous normal current sampling for three channels

${SDK_INSTALL_PATH}/examples/current_sense/icss_sdfm_three_channel_with_phase_compensation Application specific sources for ICSS SDFM with phase compensation
${SDK_INSTALL_PATH}/examples/current_sense Common source for ICSS SDFM applications
${SDK_INSTALL_PATH}/source/current_sense/sdfm
firmware/ Folder containing ICSS SDFM firmware sources
driver/ ICSS SDFM driver source
include/ Folder containing ICSS SDFM structures and APIs declarations

Supported Combinations

Parameter Value
CPU + OS r5fss0-0 freertos
ICSSG ICSSG0
PRU PRU0 (single channel)
PRU0, RTU-PRU0, TXPRU0 (multi channel using three PRUs - load share mode)
Toolchain ti-arm-clang
Board am243x-evm, am243x-lp
Examples folder examples/current_sense

ICSS SDFM Examples Description

Following are different examples for ICSS SDFM:

Example Enabled Features Tested/Supported Features
Basic ICSS SDFM Examples Trigger based Normal current, Over current detection Zero cross detection, Fast detect, Double Update
SDFM Examples with Continuous Normal Current Sampling Continuous normal current sampling Fast detect
SDFM Example With Phase Compensation Trigger based Normal current, Phase compensation, Over current detection

Fast detect, Double Update, Zero cross detection