This example does trigger based normal current sampling. Normal current Over-sampling Ratio (OSR), Over current OSR and Normal current trigger time can be configured by the user. There are two different examples based on number of SDFM channels.

Three Channels

Only one core - PRU is used for this example.

The example does the below:

• Set SDFM channels: Channel 0 - Channel 2
• Configure normal current sample trigger time (time for read sample) and OSR

Nine Channels

Load share mode of PRU-ICSSG is enabled for this example and three cores - RTU-PRU, PRU and TX-PRU are used for this example.

The example does the below

• Enable load share mode
• Set SDFM channels: Channel 0 - Channel 8
• Configure normal current sample trigger time (time for read sample) and OSR

Important files and directory structure

Supported Combinations

Steps to Run the Example

Hardware Prerequisites

Other than the basic EVM setup mentioned in EVM Setup , below additional hardware is required to run this demo

• TIDEP-01015 3 Axis Board
• Interface card connecting EVM and TIDEP-01015 3 Axis
• Signal generator

Note

For more design details of the TIDEP-01015 3 Axis Board, or Interface card connecting EVM and TIDEP-01015 3 Axis, please contact TI via E2E/FAE.

Hardware Setup

Hardware Setup SDFM

SDFM: EVM and 3axis board setup view

Hardware Prerequisities for LP

• AMC1035EVM
• AM243x-LP Board
• Signal generator

LP Hardware Setup

LP Hardware setup

SDFM: LP setup view

Build, load and run

• When using CCS projects to build, import the CCS project and build it using the CCS project menu (see Using SDK with CCS Projects ).
• When using makefiles to build, note the required combination and build using make command (see Using SDK with Makefiles )
• Launch a CCS debug session and run the executable, see CCS Launch, Load and Run

Test Case Description

Test Details	Steps	Pass/Fail Criteria
1. Normal current sample data	1. Run example on supported board	The drawn graph and raw data should look like the attached image
	2. Draw the graph of sdfm_ch0_samples, sdfm_ch1_samples and sdfm_ch2_samples arrays	NC sample data
2. To check raw data for Single Update (64 Normal Current (NC) OSR)	1. Set NC OSR to 64	The drawn graph and raw data should look like the attached image
	2. Set single update trigger time to half of EPWM cycle time
	3. Build and run example
	4. Draw graph for Raw data	Single Update Raw data
3. To check Raw data for Double Update	1. Set NC OSR to 64	The drawn graphs and raw data should look like attached image
	2. Enable double update
	3. Set single update trigger time to 1/4 of EPWM cycle time
	4. Set double update trigger time to 3/4 of EPWM cycle time
	5. Build and run example
	6. Draw graph for Raw data	Double Update Raw data
		The pattern of the graph should be different from the single update graph. It takes 2 samples in one EPWM cycle so the graph pattern should look more like a sine wave compare to single update graph
4. To test SINC1/SINC2/SINC3 filter	1. Set NC OSR to 64	Raw data should have different resolution for different SINC filter
	2. Set accumulator source to SINC1/SINC2/SINC3	SINC3 raw data resolution = OSR *(SINC2 raw data resolution) = OSR*OSR*(SINC1 raw data resolution)
	3. Build and run example
5. To check Threshold comparator and Over current	1. Enable Comparator filter	Trip status bit must be set for the respective pwm trip zone block and TZ_OUT pin must be high
	2. Set High Threshold to 3500 and low threshold to 2500 (low and high threshold value should be configured based on raw data resolution for 16 OSR)
	3. Set Over current OSR to 16	High Low Threshold status bits must be constantly unset and set
	4. Probe PWMm_TZ_OUT pin
	5. Build and run example
	6. Capture signal in Logic analyzer
6. To check NC Samples with Different NC OSR Values	1. Set NC OSR values between 16 to 255	Raw data should have different resolution for different OSR values
	2. Build and run example
	3. Observe resolution of raw data
7. To check NC samples with different sdfm clock values	1. Set NC OSR to 64	Raw data should have different resolution for different sdfm clock values
	2. Set ecap_divider variable in sdfm_example.c file for different sd clock generation
	3. Set Sigma delta clock equal to ecap generated clock
	4. Build and run example
	5. Observe resolution of raw data
8. To check Fast detect	1. Set NC OSR to 64	Trip must be triggered for the respective pwm trip zone block
	2. Enable Fast detect and disable Comparator
	3. Set Fast Detect fields with these values { window size = 4, Zero max = 18, Zero min = 2}	Zero max/min Threshold hit bits must be constantly unset and set
	4. Build and run example	One max/min threshold hit bits must be unset
	5. 1) Observe TZ_OUT PIN. 2) Check zero/one count max & zero/one count min threshold hit bits in memory map
9. To check Zero Cross	1. Enable Comparator filter	Logic analyzer capture should match with this capture
	2. Set Overcurrent (OC) OSR to 16
	3. Enable Zero cross detection
	4. Set zero cross threshold vales to 1700 {value should be between max sampled value and min sampled value for 16 OSR}	Zero cross GPIO behaviour
	5. probe ch0 zero cross GPIO pins and input SD analog signal
	6. Build and run example
	7. Capture signals in logic analyzer
10.Testing with sdfm clock from EPWM	1. Make hardware set up like attached image	All test cases results should match with ECAP test case results
	2. SDFM: Hw set for clock from EPWM
	3. Enable "APP_EPWM1_ENABLE" macro in app_sdfm.c file
	4. Set EPWM1 out put frequency to 12.5MHz or 5MHz in app_sdfm.c file
	5. Set Sigma delta clock equal to EPWM1 output frequency
	6. Build and run example
	7. Test all test cases from 1 to 5 with EPWM clock
11. To test EPWM Synchronization source	1. Set synchronization source to EPWM3	All test cases sh
	2. Set NC OSR to 64	The drawn graph and raw data should look like the attached image
	3. Set single update trigger time to half of EPWM cycle time
	4. Add and configure EPWM3 instance in SysConfig
	5. Build and run example
	6. Draw graph for Raw data	Single Update Raw data
12. To test SDFM clock generation from eCAP	1. Set SDCLK Generation From to eCAP
	2. SDFM Clock to 20MHz	Generated clock should come out on PRGx_ECAP0_IN_APWM_OUT signal
	3. Configure PRGx_ECAP0_IN_APWM_OUT pin inside PRU ICSSG ECAP SysConfig module
	4. Build and run example
13. To test SDFM clock generation from ICSSG PRU GPO1	1. Set SDCLK Generation From to PRU-ICSSG (PRG<k>_PRU1/0_GPI1)
	2. SDFM Clock to 20MHz	Generated clock should come out on PRG<k>_PRU1/0_GPI1 signal
	3. Build and run example
14. To test SDFM clock generation from IEP	1. Set SDCLK Generation From to IEP
	2. SDFM Clock to 20MHz	Generated clock should come out on two pins corresponding SYNC0 and SYNC1
	3. Configure SYNC_OUT0 and SYNC_OUT0 pins inside PRU ICSSG IEP SysConfig module
	4. Build and run example