4.2. PRU ICSS EthernetIP Release Notes

4.2.1. Overview

The PRU-ICSS Ethernet/IP package provides the foundation that facilitate application software development for Ethernet/IP Adapter on TI Sitara Embedded Processors with PRU-ICSS HW IP.

4.2.2. Licensing

Please refer to the software manifest, which outlines the licensing status for all packages included in this release. The manifest can be found on the SDK download page or in the installed directory. The directory structure is shown in the user guide here

4.2.3. Standard Compliance

Compliant to ODVA EtherNet IP Comformance Tests 19.1

4.2.4. Documentation

  • EtherNet IP Datasheet: Data sheet contains information about the capabilities of the solution, certification information (if applicable), memory and pin mux information. It can be found in the ‘docs’ folder in the installation directory. The directory structure is shown in the user guide here
  • Software Manifest: Provides license information on software included in the package. The manifest can be found on the SDK download page or in the installed directory. The directory structure is shown in the user guide here
  • EVM Quick Start Guide: Provides information on hardware setup and running the demonstration application that is loaded on flash. This document is provided as part of the EVM kit.

4.2.4.1. Release 01.00.04

Released November 2023

PRU-ICSS Ethernet/IP package download link : https://www.ti.com/tool/PRU-ICSS-INDUSTRIAL-SW

4.2.4.1.1. What’s New

  • Compliance to Conformance Test Suite v19.1
  • LLDP support in the firmware
  • TMG stack update to version 3.7.0.0
  • Removed support for K2G
  • Bug Fixes

4.2.4.1.2. Features supported

  • Ethernet/IP Capabilities
    • Explicit Messaging and Implicit Messaging
    • UCMM
    • Class 1 and Class 3 Connection
  • Object classes supported
    • Identity Object
    • Message Router Object
    • Assembly Object
    • Connection Manager Object
    • Ethernet Link Object
    • TCP/IP Interface Object
    • QOS Object
    • Device Level Ring Object
  • Supported Connections
    • Exclusive Owner Connection
    • Input Only Connection
    • Listen Only Connection
  • Total CIP connections : 9
    • IO Messaging : 6
    • Explicit Messaging : 3
  • PHY Configuration
    • Duplex : Half/Full/Auto
    • Speed : 10/100/Auto
  • Device Configuration : EDS File
  • QoS scheme : 3-bit VLAN PCP
    • No of levels supported : 8
    • Number of queues : 4. 2 QoS levels per queue
  • Statistics
    • Media counters supported per port
    • Interface counters supported per port
  • Conformance : CT 19.1 compliant
  • Min RPI supported : 1ms
  • Device Level Ring
    • Beacon Based
    • Min. beacon interval : 200 us
    • Min. beacon timeout : 400 us
    • Self configuring
  • PTP/1588
    • Supports Drives Profile : E2E clock.
    • PTP over UDP
    • Transparent Clock supported
    • Ordinary Clock supported
    • Single and Two step clock supported
  • Learning/FDB : Yes
    • 1024 entries per port
    • Learning table on DDR
  • Storm Prevention : Yes. Configurable per port
  • Support for Multicast Filtering
    • Supported on all SoCs
    • Hash Table for faster lookup
    • O(1) complexity

4.2.4.1.3. What is not supported

  • CIP Sync support in stack
  • IEEE 1588 Master support

4.2.4.1.4. PRU-ICSS Firmware Revision

Platform Build Firmware Header Location
AM3/AM4/AMIC110 5.4.2 protocols\ethernetip_adapter\firmware\v1.0
AM57x 5.4.2 protocols\ethernetip_adapter\firmware\v2.1

4.2.4.1.5. Fixed Issues

Record ID Platform Details
PINDSW-3359 AM335x, AM437x AM571x, AM572x DUT reports incorrect topology in case of DLR state change
PINDSW-3360 AM335x, AM437x AM571x, AM572x DUT forward DLR Frames only if a IP address is configured
PINDSW-4635 AM335x, AM437x AM571x, AM572x Invalid receive packet length information in Buffer descriptor when high netwrok load is applied
PINDSW-4651 AM335x, AM437x AM571x, AM572x DLR: Sign On frames are not forwarded when Supervisor switch happens
PINDSW-4966 AM335x, AM437x AM571x, AM572x Switching supervisors on the fly still does not reliably work
PINDSW-5014 AM335x, AM437x AM571x, AM572x TimeSync_drvDisable API does not work everytime
PINDSW-5198 AM335x, AM437x AM571x, AM572x EtherNet/IP Firmware does not process PTP frames if “V1 Compatibility” is set in PTP header
PINDSW-5382 AM335x, AM437x AM571x, AM572x EIP_DLR_processDLRFrame API fails on large DLR Sign-On Frames
PINDSW-6941 AM335x, AM437x AM571x, AM572x Active Supervisor MAC and IP address is not being cleared after the supervisor is disabled.
PINDSW-7027 AMIC110 Ethernet Link Object Test failures in CT19.1 - PHY does not get configured properly in Half Duplex Mode

4.2.4.1.6. Known Issues

This section contains the list of known Issues at the time of making the release.

Record ID Platform Details Workaround
PINDSW-3082 AM571x Ping fails on AM571x board ICSS1 Port1  
PINDSW-7013 AM572x Flash Read not working as expected when loading EthernetIP application from SD card  
PINDSW-7077 AM335x, AM437x AM571x, AM572x Automated ACD Behavior Test V2.4.13 in ODVA Interactive Test Sequencer fails sporadically.  
PINDSW-7014 AM335x, AM43x, AM571x, AM572x New stack supports minimum RPI of 2 ms  

4.2.4.2. Additional Notes

Details of key interface changes in the package from the previous release

Note

Ethernet/IP application on AM64x and AM65x is not supported in this release.

Note

QuickConnect (QC) has been added as an experimental feature in the TMG stack and has not been validated through testing.

NEW OLD Notes/Impact
The Ethernet/IP application uses the TimeSync library from the PROCESSOR-SDK-RTOS package. Therefore, any changes required in the TimeSync driver need to be done in the PDK package inside the PROCESSOR-SDK-RTOS : [PDK_INSTALL_DIR]/pakages/ti/transport/timeSync/include. The [INSTALL-DIR]/protocols/timeSync folder only contains the files required for building the PTPD stack. The Ethernet/IP application used the TimeSync library from the PRU-ICSS-EthernetIP_Adapter package. The [INSTALL-DIR]/protocols/timeSync folder contained the TimeSync driver source and include files for building the TimeSync library.  
The stc folder provided with the application has been renamed to soc. All the soc files required for the ODVA CT19.1 tests are located at [INSTALL-DIR]/examples/ethernetip_adapter/soc The stc files for ODVA Conformance tests were provided with the application in the stc folder.  

The changes for the Target Configuration parameters for this release are as follows.

Target Info:

Vendor ID 1227
Device Type 12
Product Code 335/437/571/572 (depending on the SOC)
Revision 3.7
Inter-Step Delay (ms) 1000

Connection Information:

Exclusive Owner:
T->O Instance : 101 , Size : 10
O->T Instance : 102 , Size : 10
Input Only:
T->O Instance : 101 , Size : 10
O->T Heartbeat : Instance : 199
Listen Only:
T->O Instance : 101 , Size : 10
O->T Heartbeat : Instance : 198
Configuration Data:
Configuration Instance : 103 , Size : 8

The old target configuration parameters were as follows.

Target Info:

Vendor ID 806
Device Type 12
Product Code 1026
Revision 1.1
Inter-Step Delay (ms) 0

Connection Information:

Exclusive Owner:
T->O Instance : 101 , Size : 1
O->T Instance : 102 , Size : 1
Input Only:
T->O Instance : 101 , Size : 1
O->T Heartbeat : Instance : 198
Listen Only:
T->O Instance : 101 , Size : 1
O->T Heartbeat : Instance : 199
Configuration Data:
Configuration Instance : 103 , Size : 0