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MCUSW
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MCUSW
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This file contains generated pre compile configuration file for FLS MCAL driver.
Go to the source code of this file.
| #define NOR_BLOCK_SIZE (131072U) |
FLASH device specific items (note: sizes are in bytes)
| #define NOR_UNIFORM_SECTOR_SIZE (4096U) |
| #define NOR_SECTOR_SIZE (4096U) |
| #define NOR_SIZE (67108864U) |
| #define NOR_NUM_4K_SECTORS (16384U) |
| #define NOR_NUM_SECTORS (NOR_SIZE / NOR_UNIFORM_SECTOR_SIZE) |
| #define NOR_NUM_BLOCKS (NOR_SIZE / NOR_BLOCK_SIZE) |
| #define NOR_PAGE_SIZE (256U) |
| #define NOR_NUM_PAGES_PER_SECTOR (NOR_SECTOR_SIZE / NOR_PAGE_SIZE) |
| #define NOR_NUM_PAGES_PER_BLOCK (NOR_BLOCK_SIZE / NOR_PAGE_SIZE) |
| #define NOR_ERASED_DATA (0xffU) |
| #define NOR_4K_SECT_BOT_END_OFFSET (0x0U) |
| #define NOR_BE_SECTOR_NUM (-1U) |
| #define NOR_CMD_BULK_ERASE (0x60U) |
| #define NOR_CMD_WRREG (0x1U) |
| #define NOR_CMD_WREN (0x6U) |
| #define NOR_CMD_WRDIS (0x0U) |
| #define NOR_CMD_RDSR (0x5U) |
| #define NOR_CMD_RDSR2 (0x0U) |
| #define NOR_CMD_RDREG (0x0U) |
| #define NOR_CMD_RDCR (0x0U) |
| #define NOR_CMD_RDID (0x9fU) |
| #define NOR_CMD_SRSTE (0x66U) |
| #define NOR_CMD_SFRST (0x99U) |
| #define NOR_CMD_BLOCK_ERASE (0xd8U) |
| #define NOR_CMD_SECTOR_ERASE (0x20U) |
| #define NOR_CMD_READ (0x3U) |
| #define NOR_CMD_FAST_READ (0xbU) |
| #define NOR_CMD_OCTAL_READ (0x8bU) |
| #define NOR_CMD_OCTAL_DDR_READ (0x0U) |
| #define NOR_CMD_PAGE_PROG (0x2U) |
| #define NOR_CMD_OCTAL_PROG (0x82U) |
| #define NOR_CMD_WRITE_VCR (0x81U) |
| #define NOR_CMD_READ_VCR (0x85U) |
| #define NOR_VREG_OFFSET (0x0U) |
| #define NOR_NVREG_OFFSET (0x0U) |
| #define NOR_STS1_NVREG_ADDR (0x0U) |
| #define NOR_STS2_NVREG_ADDR (0x0U) |
| #define NOR_CFG1_NVREG_ADDR (0x0U) |
| #define NOR_CFG2_NVREG_ADDR (0x0U) |
| #define NOR_CFG3_NVREG_ADDR (0x0U) |
| #define NOR_CFG4_NVREG_ADDR (0x0U) |
| #define NOR_CFG5_NVREG_ADDR (0x0U) |
| #define NOR_STS1_VREG_ADDR (0x0U) |
| #define NOR_STS2_VREG_ADDR (0x0U) |
| #define NOR_CFG1_VREG_ADDR (0x0U) |
| #define NOR_CFG2_VREG_ADDR (0x0U) |
| #define NOR_CFG3_VREG_ADDR (0x0U) |
| #define NOR_CFG4_VREG_ADDR (0x0U) |
| #define NOR_CFG5_VREG_ADDR (0x0U) |
| #define NOR_RDID_NUM_BYTES (0x3U) |
Read ID command definitions
| #define NOR_MANF_ID (0x2cU) /* Manufacturer ID */ |
| #define NOR_DEVICE_ID (0x5b1aU) /* Device ID */ |
| #define NOR_SR_WIP ((1U) << 0U) |
Status Register: Write-in-Progress bit
| #define NOR_SR_WRPGEN ((1U) << 1U) |
Status Register: Program enabled bit
| #define NOR_CR_TBPARM ((1U) << 2U) |
Configuration Register: TBPARM bit
| #define NOR_CMD_RDCR_VOL (0x85U) |
| #define NOR_CMD_RDCR_NVOL (0xb5U) |
| #define NOR_CMD_OCTAL_O_FAST_RD (0x8bU) |
| #define NOR_CMD_OCTAL_IO_FAST_RD (0xcbU) |
| #define NOR_CMD_OCTAL_FAST_PROG (0x82U) |
| #define NOR_CMD_EXT_OCTAL_FAST_PROG (0xc2U) |
| #define NOR_CMD_QUAD_O_FAST_RD (0x6bU) |
| #define NOR_CMD_QUAD_IO_FAST_RD (0xebU) |
| #define NOR_CMD_QUAD_DDR_O_FAST_RD (0x6dU) |
| #define NOR_CMD_QUAD_FAST_PROG (0x32U) |
| #define NOR_CMD_EXT_QUAD_FAST_PROG (0x38U) |
| #define NOR_CMD_OCTAL_DDR_O_FAST_RD (0x9DU) |
| #define NOR_CMD_OCTAL_DDR_IO_FAST_RD (0xFDU) |
| #define NOR_CMD_READ_ENVCR (0x65U) |
| #define NOR_CMD_WRITE_NVCR (0xb1U) |
| #define NOR_CMD_READ_NVCR (0xb5U) |
| #define NOR_CMD_WRITE_ENVCR (0x61U) |
| #define NOR_SINGLE_READ_DUMMY_CYCLE ((0U)) |
Dummy cycles for various Read operations
| #define NOR_SINGLE_CMD_READ_DUMMY_CYCLE (1U) |
| #define NOR_OCTAL_SDR_CMD_READ_DUMMY_CYCLE (3U) |
| #define NOR_OCTAL_DDR_CMD_READ_DUMMY_CYCLE (4U) |
| #define NOR_OCTAL_READ_DUMMY_CYCLE (30U) |
| #define NOR_OCTAL_READ_DUMMY_CYCLE_LC (0x0U) |
| #define NOR_OCTAL_READ_DUMMY_CYCLE_INDAC (0U) |
| #define NOR_OCTAL_READ_DUMMY_CYCLE_LC_INDAC (0x0U) |
| #define NOR_QUAD_READ_DUMMY_CYCLE (10U) |
| #define NOR_RDID_CMD_LENGTH_SINGLE (0U) |
Read ID Command Lengths
| #define NOR_RDID_CMD_LENGTH_OCTAL (0U) |
| #define NOR_PAGE_PROG_TIMEOUT (400U) |
Timeouts (in microseconds)
| #define NOR_SECTOR_ERASE_TIMEOUT (600000U) |
| #define NOR_WRR_WRITE_TIMEOUT (600000U) |
| #define NOR_BULK_ERASE_TIMEOUT (110000000U) |
1.12.0