Fls_NOR_Device.h

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  /*****************************************************************************
    Project: FLS_J721E
    Date   : 2024-09-30 07:37:25
    This file is generated by EB Tresos
    Do not modify this file, otherwise the software may behave in unexpected way.
 ******************************************************************************/
 
#ifndef FLS_NOR_DEVICE_H_
#define FLS_NOR_DEVICE_H_
 
/**************************************************************************
                            Macro Definitions
 **************************************************************************/
/* Selected Flash M35XU512_3BYTE_ADDRESSING */
 
 
 
/* NOR Block Size in bytes. */ 
#define NOR_BLOCK_SIZE              (131072U)
 
/* NOR Sector Size in bytes  */ 
#define NOR_UNIFORM_SECTOR_SIZE     (4096U)
 
/* NOR Hybrid Sector Size in bytes. Uniform Address space consists of all 256 KB Sectors */
#define NOR_SECTOR_SIZE             (4096U)
 
/* Total NOR Size in bytes */
#define NOR_SIZE                    (67108864U)
 
/* Number of 4K sectors in the NOR flash */
#define NOR_NUM_4K_SECTORS          (16384U)
 
 
/* Total number of sectors in the NOR flash */
#define NOR_NUM_SECTORS             (NOR_SIZE / NOR_UNIFORM_SECTOR_SIZE)
 
 
/* Total number of blocks in the NOR flash */
#define NOR_NUM_BLOCKS              (NOR_SIZE / NOR_BLOCK_SIZE)
 
/* Page size of the NOR flash in bytes */
#define NOR_PAGE_SIZE               (256U)
 
/* Number of pages per sector */
#define NOR_NUM_PAGES_PER_SECTOR    (NOR_SECTOR_SIZE / NOR_PAGE_SIZE)
 
/* Number of pages per block */
#define NOR_NUM_PAGES_PER_BLOCK     (NOR_BLOCK_SIZE / NOR_PAGE_SIZE)
 
/* Value of erased data */
#define NOR_ERASED_DATA             (0xffU)
 
/* Offset for the bottom of the 4K sector */
#define NOR_4K_SECT_BOT_END_OFFSET  (0x0U)
 
/* Number of sectors in the BE (Block Erase) region */
#define NOR_BE_SECTOR_NUM           (-1U)
 
/* Bulk Erase command for the NOR flash */
#define NOR_CMD_BULK_ERASE          (0x60U)
 
/* Write Register command */
#define NOR_CMD_WRREG               (0x1U)
 
/* Write Enable command */
#define NOR_CMD_WREN                (0x6U)
 
/* Write Disable command */
#define NOR_CMD_WRDIS               (0x0U)
 
/* Read Status Register command */
#define NOR_CMD_RDSR                (0x5U)
 
/* Read Status Register 2 command */
#define NOR_CMD_RDSR2               (0x0U)
 
/* Register Read command */
#define NOR_CMD_RDREG               (0x0U)
 
/* Read Configuration Register command */
#define NOR_CMD_RDCR                (0x0U)
 
#define NOR_CMD_RDID                 (0x9fU)
 
/* Software Reset Enable command */
#define NOR_CMD_SRSTE               (0x66U)
 
/* Software Reset command */
#define NOR_CMD_SFRST               (0x99U)
 
/* Block Erase command */
#define NOR_CMD_BLOCK_ERASE         (0xd8U)
 
/* Sector Erase command */
#define NOR_CMD_SECTOR_ERASE        (0x20U)
 
/* Standard Read command */
#define NOR_CMD_READ                (0x3U)
 
/* Fast Read command */
#define NOR_CMD_FAST_READ           (0xbU)
 
/* Octal Read command (calculated based on sector size) */
#define NOR_CMD_OCTAL_READ          (0x8bU)
 
/* Octal DDR Read command (calculated based on NOR size and sector size) */
#define NOR_CMD_OCTAL_DDR_READ      (0x0U)
 
/* Page Program command */
#define NOR_CMD_PAGE_PROG           (0x2U)
 
/* Octal Program command */
#define NOR_CMD_OCTAL_PROG          (0x82U)
 
/* Write VCR (Volatile Configuration Register) command */
#define NOR_CMD_WRITE_VCR           (0x81U)
 
/* Read VCR (Volatile Configuration Register) command */
#define NOR_CMD_READ_VCR            (0x85U)
 
/* Offset for the volatile register */
#define NOR_VREG_OFFSET             (0x0U)
 
/* Offset for the non-volatile register */
#define NOR_NVREG_OFFSET            (0x0U)
 
/* Non-Volatile Status Register 1 address */
#define NOR_STS1_NVREG_ADDR         (0x0U)
 
/* Non-Volatile Status Register 2 address */
#define NOR_STS2_NVREG_ADDR         (0x0U)
 
/* Non-Volatile Configuration Register 1 address */
#define NOR_CFG1_NVREG_ADDR         (0x0U)
 
/* Non-Volatile Configuration Register 2 address */
#define NOR_CFG2_NVREG_ADDR         (0x0U)
 
/* Non-Volatile Configuration Register 3 address */
#define NOR_CFG3_NVREG_ADDR         (0x0U)
 
/* Non-Volatile Configuration Register 4 address */
#define NOR_CFG4_NVREG_ADDR         (0x0U)
 
/* Non-Volatile Configuration Register 5 address */
#define NOR_CFG5_NVREG_ADDR         (0x0U)
 
/* Volatile Status Register 1 address */
#define NOR_STS1_VREG_ADDR          (0x0U)
 
/* Volatile Status Register 2 address */
#define NOR_STS2_VREG_ADDR          (0x0U)
 
/* Volatile Configuration Register 1 address */
#define NOR_CFG1_VREG_ADDR          (0x0U)
 
/* Volatile Configuration Register 2 address */
#define NOR_CFG2_VREG_ADDR          (0x0U)
 
/* Volatile Configuration Register 3 address */
#define NOR_CFG3_VREG_ADDR          (0x0U)
 
/* Volatile Configuration Register 4 address */
#define NOR_CFG4_VREG_ADDR          (0x0U)
 
/* Volatile Configuration Register 5 address */
#define NOR_CFG5_VREG_ADDR         (0x0U)
 
#define NOR_RDID_NUM_BYTES          (0x3U)
#define NOR_MANF_ID                 (0x2cU)  /* Manufacturer ID */
#define NOR_DEVICE_ID               (0x5b1aU)  /* Device ID */
 
#define NOR_SR_WIP                  ((1U) << 0U)
 
#define NOR_SR_WRPGEN               ((1U) << 1U)
 
#define NOR_CR_TBPARM               ((1U) << 2U)
 
#define NOR_CMD_RDCR_VOL             (0x85U)
#define NOR_CMD_RDCR_NVOL            (0xb5U)
#define NOR_CMD_OCTAL_O_FAST_RD      (0x8bU)
#define NOR_CMD_OCTAL_IO_FAST_RD     (0xcbU)
#define NOR_CMD_OCTAL_FAST_PROG      (0x82U)
#define NOR_CMD_EXT_OCTAL_FAST_PROG  (0xc2U)
#define NOR_CMD_QUAD_O_FAST_RD       (0x6bU)
#define NOR_CMD_QUAD_IO_FAST_RD      (0xebU)
#define NOR_CMD_QUAD_DDR_O_FAST_RD   (0x6dU)
#define NOR_CMD_QUAD_FAST_PROG       (0x32U)
#define NOR_CMD_EXT_QUAD_FAST_PROG   (0x38U)
#define NOR_CMD_OCTAL_DDR_O_FAST_RD  (0x9DU)
#define NOR_CMD_OCTAL_DDR_IO_FAST_RD (0xFDU)
 
#define NOR_CMD_READ_ENVCR           (0x65U)
 
#define NOR_CMD_WRITE_NVCR           (0xb1U)
#define NOR_CMD_READ_NVCR            (0xb5U)
#define NOR_CMD_WRITE_ENVCR          (0x61U)
 
#define NOR_SINGLE_READ_DUMMY_CYCLE         ((0U))
#define NOR_SINGLE_CMD_READ_DUMMY_CYCLE     (1U)
#define NOR_OCTAL_SDR_CMD_READ_DUMMY_CYCLE  (3U)
#define NOR_OCTAL_DDR_CMD_READ_DUMMY_CYCLE  (4U)
#define NOR_OCTAL_READ_DUMMY_CYCLE          (30U)
#define NOR_OCTAL_READ_DUMMY_CYCLE_LC       (0x0U)
#define NOR_OCTAL_READ_DUMMY_CYCLE_INDAC    (0U)
#define NOR_OCTAL_READ_DUMMY_CYCLE_LC_INDAC (0x0U)
#define NOR_QUAD_READ_DUMMY_CYCLE           (10U)
 
#define NOR_RDID_CMD_LENGTH_SINGLE          (0U)
#define NOR_RDID_CMD_LENGTH_OCTAL           (0U)
 
#define NOR_PAGE_PROG_TIMEOUT               (400U)
#define NOR_SECTOR_ERASE_TIMEOUT            (600000U)
#define NOR_WRR_WRITE_TIMEOUT               (600000U)
#define NOR_BULK_ERASE_TIMEOUT              (110000000U)
 
 
#endif /* DEVICE_H_ */
 
/* Nothing past this point */